SRAM_CTRL/RET Simulation Results

Wednesday January 03 2024 20:02:50 UTC

GitHub Revision: 748235cbb6

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 25438953283828179064589190240910206115356752103516363191807863392753441298838

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sram_ctrl_smoke 1.915m 1.238ms 48 50 96.00
V1 csr_hw_reset sram_ctrl_csr_hw_reset 0.800s 41.129us 5 5 100.00
V1 csr_rw sram_ctrl_csr_rw 0.720s 16.236us 19 20 95.00
V1 csr_bit_bash sram_ctrl_csr_bit_bash 1.990s 574.510us 5 5 100.00
V1 csr_aliasing sram_ctrl_csr_aliasing 0.710s 17.779us 5 5 100.00
V1 csr_mem_rw_with_rand_reset sram_ctrl_csr_mem_rw_with_rand_reset 3.280s 43.710us 19 20 95.00
V1 regwen_csr_and_corresponding_lockable_csr sram_ctrl_csr_rw 0.720s 16.236us 19 20 95.00
sram_ctrl_csr_aliasing 0.710s 17.779us 5 5 100.00
V1 mem_walk sram_ctrl_mem_walk 11.450s 5.665ms 49 50 98.00
V1 mem_partial_access sram_ctrl_mem_partial_access 5.300s 176.531us 49 50 98.00
V1 TOTAL 199 205 97.07
V2 multiple_keys sram_ctrl_multiple_keys 27.656m 43.955ms 47 50 94.00
V2 stress_pipeline sram_ctrl_stress_pipeline 6.437m 28.437ms 49 50 98.00
V2 bijection sram_ctrl_bijection 1.399m 20.760ms 49 50 98.00
V2 access_during_key_req sram_ctrl_access_during_key_req 39.094m 22.372ms 49 50 98.00
V2 lc_escalation sram_ctrl_lc_escalation 21.650s 739.682us 41 50 82.00
V2 executable sram_ctrl_executable 25.759m 6.928ms 46 50 92.00
V2 partial_access sram_ctrl_partial_access 1.847m 790.929us 50 50 100.00
sram_ctrl_partial_access_b2b 8.875m 21.040ms 45 50 90.00
V2 max_throughput sram_ctrl_max_throughput 2.005m 521.933us 48 50 96.00
sram_ctrl_throughput_w_partial_write 2.097m 595.289us 48 50 96.00
V2 regwen sram_ctrl_regwen 25.338m 28.844ms 49 50 98.00
V2 ram_cfg sram_ctrl_ram_cfg 1.430s 39.601us 46 50 92.00
V2 stress_all sram_ctrl_stress_all 1.188h 252.925ms 46 50 92.00
V2 alert_test sram_ctrl_alert_test 0.720s 21.606us 47 50 94.00
V2 tl_d_oob_addr_access sram_ctrl_tl_errors 4.430s 533.843us 19 20 95.00
V2 tl_d_illegal_access sram_ctrl_tl_errors 4.430s 533.843us 19 20 95.00
V2 tl_d_outstanding_access sram_ctrl_csr_hw_reset 0.800s 41.129us 5 5 100.00
sram_ctrl_csr_rw 0.720s 16.236us 19 20 95.00
sram_ctrl_csr_aliasing 0.710s 17.779us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.790s 49.425us 19 20 95.00
V2 tl_d_partial_access sram_ctrl_csr_hw_reset 0.800s 41.129us 5 5 100.00
sram_ctrl_csr_rw 0.720s 16.236us 19 20 95.00
sram_ctrl_csr_aliasing 0.710s 17.779us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.790s 49.425us 19 20 95.00
V2 TOTAL 698 740 94.32
V2S passthru_mem_tl_intg_err sram_ctrl_passthru_mem_tl_intg_err 10.630s 1.322ms 20 20 100.00
V2S tl_intg_err sram_ctrl_sec_cm 3.400s 442.157us 5 5 100.00
sram_ctrl_tl_intg_err 2.750s 1.012ms 20 20 100.00
V2S prim_count_check sram_ctrl_sec_cm 3.400s 442.157us 5 5 100.00
V2S sec_cm_bus_integrity sram_ctrl_tl_intg_err 2.750s 1.012ms 20 20 100.00
V2S sec_cm_ctrl_config_regwen sram_ctrl_regwen 25.338m 28.844ms 49 50 98.00
V2S sec_cm_exec_config_regwen sram_ctrl_csr_rw 0.720s 16.236us 19 20 95.00
V2S sec_cm_exec_config_mubi sram_ctrl_executable 25.759m 6.928ms 46 50 92.00
V2S sec_cm_exec_intersig_mubi sram_ctrl_executable 25.759m 6.928ms 46 50 92.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi sram_ctrl_executable 25.759m 6.928ms 46 50 92.00
V2S sec_cm_lc_escalate_en_intersig_mubi sram_ctrl_lc_escalation 21.650s 739.682us 41 50 82.00
V2S sec_cm_mem_integrity sram_ctrl_passthru_mem_tl_intg_err 10.630s 1.322ms 20 20 100.00
V2S sec_cm_mem_scramble sram_ctrl_smoke 1.915m 1.238ms 48 50 96.00
V2S sec_cm_addr_scramble sram_ctrl_smoke 1.915m 1.238ms 48 50 96.00
V2S sec_cm_instr_bus_lc_gated sram_ctrl_executable 25.759m 6.928ms 46 50 92.00
V2S sec_cm_ram_tl_lc_gate_fsm_sparse sram_ctrl_sec_cm 3.400s 442.157us 5 5 100.00
V2S sec_cm_key_global_esc sram_ctrl_lc_escalation 21.650s 739.682us 41 50 82.00
V2S sec_cm_key_local_esc sram_ctrl_sec_cm 3.400s 442.157us 5 5 100.00
V2S sec_cm_init_ctr_redun sram_ctrl_sec_cm 3.400s 442.157us 5 5 100.00
V2S sec_cm_scramble_key_sideload sram_ctrl_smoke 1.915m 1.238ms 48 50 96.00
V2S sec_cm_tlul_fifo_ctr_redun sram_ctrl_sec_cm 3.400s 442.157us 5 5 100.00
V2S TOTAL 45 45 100.00
V3 stress_all_with_rand_reset sram_ctrl_stress_all_with_rand_reset 1.683h 2.061ms 47 50 94.00
V3 TOTAL 47 50 94.00
TOTAL 989 1040 95.10

Testplan Progress

Items Total Written Passing Progress
V1 8 8 3 37.50
V2 16 16 1 6.25
V2S 3 3 3 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.65 100.00 98.13 100.00 100.00 99.71 99.70 100.00

Failure Buckets

Past Results