SRAM_CTRL/RET Simulation Results

Sunday March 24 2024 19:02:40 UTC

GitHub Revision: 70ad420931

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 56687816123908180356912499273064417112757374299033127319246303583078997854118

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sram_ctrl_smoke 2.156m 8.537ms 50 50 100.00
V1 csr_hw_reset sram_ctrl_csr_hw_reset 0.700s 15.131us 5 5 100.00
V1 csr_rw sram_ctrl_csr_rw 0.680s 20.568us 20 20 100.00
V1 csr_bit_bash sram_ctrl_csr_bit_bash 2.180s 458.451us 5 5 100.00
V1 csr_aliasing sram_ctrl_csr_aliasing 0.770s 68.758us 5 5 100.00
V1 csr_mem_rw_with_rand_reset sram_ctrl_csr_mem_rw_with_rand_reset 2.380s 41.085us 19 20 95.00
V1 regwen_csr_and_corresponding_lockable_csr sram_ctrl_csr_rw 0.680s 20.568us 20 20 100.00
sram_ctrl_csr_aliasing 0.770s 68.758us 5 5 100.00
V1 mem_walk sram_ctrl_mem_walk 10.610s 1.304ms 50 50 100.00
V1 mem_partial_access sram_ctrl_mem_partial_access 5.660s 1.375ms 50 50 100.00
V1 TOTAL 204 205 99.51
V2 multiple_keys sram_ctrl_multiple_keys 37.742m 25.423ms 49 50 98.00
V2 stress_pipeline sram_ctrl_stress_pipeline 5.942m 29.047ms 50 50 100.00
V2 bijection sram_ctrl_bijection 1.330m 5.403ms 50 50 100.00
V2 access_during_key_req sram_ctrl_access_during_key_req 26.616m 5.585ms 50 50 100.00
V2 lc_escalation sram_ctrl_lc_escalation 11.040s 1.261ms 50 50 100.00
V2 executable sram_ctrl_executable 53.756m 19.223ms 50 50 100.00
V2 partial_access sram_ctrl_partial_access 2.711m 871.368us 50 50 100.00
sram_ctrl_partial_access_b2b 9.573m 103.475ms 50 50 100.00
V2 max_throughput sram_ctrl_max_throughput 2.683m 844.950us 50 50 100.00
sram_ctrl_throughput_w_partial_write 2.580m 577.484us 50 50 100.00
V2 regwen sram_ctrl_regwen 45.841m 30.180ms 50 50 100.00
V2 ram_cfg sram_ctrl_ram_cfg 0.890s 53.524us 50 50 100.00
V2 stress_all sram_ctrl_stress_all 1.642h 133.483ms 48 50 96.00
V2 alert_test sram_ctrl_alert_test 0.740s 104.783us 50 50 100.00
V2 tl_d_oob_addr_access sram_ctrl_tl_errors 5.240s 542.886us 20 20 100.00
V2 tl_d_illegal_access sram_ctrl_tl_errors 5.240s 542.886us 20 20 100.00
V2 tl_d_outstanding_access sram_ctrl_csr_hw_reset 0.700s 15.131us 5 5 100.00
sram_ctrl_csr_rw 0.680s 20.568us 20 20 100.00
sram_ctrl_csr_aliasing 0.770s 68.758us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.820s 84.308us 20 20 100.00
V2 tl_d_partial_access sram_ctrl_csr_hw_reset 0.700s 15.131us 5 5 100.00
sram_ctrl_csr_rw 0.680s 20.568us 20 20 100.00
sram_ctrl_csr_aliasing 0.770s 68.758us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.820s 84.308us 20 20 100.00
V2 TOTAL 737 740 99.59
V2S passthru_mem_tl_intg_err sram_ctrl_passthru_mem_tl_intg_err 4.990s 6.396ms 20 20 100.00
V2S tl_intg_err sram_ctrl_sec_cm 3.290s 244.674us 5 5 100.00
sram_ctrl_tl_intg_err 3.160s 621.883us 20 20 100.00
V2S prim_count_check sram_ctrl_sec_cm 3.290s 244.674us 5 5 100.00
V2S sec_cm_bus_integrity sram_ctrl_tl_intg_err 3.160s 621.883us 20 20 100.00
V2S sec_cm_ctrl_config_regwen sram_ctrl_regwen 45.841m 30.180ms 50 50 100.00
V2S sec_cm_exec_config_regwen sram_ctrl_csr_rw 0.680s 20.568us 20 20 100.00
V2S sec_cm_exec_config_mubi sram_ctrl_executable 53.756m 19.223ms 50 50 100.00
V2S sec_cm_exec_intersig_mubi sram_ctrl_executable 53.756m 19.223ms 50 50 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi sram_ctrl_executable 53.756m 19.223ms 50 50 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi sram_ctrl_lc_escalation 11.040s 1.261ms 50 50 100.00
V2S sec_cm_mem_integrity sram_ctrl_passthru_mem_tl_intg_err 4.990s 6.396ms 20 20 100.00
V2S sec_cm_mem_scramble sram_ctrl_smoke 2.156m 8.537ms 50 50 100.00
V2S sec_cm_addr_scramble sram_ctrl_smoke 2.156m 8.537ms 50 50 100.00
V2S sec_cm_instr_bus_lc_gated sram_ctrl_executable 53.756m 19.223ms 50 50 100.00
V2S sec_cm_ram_tl_lc_gate_fsm_sparse sram_ctrl_sec_cm 3.290s 244.674us 5 5 100.00
V2S sec_cm_key_global_esc sram_ctrl_lc_escalation 11.040s 1.261ms 50 50 100.00
V2S sec_cm_key_local_esc sram_ctrl_sec_cm 3.290s 244.674us 5 5 100.00
V2S sec_cm_init_ctr_redun sram_ctrl_sec_cm 3.290s 244.674us 5 5 100.00
V2S sec_cm_scramble_key_sideload sram_ctrl_smoke 2.156m 8.537ms 50 50 100.00
V2S sec_cm_tlul_fifo_ctr_redun sram_ctrl_sec_cm 3.290s 244.674us 5 5 100.00
V2S TOTAL 45 45 100.00
V3 stress_all_with_rand_reset sram_ctrl_stress_all_with_rand_reset 14.069m 4.197ms 46 50 92.00
V3 TOTAL 46 50 92.00
TOTAL 1032 1040 99.23

Testplan Progress

Items Total Written Passing Progress
V1 8 8 7 87.50
V2 16 16 14 87.50
V2S 3 3 3 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.10 99.81 97.10 100.00 100.00 98.58 99.70 98.52

Failure Buckets

Past Results