SRAM_CTRL/RET Simulation Results

Tuesday March 12 2024 19:02:37 UTC

GitHub Revision: `bc285b7382`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 8078106501385188224785993882809517173695187907049792415947230968390919037084

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	3.390m	761.408us	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.690s	38.496us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.690s	12.327us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.110s	189.138us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.720s	21.508us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.440s	141.014us	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.690s	12.327us	20	20	100.00
		sram_ctrl_csr_aliasing	0.720s	21.508us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	10.890s	681.315us	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	5.720s	684.084us	50	50	100.00
V1		TOTAL			204	205	99.51
V2	multiple_keys	sram_ctrl_multiple_keys	32.562m	32.287ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.228m	3.874ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.333m	10.706ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	24.555m	17.647ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	11.240s	953.886us	43	50	86.00
V2	executable	sram_ctrl_executable	24.369m	265.293ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	3.120m	541.136us	50	50	100.00
		sram_ctrl_partial_access_b2b	9.726m	24.362ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	3.119m	139.343us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.674m	620.417us	50	50	100.00
V2	regwen	sram_ctrl_regwen	37.168m	8.326ms	49	50	98.00
V2	ram_cfg	sram_ctrl_ram_cfg	0.880s	63.445us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.003h	73.896ms	39	50	78.00
V2	alert_test	sram_ctrl_alert_test	0.760s	47.432us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	5.110s	931.611us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	5.110s	931.611us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.690s	38.496us	5	5	100.00
		sram_ctrl_csr_rw	0.690s	12.327us	20	20	100.00
		sram_ctrl_csr_aliasing	0.720s	21.508us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.860s	64.941us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.690s	38.496us	5	5	100.00
		sram_ctrl_csr_rw	0.690s	12.327us	20	20	100.00
		sram_ctrl_csr_aliasing	0.720s	21.508us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.860s	64.941us	20	20	100.00
V2		TOTAL			721	740	97.43
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	3.570s	3.613ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	2.830s	220.152us	5	5	100.00
		sram_ctrl_tl_intg_err	4.000s	3.849ms	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	2.830s	220.152us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	4.000s	3.849ms	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	37.168m	8.326ms	49	50	98.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.690s	12.327us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	24.369m	265.293ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	24.369m	265.293ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	24.369m	265.293ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	11.240s	953.886us	43	50	86.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	3.570s	3.613ms	20	20	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	3.390m	761.408us	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	3.390m	761.408us	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	24.369m	265.293ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	2.830s	220.152us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	11.240s	953.886us	43	50	86.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	2.830s	220.152us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	2.830s	220.152us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	3.390m	761.408us	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	2.830s	220.152us	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	20.825m	7.300ms	43	50	86.00
V3		TOTAL			43	50	86.00
		TOTAL			1013	1040	97.40

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	16	16	13	81.25
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.39	100.00	97.77	100.00	100.00	99.71	99.70	98.52

Failure Buckets

UVM_ERROR (sram_ctrl_scoreboard.sv:405) [scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= * (* [*] vs * [*]) has 12 failures:

Test sram_ctrl_stress_all has 5 failures.

2.sram_ctrl_stress_all.11052337349933275661271889102592572392499163734780714131123906595472884373001
Line 301, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/2.sram_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 7831690469 ps: (sram_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= 6 (7 [0x7] vs 6 [0x6])
  UVM_INFO @ 7831690469 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.sram_ctrl_stress_all.41468234699602291282390631430559700739033802853429133204579061057296526546771
Line 418, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/7.sram_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 14634829520 ps: (sram_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= 6 (7 [0x7] vs 6 [0x6])
  UVM_INFO @ 14634829520 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Test sram_ctrl_lc_escalation has 7 failures.

7.sram_ctrl_lc_escalation.54712843168024219386172189375821229654635102554369632974688615868881386810527
Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/7.sram_ctrl_lc_escalation/latest/run.log

  UVM_ERROR @ 397721395 ps: (sram_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= 6 (7 [0x7] vs 6 [0x6])
  UVM_INFO @ 397721395 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

22.sram_ctrl_lc_escalation.3964061555226572252201604513307334215786426952032417862989947252559983266841
Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/22.sram_ctrl_lc_escalation/latest/run.log

  UVM_ERROR @ 281302973 ps: (sram_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= 6 (7 [0x7] vs 6 [0x6])
  UVM_INFO @ 281302973 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_ERROR (cip_base_vseq.sv:827) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 7 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 7 failures.
  - 1.sram_ctrl_stress_all_with_rand_reset.23292504561526172519022953530339766315593048462967774037880613331463402295539
    Line 436, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/1.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2699394002 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2699394002 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.sram_ctrl_stress_all_with_rand_reset.35090703194556279241112911862188087799641685540510006257823735139754183067212
    Line 293, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/2.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 5832756891 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 5832756891 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.

Offending '(((((((((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))))' has 5 failures:

Test sram_ctrl_stress_all has 5 failures.

14.sram_ctrl_stress_all.72438595873042909881165603210412297891157575542214224030994813074089702600237
Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/14.sram_ctrl_stress_all/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @ 348880276 ps: (tlul_assert.sv:272) [ASSERT FAILED] dDataKnown_A
  UVM_INFO @ 348880276 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

25.sram_ctrl_stress_all.11682309712602792285530087650062253540412233531080388886977934626003444926141
Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/25.sram_ctrl_stress_all/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @  89373477 ps: (tlul_assert.sv:272) [ASSERT FAILED] dDataKnown_A
  UVM_INFO @  89373477 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: * has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 19.sram_ctrl_csr_mem_rw_with_rand_reset.107274830894345133887732344107766927055995426360062839818371691383650467221452
    Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/19.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  93997869 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (12 [0xc] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: 0x9
  UVM_INFO @  93997869 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(!$isunknown(rdata_o))' has 1 failures:
- Test sram_ctrl_stress_all has 1 failures.
  - 44.sram_ctrl_stress_all.34329715877174204005236712902205179703562114965063975575022118588586747142246
    Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/44.sram_ctrl_stress_all/latest/run.log
```
      Offending '(!$isunknown(rdata_o))'
  UVM_ERROR @ 140374409 ps: (prim_fifo_sync.sv:193) [ASSERT FAILED] DataKnown_A
  UVM_INFO @ 140374409 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_regwen has 1 failures.
  - 45.sram_ctrl_regwen.31756922560719404176886702746055838641446810758178104384309575627155594062317
    Line 281, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/45.sram_ctrl_regwen/latest/run.log
```
  UVM_FATAL @ 21104711913 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0x5b24974f
  UVM_INFO @ 21104711913 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```