SRAM_CTRL/RET Simulation Results

Sunday March 17 2024 19:02:52 UTC

GitHub Revision: `c187a82ee8`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 28440605375541353837496064678278045899395893237469128852560697715229879921060

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.279m	198.595us	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.780s	39.552us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.710s	20.847us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.850s	86.625us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.700s	36.510us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.810s	68.099us	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.710s	20.847us	20	20	100.00
		sram_ctrl_csr_aliasing	0.700s	36.510us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	10.950s	2.720ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	5.230s	322.436us	50	50	100.00
V1		TOTAL			204	205	99.51
V2	multiple_keys	sram_ctrl_multiple_keys	30.428m	25.055ms	49	50	98.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	7.278m	9.608ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.398m	11.245ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	37.612m	21.826ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	10.180s	3.698ms	50	50	100.00
V2	executable	sram_ctrl_executable	38.003m	19.984ms	49	50	98.00
V2	partial_access	sram_ctrl_partial_access	2.633m	224.134us	50	50	100.00
		sram_ctrl_partial_access_b2b	9.108m	71.437ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.253m	155.140us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.121m	162.945us	50	50	100.00
V2	regwen	sram_ctrl_regwen	24.829m	19.616ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	0.850s	52.215us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.856h	53.541ms	45	50	90.00
V2	alert_test	sram_ctrl_alert_test	0.830s	24.072us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.750s	830.957us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.750s	830.957us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.780s	39.552us	5	5	100.00
		sram_ctrl_csr_rw	0.710s	20.847us	20	20	100.00
		sram_ctrl_csr_aliasing	0.700s	36.510us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.850s	98.908us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.780s	39.552us	5	5	100.00
		sram_ctrl_csr_rw	0.710s	20.847us	20	20	100.00
		sram_ctrl_csr_aliasing	0.700s	36.510us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.850s	98.908us	20	20	100.00
V2		TOTAL			733	740	99.05
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	4.660s	6.261ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	3.940s	6.113ms	5	5	100.00
		sram_ctrl_tl_intg_err	3.140s	592.660us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	3.940s	6.113ms	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	3.140s	592.660us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	24.829m	19.616ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.710s	20.847us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	38.003m	19.984ms	49	50	98.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	38.003m	19.984ms	49	50	98.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	38.003m	19.984ms	49	50	98.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	10.180s	3.698ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	4.660s	6.261ms	20	20	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.279m	198.595us	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.279m	198.595us	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	38.003m	19.984ms	49	50	98.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	3.940s	6.113ms	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	10.180s	3.698ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	3.940s	6.113ms	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	3.940s	6.113ms	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.279m	198.595us	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	3.940s	6.113ms	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	23.020m	7.721ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			1031	1040	99.13

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	16	16	13	81.25
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.36	100.00	97.77	100.00	100.00	99.71	99.70	98.33

Failure Buckets

Offending '(((((((((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))))' has 4 failures:

Test sram_ctrl_stress_all has 4 failures.

1.sram_ctrl_stress_all.20785677020190329706979096336461802478916280477700554367068990557582734326483
Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/1.sram_ctrl_stress_all/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @  74069113 ps: (tlul_assert.sv:272) [ASSERT FAILED] dDataKnown_A
  UVM_INFO @  74069113 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.sram_ctrl_stress_all.80656317541972923654634681635929930745129214800034511398898629157574751994047
Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/3.sram_ctrl_stress_all/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @  56165247 ps: (tlul_assert.sv:272) [ASSERT FAILED] dDataKnown_A
  UVM_INFO @  56165247 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status reset value: * has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 0.sram_ctrl_csr_mem_rw_with_rand_reset.8054442131546727098691827023426017798201639699969404722845805995854848281336
    Line 280, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/0.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  54749556 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (56 [0x38] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status reset value: 0x0
  UVM_INFO @  54749556 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_executable has 1 failures.
  - 8.sram_ctrl_executable.19893111422809120714800524558352961936718340224588557868957066732847527041368
    Line 278, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/8.sram_ctrl_executable/latest/run.log
```
  UVM_FATAL @ 26217521110 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0x10afb48f
  UVM_INFO @ 26217521110 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(!$isunknown(rdata_o))' has 1 failures:
- Test sram_ctrl_stress_all has 1 failures.
  - 17.sram_ctrl_stress_all.49475083809317947634056765140614393955085562099317770750534716678510901978574
    Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/17.sram_ctrl_stress_all/latest/run.log
```
      Offending '(!$isunknown(rdata_o))'
  UVM_ERROR @ 722335159 ps: (prim_fifo_sync.sv:193) [ASSERT FAILED] DataKnown_A
  UVM_INFO @ 722335159 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_multiple_keys has 1 failures.
  - 18.sram_ctrl_multiple_keys.77762295765624342192381835286556694329377657388371273522067121791057902949577
    Line 310, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/18.sram_ctrl_multiple_keys/latest/run.log
```
  UVM_FATAL @ 160496678028 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0x4b47fe7b
  UVM_INFO @ 160496678028 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:827) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 1 failures.
  - 21.sram_ctrl_stress_all_with_rand_reset.40064664852114258350160017968638052687423103256613375582349458912529780439597
    Line 278, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/21.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2481988782 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2481988782 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```