e844018f2c| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | sram_ctrl_smoke | 0 | 50 | 0.00 | ||
| V1 | csr_hw_reset | sram_ctrl_csr_hw_reset | 0.660s | 16.948us | 5 | 5 | 100.00 |
| V1 | csr_rw | sram_ctrl_csr_rw | 0.740s | 41.189us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | sram_ctrl_csr_bit_bash | 2.080s | 466.910us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | sram_ctrl_csr_aliasing | 0.720s | 38.327us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | sram_ctrl_csr_mem_rw_with_rand_reset | 2.730s | 37.688us | 18 | 20 | 90.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | sram_ctrl_csr_rw | 0.740s | 41.189us | 20 | 20 | 100.00 |
| sram_ctrl_csr_aliasing | 0.720s | 38.327us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | sram_ctrl_mem_walk | 0 | 50 | 0.00 | ||
| V1 | mem_partial_access | sram_ctrl_mem_partial_access | 0 | 50 | 0.00 | ||
| V1 | TOTAL | 53 | 205 | 25.85 | |||
| V2 | multiple_keys | sram_ctrl_multiple_keys | 0 | 50 | 0.00 | ||
| V2 | stress_pipeline | sram_ctrl_stress_pipeline | 0 | 50 | 0.00 | ||
| V2 | bijection | sram_ctrl_bijection | 0 | 50 | 0.00 | ||
| V2 | access_during_key_req | sram_ctrl_access_during_key_req | 0 | 50 | 0.00 | ||
| V2 | lc_escalation | sram_ctrl_lc_escalation | 0 | 50 | 0.00 | ||
| V2 | executable | sram_ctrl_executable | 0 | 50 | 0.00 | ||
| V2 | partial_access | sram_ctrl_partial_access | 0 | 50 | 0.00 | ||
| sram_ctrl_partial_access_b2b | 0 | 50 | 0.00 | ||||
| V2 | max_throughput | sram_ctrl_max_throughput | 0 | 50 | 0.00 | ||
| sram_ctrl_throughput_w_partial_write | 0 | 50 | 0.00 | ||||
| V2 | regwen | sram_ctrl_regwen | 0 | 50 | 0.00 | ||
| V2 | ram_cfg | sram_ctrl_ram_cfg | 0 | 50 | 0.00 | ||
| V2 | stress_all | sram_ctrl_stress_all | 0 | 50 | 0.00 | ||
| V2 | alert_test | sram_ctrl_alert_test | 0 | 50 | 0.00 | ||
| V2 | tl_d_oob_addr_access | sram_ctrl_tl_errors | 4.570s | 127.501us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | sram_ctrl_tl_errors | 4.570s | 127.501us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | sram_ctrl_csr_hw_reset | 0.660s | 16.948us | 5 | 5 | 100.00 |
| sram_ctrl_csr_rw | 0.740s | 41.189us | 20 | 20 | 100.00 | ||
| sram_ctrl_csr_aliasing | 0.720s | 38.327us | 5 | 5 | 100.00 | ||
| sram_ctrl_same_csr_outstanding | 0.830s | 40.674us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | sram_ctrl_csr_hw_reset | 0.660s | 16.948us | 5 | 5 | 100.00 |
| sram_ctrl_csr_rw | 0.740s | 41.189us | 20 | 20 | 100.00 | ||
| sram_ctrl_csr_aliasing | 0.720s | 38.327us | 5 | 5 | 100.00 | ||
| sram_ctrl_same_csr_outstanding | 0.830s | 40.674us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 40 | 740 | 5.41 | |||
| V2S | passthru_mem_tl_intg_err | sram_ctrl_passthru_mem_tl_intg_err | 3.850s | 4.832ms | 20 | 20 | 100.00 |
| V2S | tl_intg_err | sram_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| sram_ctrl_tl_intg_err | 2.380s | 426.678us | 20 | 20 | 100.00 | ||
| V2S | prim_count_check | sram_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_bus_integrity | sram_ctrl_tl_intg_err | 2.380s | 426.678us | 20 | 20 | 100.00 |
| V2S | sec_cm_ctrl_config_regwen | sram_ctrl_regwen | 0 | 50 | 0.00 | ||
| V2S | sec_cm_exec_config_regwen | sram_ctrl_csr_rw | 0.740s | 41.189us | 20 | 20 | 100.00 |
| V2S | sec_cm_exec_config_mubi | sram_ctrl_executable | 0 | 50 | 0.00 | ||
| V2S | sec_cm_exec_intersig_mubi | sram_ctrl_executable | 0 | 50 | 0.00 | ||
| V2S | sec_cm_lc_hw_debug_en_intersig_mubi | sram_ctrl_executable | 0 | 50 | 0.00 | ||
| V2S | sec_cm_lc_escalate_en_intersig_mubi | sram_ctrl_lc_escalation | 0 | 50 | 0.00 | ||
| V2S | sec_cm_mem_integrity | sram_ctrl_passthru_mem_tl_intg_err | 3.850s | 4.832ms | 20 | 20 | 100.00 |
| V2S | sec_cm_mem_scramble | sram_ctrl_smoke | 0 | 50 | 0.00 | ||
| V2S | sec_cm_addr_scramble | sram_ctrl_smoke | 0 | 50 | 0.00 | ||
| V2S | sec_cm_instr_bus_lc_gated | sram_ctrl_executable | 0 | 50 | 0.00 | ||
| V2S | sec_cm_ram_tl_lc_gate_fsm_sparse | sram_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_key_global_esc | sram_ctrl_lc_escalation | 0 | 50 | 0.00 | ||
| V2S | sec_cm_key_local_esc | sram_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_init_ctr_redun | sram_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_scramble_key_sideload | sram_ctrl_smoke | 0 | 50 | 0.00 | ||
| V2S | sec_cm_tlul_fifo_ctr_redun | sram_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | TOTAL | 40 | 45 | 88.89 | |||
| V3 | stress_all_with_rand_reset | sram_ctrl_stress_all_with_rand_reset | 0 | 50 | 0.00 | ||
| V3 | TOTAL | 0 | 50 | 0.00 | |||
| TOTAL | 133 | 1040 | 12.79 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 4 | 50.00 |
| V2 | 16 | 16 | 2 | 12.50 |
| V2S | 3 | 3 | 2 | 66.67 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 47.68 | 25.95 | 32.17 | 70.74 | 0.00 | 28.53 | 98.47 | 77.92 |
launch_task.returncode != *, err: * *:*:* * lswatcher.go:*] Failed to connect to Watcher service in the Envelope (you probably need to import _ "google3/tech/env/go/envelope"): generic::unimplemented: envrpc: no envelope available for service "chubby.googleapis.com" Failure to submit jobs: rpc error: code = Unavailable desc = The service is currently unavailable. has 453 failures:
0.sram_ctrl_smoke.113538680131974431544485495434493200236653873805951607298605993956620066225433
Log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/0.sram_ctrl_smoke/latest/run.log
2.sram_ctrl_smoke.39995900510507387180755139262790680236828745389523784277628957925574921198423
Log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/2.sram_ctrl_smoke/latest/run.log
... and 1 more failures.
0.sram_ctrl_bijection.26156694031892007438223410866677717608840827537781010535289599050860405175476
Log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/0.sram_ctrl_bijection/latest/run.log
2.sram_ctrl_bijection.61790033181856921127684618347680553520708716219836064780535500174443335134174
Log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/2.sram_ctrl_bijection/latest/run.log
... and 1 more failures.
0.sram_ctrl_partial_access.82322422465451840512262571233142632403371306051699946496563793263553554310527
Log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/0.sram_ctrl_partial_access/latest/run.log
2.sram_ctrl_partial_access.89175177298518732716549386475877134683465496130938414997956133446996854006159
Log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/2.sram_ctrl_partial_access/latest/run.log
... and 1 more failures.
0.sram_ctrl_max_throughput.113529436650565041847105193435593854821104112848139178931152295684065154540399
Log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/0.sram_ctrl_max_throughput/latest/run.log
2.sram_ctrl_max_throughput.40750176688100182570203113880671018095324162033862933347243402807351745583968
Log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/2.sram_ctrl_max_throughput/latest/run.log
... and 1 more failures.
0.sram_ctrl_lc_escalation.85698789642414385968828623657047049393951417781397211932528603150275439313713
Log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/0.sram_ctrl_lc_escalation/latest/run.log
2.sram_ctrl_lc_escalation.88997116901614990152791314297475766014980727521284182960898338005117685191627
Log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/2.sram_ctrl_lc_escalation/latest/run.log
... and 1 more failures.
Job killed most likely because its dependent job failed. has 452 failures:
0.sram_ctrl_multiple_keys.10776087975843351922768369437806938141410113533558986316226797772194822803108
Log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/0.sram_ctrl_multiple_keys/latest/run.log
2.sram_ctrl_multiple_keys.112351799678747137154813045389285010245042357071772313646277524415530817309529
Log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/2.sram_ctrl_multiple_keys/latest/run.log
... and 1 more failures.
0.sram_ctrl_stress_pipeline.77261134383707020054611492195292045118554656309086469699478744714060539229381
Log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/0.sram_ctrl_stress_pipeline/latest/run.log
2.sram_ctrl_stress_pipeline.42895599659491456621176580555506966186221234921988562874449471863781385541122
Log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/2.sram_ctrl_stress_pipeline/latest/run.log
... and 1 more failures.
0.sram_ctrl_partial_access_b2b.6073529824632727363434856251069490995202356197609169598441112031401688156418
Log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/0.sram_ctrl_partial_access_b2b/latest/run.log
2.sram_ctrl_partial_access_b2b.33509058547675474541191089839663107833185702935018122852653305548161294799962
Log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/2.sram_ctrl_partial_access_b2b/latest/run.log
... and 1 more failures.
0.sram_ctrl_throughput_w_partial_write.66651011908850856733341658323735504562043685580622768838403654352875943452486
Log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/0.sram_ctrl_throughput_w_partial_write/latest/run.log
2.sram_ctrl_throughput_w_partial_write.47926122434100219374593695053594985603656351362547812435147155222734688873555
Log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/2.sram_ctrl_throughput_w_partial_write/latest/run.log
... and 1 more failures.
0.sram_ctrl_access_during_key_req.86048499829208191082764256750317406305814954991974369306326994042330990745611
Log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/0.sram_ctrl_access_during_key_req/latest/run.log
2.sram_ctrl_access_during_key_req.62622176929793396803802190259801630823485356826871050447124610318331075973306
Log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/2.sram_ctrl_access_during_key_req/latest/run.log
... and 1 more failures.
Exit reason: Error: User command failed Job returned non-zero exit code has 1 failures:
6.sram_ctrl_csr_mem_rw_with_rand_reset.74074713360583302478550718630808414255882669992705246270900739559559321037723
Log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/6.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
[make]: simulate
cd /workspace/6.sram_ctrl_csr_mem_rw_with_rand_reset/latest && /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501427099 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_csr_mem_rw_with_rand_reset.501427099
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Mar 14 12:26 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status reset value: * has 1 failures:
19.sram_ctrl_csr_mem_rw_with_rand_reset.98993649592968287615502410284684461409313209172685737112568323230175876164412
Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/19.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 91315166 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (40 [0x28] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status reset value: 0x0
UVM_INFO @ 91315166 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---