SRAM_CTRL/RET Simulation Results

Tuesday March 19 2024 19:02:40 UTC

GitHub Revision: `f7fc348358`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 93166527750821992054916907919379261408154533955814283538537589225972237641118

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.705m	151.807us	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.710s	19.760us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.710s	31.872us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.300s	524.712us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.750s	23.639us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.780s	67.524us	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.710s	31.872us	20	20	100.00
		sram_ctrl_csr_aliasing	0.750s	23.639us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	12.540s	5.615ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	5.730s	158.338us	50	50	100.00
V1		TOTAL			204	205	99.51
V2	multiple_keys	sram_ctrl_multiple_keys	37.249m	14.176ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.176m	14.901ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.418m	57.699ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	30.180m	5.394ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	9.930s	1.033ms	50	50	100.00
V2	executable	sram_ctrl_executable	29.733m	21.250ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	2.644m	716.339us	50	50	100.00
		sram_ctrl_partial_access_b2b	9.864m	88.879ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.898m	1.584ms	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.685m	861.530us	50	50	100.00
V2	regwen	sram_ctrl_regwen	32.113m	4.131ms	49	50	98.00
V2	ram_cfg	sram_ctrl_ram_cfg	0.900s	106.101us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.681h	62.186ms	44	50	88.00
V2	alert_test	sram_ctrl_alert_test	0.700s	21.034us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.820s	651.401us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.820s	651.401us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.710s	19.760us	5	5	100.00
		sram_ctrl_csr_rw	0.710s	31.872us	20	20	100.00
		sram_ctrl_csr_aliasing	0.750s	23.639us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.820s	46.279us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.710s	19.760us	5	5	100.00
		sram_ctrl_csr_rw	0.710s	31.872us	20	20	100.00
		sram_ctrl_csr_aliasing	0.750s	23.639us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.820s	46.279us	20	20	100.00
V2		TOTAL			733	740	99.05
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	3.640s	2.618ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	4.010s	1.784ms	5	5	100.00
		sram_ctrl_tl_intg_err	2.980s	1.408ms	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	4.010s	1.784ms	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.980s	1.408ms	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	32.113m	4.131ms	49	50	98.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.710s	31.872us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	29.733m	21.250ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	29.733m	21.250ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	29.733m	21.250ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	9.930s	1.033ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	3.640s	2.618ms	20	20	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.705m	151.807us	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.705m	151.807us	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	29.733m	21.250ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	4.010s	1.784ms	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	9.930s	1.033ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	4.010s	1.784ms	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	4.010s	1.784ms	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.705m	151.807us	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	4.010s	1.784ms	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	16.410m	7.915ms	43	50	86.00
V3		TOTAL			43	50	86.00
		TOTAL			1025	1040	98.56

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	16	16	14	87.50
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.39	100.00	97.77	100.00	100.00	99.71	99.70	98.52

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:827) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 7 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 7 failures.
  - 6.sram_ctrl_stress_all_with_rand_reset.1069985734553146840677506565179449425715405460021596954442512058877694813152
    Line 312, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/6.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1545104001 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1545104001 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 11.sram_ctrl_stress_all_with_rand_reset.78718688414670356326984733085607316301906812884812631826262219005405064159646
    Line 310, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/11.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1314675625 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1314675625 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.

Offending '(((((((((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))))' has 5 failures:

Test sram_ctrl_stress_all has 5 failures.

3.sram_ctrl_stress_all.23154800057485903605441137282726823499817954239450311452123678461547969534350
Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/3.sram_ctrl_stress_all/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @ 136761962 ps: (tlul_assert.sv:272) [ASSERT FAILED] dDataKnown_A
  UVM_INFO @ 136761962 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

12.sram_ctrl_stress_all.114216135671457919964585843744636935347652840265259049255297876755076195059528
Line 279, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/12.sram_ctrl_stress_all/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @ 166554720 ps: (tlul_assert.sv:272) [ASSERT FAILED] dDataKnown_A
  UVM_INFO @ 166554720 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: * has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 11.sram_ctrl_csr_mem_rw_with_rand_reset.38954165999128875531485238455672047438139956040431979270727484504542219912156
    Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/11.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  49281594 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (15 [0xf] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: 0x9
  UVM_INFO @  49281594 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_stress_all has 1 failures.
  - 16.sram_ctrl_stress_all.48735124439254658946271135566391616683867779127443483146849159276884673622879
    Line 351, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/16.sram_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 207602241702 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0x7d75cb50
  UVM_INFO @ 207602241702 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_regwen has 1 failures.
  - 41.sram_ctrl_regwen.112197801395923514531251183880076457656687181561524828209012977464458028320718
    Line 275, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/41.sram_ctrl_regwen/latest/run.log
```
  UVM_FATAL @ 10279562633 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0x49c48cfa
  UVM_INFO @ 10279562633 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```