SRAM_CTRL/RET Simulation Results

Thursday March 07 2024 20:02:34 UTC

GitHub Revision: `36c168c253`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 132539995404104259171688804297348475616986265371189902218943342622053800053

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	3.274m	640.762us	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.740s	38.716us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.720s	23.826us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.140s	213.803us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.730s	38.138us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.990s	132.665us	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.720s	23.826us	20	20	100.00
		sram_ctrl_csr_aliasing	0.730s	38.138us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	12.470s	8.699ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	5.640s	680.778us	50	50	100.00
V1		TOTAL			204	205	99.51
V2	multiple_keys	sram_ctrl_multiple_keys	44.291m	83.440ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.899m	4.683ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.370m	49.468ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	24.265m	15.427ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	1.544m	11.896ms	44	50	88.00
V2	executable	sram_ctrl_executable	28.054m	9.492ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	2.591m	229.585us	50	50	100.00
		sram_ctrl_partial_access_b2b	8.440m	226.157ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.652m	157.001us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.904m	1.817ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	35.667m	29.576ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	0.830s	49.228us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.068h	696.883ms	39	50	78.00
V2	alert_test	sram_ctrl_alert_test	0.700s	19.429us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	5.140s	437.838us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	5.140s	437.838us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.740s	38.716us	5	5	100.00
		sram_ctrl_csr_rw	0.720s	23.826us	20	20	100.00
		sram_ctrl_csr_aliasing	0.730s	38.138us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.840s	51.561us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.740s	38.716us	5	5	100.00
		sram_ctrl_csr_rw	0.720s	23.826us	20	20	100.00
		sram_ctrl_csr_aliasing	0.730s	38.138us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.840s	51.561us	20	20	100.00
V2		TOTAL			723	740	97.70
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	3.380s	808.362us	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	2.960s	634.492us	5	5	100.00
		sram_ctrl_tl_intg_err	2.600s	653.157us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	2.960s	634.492us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.600s	653.157us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	35.667m	29.576ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.720s	23.826us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	28.054m	9.492ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	28.054m	9.492ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	28.054m	9.492ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	1.544m	11.896ms	44	50	88.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	3.380s	808.362us	20	20	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	3.274m	640.762us	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	3.274m	640.762us	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	28.054m	9.492ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	2.960s	634.492us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	1.544m	11.896ms	44	50	88.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	2.960s	634.492us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	2.960s	634.492us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	3.274m	640.762us	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	2.960s	634.492us	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	17.446m	2.198ms	45	50	90.00
V3		TOTAL			45	50	90.00
		TOTAL			1017	1040	97.79

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	16	16	14	87.50
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.36	100.00	97.77	100.00	100.00	99.71	99.70	98.33

Failure Buckets

UVM_ERROR (sram_ctrl_scoreboard.sv:405) [scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= * (* [*] vs * [*]) has 14 failures:

Test sram_ctrl_lc_escalation has 6 failures.

1.sram_ctrl_lc_escalation.10048580255546336716012999285368087052496420939990350117858688588184428876217
Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/1.sram_ctrl_lc_escalation/latest/run.log

  UVM_ERROR @ 514159748 ps: (sram_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= 6 (7 [0x7] vs 6 [0x6])
  UVM_INFO @ 514159748 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

25.sram_ctrl_lc_escalation.65172949053296203593819051898705731547477990526817797721998282584361048719975
Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/25.sram_ctrl_lc_escalation/latest/run.log

  UVM_ERROR @  61749743 ps: (sram_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= 6 (7 [0x7] vs 6 [0x6])
  UVM_INFO @  61749743 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Test sram_ctrl_stress_all has 8 failures.

3.sram_ctrl_stress_all.67464400692033521071419904978879930124549543104013230919011592294071910585732
Line 305, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/3.sram_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 5764072083 ps: (sram_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= 6 (7 [0x7] vs 6 [0x6])
  UVM_INFO @ 5764072083 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

9.sram_ctrl_stress_all.56174019421519464377800365015229277967728000627131960802103240570690149906751
Line 355, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/9.sram_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 11116860708 ps: (sram_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= 6 (7 [0x7] vs 6 [0x6])
  UVM_INFO @ 11116860708 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

UVM_ERROR (cip_base_vseq.sv:827) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 5 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 5 failures.
  - 4.sram_ctrl_stress_all_with_rand_reset.109056427848352323221549225286223300065908295032088722870286047851210828446756
    Line 278, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/4.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 611355831 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 611355831 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 24.sram_ctrl_stress_all_with_rand_reset.97814619948791969718173657212398299444369133990921644120884268691157780378828
    Line 292, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/24.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 994798632 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 994798632 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.

Offending '(((((((((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))))' has 2 failures:

Test sram_ctrl_stress_all has 2 failures.

2.sram_ctrl_stress_all.36814711745048061514941588557805511118526118842170921888189662769856593620568
Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/2.sram_ctrl_stress_all/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @ 129950727 ps: (tlul_assert.sv:272) [ASSERT FAILED] dDataKnown_A
  UVM_INFO @ 129950727 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

24.sram_ctrl_stress_all.28802999735220422769436822306066080890847642213192252750701023900352776666117
Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/24.sram_ctrl_stress_all/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @  40883053 ps: (tlul_assert.sv:272) [ASSERT FAILED] dDataKnown_A
  UVM_INFO @  40883053 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: * has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 5.sram_ctrl_csr_mem_rw_with_rand_reset.5449028956854807490844214897472042865276396310610260479747215169296540694974
    Line 280, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/5.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 126844000 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (6 [0x6] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: 0x9
  UVM_INFO @ 126844000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(!$isunknown(rdata_o))' has 1 failures:
- Test sram_ctrl_stress_all has 1 failures.
  - 17.sram_ctrl_stress_all.76103550771953182124168431505916274117454536478434204554561674945180963041166
    Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/17.sram_ctrl_stress_all/latest/run.log
```
      Offending '(!$isunknown(rdata_o))'
  UVM_ERROR @ 253130333 ps: (prim_fifo_sync.sv:193) [ASSERT FAILED] DataKnown_A
  UVM_INFO @ 253130333 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```