SRAM_CTRL/RET Simulation Results

Tuesday March 26 2024 19:03:00 UTC

GitHub Revision: `b111fbcef3`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 29002153775573720681496722306495080473944791482258036550176866636887326742880

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.857m	635.526us	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.740s	40.425us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.720s	135.300us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.210s	673.345us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.740s	65.175us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	3.500s	414.520us	18	20	90.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.720s	135.300us	20	20	100.00
		sram_ctrl_csr_aliasing	0.740s	65.175us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	10.300s	2.608ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	5.620s	179.154us	50	50	100.00
V1		TOTAL			203	205	99.02
V2	multiple_keys	sram_ctrl_multiple_keys	32.320m	18.567ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.337m	8.220ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.289m	7.363ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	30.954m	23.119ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	10.020s	3.088ms	50	50	100.00
V2	executable	sram_ctrl_executable	27.247m	2.905ms	48	50	96.00
V2	partial_access	sram_ctrl_partial_access	2.494m	752.804us	50	50	100.00
		sram_ctrl_partial_access_b2b	8.764m	86.237ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.351m	549.848us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.611m	302.511us	50	50	100.00
V2	regwen	sram_ctrl_regwen	28.955m	62.104ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	0.830s	51.462us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.629h	136.228ms	47	50	94.00
V2	alert_test	sram_ctrl_alert_test	0.700s	28.719us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.990s	578.153us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.990s	578.153us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.740s	40.425us	5	5	100.00
		sram_ctrl_csr_rw	0.720s	135.300us	20	20	100.00
		sram_ctrl_csr_aliasing	0.740s	65.175us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.830s	79.015us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.740s	40.425us	5	5	100.00
		sram_ctrl_csr_rw	0.720s	135.300us	20	20	100.00
		sram_ctrl_csr_aliasing	0.740s	65.175us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.830s	79.015us	20	20	100.00
V2		TOTAL			735	740	99.32
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	3.490s	835.261us	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	3.370s	1.216ms	5	5	100.00
		sram_ctrl_tl_intg_err	3.190s	452.605us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	3.370s	1.216ms	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	3.190s	452.605us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	28.955m	62.104ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.720s	135.300us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	27.247m	2.905ms	48	50	96.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	27.247m	2.905ms	48	50	96.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	27.247m	2.905ms	48	50	96.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	10.020s	3.088ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	3.490s	835.261us	20	20	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.857m	635.526us	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.857m	635.526us	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	27.247m	2.905ms	48	50	96.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	3.370s	1.216ms	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	10.020s	3.088ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	3.370s	1.216ms	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	3.370s	1.216ms	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.857m	635.526us	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	3.370s	1.216ms	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	17.277m	3.719ms	42	50	84.00
V3		TOTAL			42	50	84.00
		TOTAL			1025	1040	98.56

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	16	16	14	87.50
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.09	99.81	97.02	100.00	100.00	98.58	99.70	98.52

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 8 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 8 failures.
  - 0.sram_ctrl_stress_all_with_rand_reset.26879763707069551542736579981890956865759133780671888342582070178479386343866
    Line 424, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/0.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4411582667 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 4411582667 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.sram_ctrl_stress_all_with_rand_reset.14888255649617456134825383276157657173290687713390752044216704507788521706172
    Line 279, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/1.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 603475423 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 603475423 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.

Offending '(((((((((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))))' has 3 failures:

Test sram_ctrl_stress_all has 3 failures.

7.sram_ctrl_stress_all.66931828572455580085926978480752603744858633909136621168640518186110268150830
Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/7.sram_ctrl_stress_all/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @ 1050430671 ps: (tlul_assert.sv:272) [ASSERT FAILED] dDataKnown_A
  UVM_INFO @ 1050430671 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

11.sram_ctrl_stress_all.78671884069777246543669569521368093106714761393248790730334720208074232498205
Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/11.sram_ctrl_stress_all/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @  56529532 ps: (tlul_assert.sv:272) [ASSERT FAILED] dDataKnown_A
  UVM_INFO @  56529532 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: * has 2 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 2 failures.
  - 9.sram_ctrl_csr_mem_rw_with_rand_reset.36316673825778496219813005805980129061835148227835389497322923169694840997668
    Line 280, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/9.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 123649770 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (5 [0x5] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: 0x9
  UVM_INFO @ 123649770 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 16.sram_ctrl_csr_mem_rw_with_rand_reset.25181681663696401022010881512496022637775166883343747709206789238380953399266
    Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/16.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  23809532 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (7 [0x7] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: 0x9
  UVM_INFO @  23809532 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=* has 2 failures:
- Test sram_ctrl_executable has 2 failures.
  - 13.sram_ctrl_executable.112314861829522049932276387291826345447159912848501592054541223983807810497559
    Line 276, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/13.sram_ctrl_executable/latest/run.log
```
  UVM_FATAL @ 19545852848 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0x682923d7
  UVM_INFO @ 19545852848 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 26.sram_ctrl_executable.79490658664119387511565717340172684081793295962686093711450223001106578128278
    Line 306, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/26.sram_ctrl_executable/latest/run.log
```
  UVM_FATAL @ 129669526664 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0x3eca0e74
  UVM_INFO @ 129669526664 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```