SRAM_CTRL/RET Simulation Results

Thursday April 04 2024 19:02:33 UTC

GitHub Revision: `2723ca659d`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 9870132716819564205271541124341458297216848204999383102382742091236484427981

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.453m	144.168us	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.660s	21.198us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.710s	23.795us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.840s	101.456us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.720s	21.836us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	3.350s	60.167us	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.710s	23.795us	20	20	100.00
		sram_ctrl_csr_aliasing	0.720s	21.836us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	10.740s	678.723us	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	5.850s	1.502ms	50	50	100.00
V1		TOTAL			204	205	99.51
V2	multiple_keys	sram_ctrl_multiple_keys	33.507m	77.818ms	49	50	98.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	5.867m	40.831ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.379m	5.215ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	36.131m	8.192ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	9.930s	2.470ms	50	50	100.00
V2	executable	sram_ctrl_executable	35.881m	18.150ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	2.579m	1.351ms	49	50	98.00
		sram_ctrl_partial_access_b2b	8.736m	133.515ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.322m	584.707us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.564m	155.302us	50	50	100.00
V2	regwen	sram_ctrl_regwen	31.492m	8.252ms	49	50	98.00
V2	ram_cfg	sram_ctrl_ram_cfg	0.870s	58.428us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.785h	283.751ms	45	50	90.00
V2	alert_test	sram_ctrl_alert_test	0.710s	49.937us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	5.240s	195.375us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	5.240s	195.375us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.660s	21.198us	5	5	100.00
		sram_ctrl_csr_rw	0.710s	23.795us	20	20	100.00
		sram_ctrl_csr_aliasing	0.720s	21.836us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.850s	172.963us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.660s	21.198us	5	5	100.00
		sram_ctrl_csr_rw	0.710s	23.795us	20	20	100.00
		sram_ctrl_csr_aliasing	0.720s	21.836us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.850s	172.963us	20	20	100.00
V2		TOTAL			732	740	98.92
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	3.590s	1.483ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	3.640s	393.210us	5	5	100.00
		sram_ctrl_tl_intg_err	2.600s	1.413ms	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	3.640s	393.210us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.600s	1.413ms	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	31.492m	8.252ms	49	50	98.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.710s	23.795us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	35.881m	18.150ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	35.881m	18.150ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	35.881m	18.150ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	9.930s	2.470ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	3.590s	1.483ms	20	20	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.453m	144.168us	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.453m	144.168us	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	35.881m	18.150ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	3.640s	393.210us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	9.930s	2.470ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	3.640s	393.210us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	3.640s	393.210us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.453m	144.168us	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	3.640s	393.210us	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	15.623m	2.042ms	41	50	82.00
V3		TOTAL			41	50	82.00
		TOTAL			1022	1040	98.27

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	16	16	12	75.00
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.09	99.81	97.02	100.00	100.00	98.58	99.70	98.52

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 9 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 9 failures.
  - 10.sram_ctrl_stress_all_with_rand_reset.36985552018850203471925020948655262433458235385651632800165817802899290302525
    Line 308, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/10.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1527059779 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1527059779 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 11.sram_ctrl_stress_all_with_rand_reset.80595954471194625608154519788601450184033686490193135932447327239199509349681
    Line 342, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/11.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1837571399 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1837571399 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.

Offending '(((((((((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))))' has 4 failures:

Test sram_ctrl_stress_all has 4 failures.

2.sram_ctrl_stress_all.62779758355457604235680980988077744133550276693172686834743373342035429321165
Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/2.sram_ctrl_stress_all/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @ 231455853 ps: (tlul_assert.sv:272) [ASSERT FAILED] dDataKnown_A
  UVM_INFO @ 231455853 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.sram_ctrl_stress_all.95109282372171096688415993470477289704882096858290084389740849581542959531144
Line 279, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/4.sram_ctrl_stress_all/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @ 824015219 ps: (tlul_assert.sv:272) [ASSERT FAILED] dDataKnown_A
  UVM_INFO @ 824015219 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_multiple_keys has 1 failures.
  - 11.sram_ctrl_multiple_keys.72768884808610252670128954249830508534884763097814081609666171007356318976281
    Line 288, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/11.sram_ctrl_multiple_keys/latest/run.log
```
  UVM_FATAL @ 49659426470 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0x93ebc528
  UVM_INFO @ 49659426470 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: * has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 17.sram_ctrl_csr_mem_rw_with_rand_reset.54056136462734448136894539126351851326700420482800586738509418114962469089168
    Line 280, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/17.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  60166979 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (4 [0x4] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: 0x9
  UVM_INFO @  60166979 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_smoke_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_partial_access has 1 failures.
  - 31.sram_ctrl_partial_access.58174274716429061115719888630367325869076805312807378829029671175321688146911
    Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/31.sram_ctrl_partial_access/latest/run.log
```
  UVM_FATAL @ 10524101273 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x794eee70
  UVM_INFO @ 10524101273 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_regwen has 1 failures.
  - 38.sram_ctrl_regwen.58764127241532311425957145444786333966068925200257646333245897966405962834862
    Line 276, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/38.sram_ctrl_regwen/latest/run.log
```
  UVM_FATAL @ 19043559044 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0xed0a6948
  UVM_INFO @ 19043559044 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(!$isunknown(rdata_o))' has 1 failures:
- Test sram_ctrl_stress_all has 1 failures.
  - 47.sram_ctrl_stress_all.104634077733500572638472376040599366046426415044259299728422311914710283474018
    Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/47.sram_ctrl_stress_all/latest/run.log
```
      Offending '(!$isunknown(rdata_o))'
  UVM_ERROR @  93468531 ps: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
  UVM_INFO @  93468531 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```