SRAM_CTRL/RET Simulation Results

Monday April 15 2024 18:56:04 UTC

GitHub Revision: 9f4903e77a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 40268988864630991006175718979742731758115610160637428218057845043020955930762

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.653m	893.933us	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.710s	40.947us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.710s	25.468us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.070s	1.431ms	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.760s	18.268us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	3.070s	167.220us	18	20	90.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.710s	25.468us	20	20	100.00
		sram_ctrl_csr_aliasing	0.760s	18.268us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	10.640s	678.231us	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	5.620s	152.975us	50	50	100.00
V1		TOTAL			203	205	99.02
V2	multiple_keys	sram_ctrl_multiple_keys	23.685m	77.405ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	7.716m	4.700ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.457m	44.981ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	30.484m	13.481ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	10.190s	858.383us	50	50	100.00
V2	executable	sram_ctrl_executable	23.796m	15.017ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	2.381m	215.006us	50	50	100.00
		sram_ctrl_partial_access_b2b	9.608m	115.131ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.738m	452.604us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.669m	310.623us	50	50	100.00
V2	regwen	sram_ctrl_regwen	28.922m	3.102ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	0.870s	376.294us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.002h	483.754ms	49	50	98.00
V2	alert_test	sram_ctrl_alert_test	0.710s	25.559us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	5.570s	728.937us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	5.570s	728.937us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.710s	40.947us	5	5	100.00
		sram_ctrl_csr_rw	0.710s	25.468us	20	20	100.00
		sram_ctrl_csr_aliasing	0.760s	18.268us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.840s	42.851us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.710s	40.947us	5	5	100.00
		sram_ctrl_csr_rw	0.710s	25.468us	20	20	100.00
		sram_ctrl_csr_aliasing	0.760s	18.268us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.840s	42.851us	20	20	100.00
V2		TOTAL			739	740	99.86
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	5.400s	7.679ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	3.030s	894.900us	5	5	100.00
		sram_ctrl_tl_intg_err	2.500s	1.141ms	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	3.030s	894.900us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.500s	1.141ms	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	28.922m	3.102ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.710s	25.468us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	23.796m	15.017ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	23.796m	15.017ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	23.796m	15.017ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	10.190s	858.383us	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	5.400s	7.679ms	20	20	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.653m	893.933us	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.653m	893.933us	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	23.796m	15.017ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	3.030s	894.900us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	10.190s	858.383us	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	3.030s	894.900us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	3.030s	894.900us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.653m	893.933us	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	3.030s	894.900us	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	12.870m	2.623ms	43	50	86.00
V3		TOTAL			43	50	86.00
		TOTAL			1030	1040	99.04

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	16	16	15	93.75
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.09	99.81	97.02	100.00	100.00	98.58	99.70	98.52

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 6 failures:

  • Test sram_ctrl_stress_all_with_rand_reset has 6 failures.

    • 7.sram_ctrl_stress_all_with_rand_reset.66449525254656144418755500169353612905963784426727955756390469726356286465952
      Line 305, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/7.sram_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 5881057240 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 5881057240 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 13.sram_ctrl_stress_all_with_rand_reset.105827673274334635833598247576236463364577170972862973508527185329058052675905
      Line 351, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/13.sram_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 13972745312 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 13972745312 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 4 more failures.

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.scr_key_valid reset value: * has 1 failures:

  • Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.

    • 2.sram_ctrl_csr_mem_rw_with_rand_reset.20376356672637163684029072730735763516969986496641949223836912613196443805545
      Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/2.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log

        UVM_ERROR @ 155350566 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status.scr_key_valid reset value: 0x0
        UVM_INFO @ 155350566 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=* has 1 failures:

  • Test sram_ctrl_stress_all_with_rand_reset has 1 failures.

    • 8.sram_ctrl_stress_all_with_rand_reset.80425150494826537451959160239561770999940747908243240365142367197121192443121
      Line 330, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/8.sram_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 22867511810 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0x8c7066cb
        UVM_INFO @ 22867511810 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: * has 1 failures:

  • Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.

    • 17.sram_ctrl_csr_mem_rw_with_rand_reset.45947152420339848045323521350863571483443050049609036970100967199534193573221
      Line 280, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/17.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log

        UVM_ERROR @  34357639 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (3 [0x3] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: 0x9
        UVM_INFO @  34357639 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(!$isunknown(rdata_o))' has 1 failures:

  • Test sram_ctrl_stress_all has 1 failures.

    • 39.sram_ctrl_stress_all.71310701025648038032159083306259587094736524475170884685683964369114630283745
      Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/39.sram_ctrl_stress_all/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @ 114367412 ps: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
        UVM_INFO @ 114367412 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2024.04.05_04.39.53
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