9656691e03| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | sram_ctrl_smoke | 2.688m | 630.847us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | sram_ctrl_csr_hw_reset | 0.670s | 40.125us | 5 | 5 | 100.00 |
| V1 | csr_rw | sram_ctrl_csr_rw | 0.690s | 14.433us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | sram_ctrl_csr_bit_bash | 2.150s | 157.761us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | sram_ctrl_csr_aliasing | 0.740s | 18.060us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | sram_ctrl_csr_mem_rw_with_rand_reset | 2.120s | 134.683us | 18 | 20 | 90.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | sram_ctrl_csr_rw | 0.690s | 14.433us | 20 | 20 | 100.00 |
| sram_ctrl_csr_aliasing | 0.740s | 18.060us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | sram_ctrl_mem_walk | 10.540s | 659.848us | 50 | 50 | 100.00 |
| V1 | mem_partial_access | sram_ctrl_mem_partial_access | 5.450s | 1.107ms | 50 | 50 | 100.00 |
| V1 | TOTAL | 203 | 205 | 99.02 | |||
| V2 | multiple_keys | sram_ctrl_multiple_keys | 32.699m | 7.142ms | 50 | 50 | 100.00 |
| V2 | stress_pipeline | sram_ctrl_stress_pipeline | 7.664m | 10.246ms | 50 | 50 | 100.00 |
| V2 | bijection | sram_ctrl_bijection | 1.524m | 62.357ms | 50 | 50 | 100.00 |
| V2 | access_during_key_req | sram_ctrl_access_during_key_req | 37.908m | 5.055ms | 50 | 50 | 100.00 |
| V2 | lc_escalation | sram_ctrl_lc_escalation | 12.380s | 10.743ms | 50 | 50 | 100.00 |
| V2 | executable | sram_ctrl_executable | 29.903m | 135.810ms | 50 | 50 | 100.00 |
| V2 | partial_access | sram_ctrl_partial_access | 2.530m | 273.433us | 50 | 50 | 100.00 |
| sram_ctrl_partial_access_b2b | 9.224m | 82.371ms | 50 | 50 | 100.00 | ||
| V2 | max_throughput | sram_ctrl_max_throughput | 2.215m | 192.999us | 50 | 50 | 100.00 |
| sram_ctrl_throughput_w_partial_write | 2.653m | 629.151us | 50 | 50 | 100.00 | ||
| V2 | regwen | sram_ctrl_regwen | 36.742m | 19.025ms | 50 | 50 | 100.00 |
| V2 | ram_cfg | sram_ctrl_ram_cfg | 0.820s | 83.795us | 50 | 50 | 100.00 |
| V2 | stress_all | sram_ctrl_stress_all | 1.853h | 276.775ms | 41 | 50 | 82.00 |
| V2 | alert_test | sram_ctrl_alert_test | 0.710s | 22.986us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | sram_ctrl_tl_errors | 4.870s | 276.779us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | sram_ctrl_tl_errors | 4.870s | 276.779us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | sram_ctrl_csr_hw_reset | 0.670s | 40.125us | 5 | 5 | 100.00 |
| sram_ctrl_csr_rw | 0.690s | 14.433us | 20 | 20 | 100.00 | ||
| sram_ctrl_csr_aliasing | 0.740s | 18.060us | 5 | 5 | 100.00 | ||
| sram_ctrl_same_csr_outstanding | 0.810s | 82.838us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | sram_ctrl_csr_hw_reset | 0.670s | 40.125us | 5 | 5 | 100.00 |
| sram_ctrl_csr_rw | 0.690s | 14.433us | 20 | 20 | 100.00 | ||
| sram_ctrl_csr_aliasing | 0.740s | 18.060us | 5 | 5 | 100.00 | ||
| sram_ctrl_same_csr_outstanding | 0.810s | 82.838us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 731 | 740 | 98.78 | |||
| V2S | passthru_mem_tl_intg_err | sram_ctrl_passthru_mem_tl_intg_err | 3.990s | 745.430us | 20 | 20 | 100.00 |
| V2S | tl_intg_err | sram_ctrl_sec_cm | 5.680s | 4.546ms | 5 | 5 | 100.00 |
| sram_ctrl_tl_intg_err | 2.850s | 791.397us | 20 | 20 | 100.00 | ||
| V2S | prim_count_check | sram_ctrl_sec_cm | 5.680s | 4.546ms | 5 | 5 | 100.00 |
| V2S | sec_cm_bus_integrity | sram_ctrl_tl_intg_err | 2.850s | 791.397us | 20 | 20 | 100.00 |
| V2S | sec_cm_ctrl_config_regwen | sram_ctrl_regwen | 36.742m | 19.025ms | 50 | 50 | 100.00 |
| V2S | sec_cm_exec_config_regwen | sram_ctrl_csr_rw | 0.690s | 14.433us | 20 | 20 | 100.00 |
| V2S | sec_cm_exec_config_mubi | sram_ctrl_executable | 29.903m | 135.810ms | 50 | 50 | 100.00 |
| V2S | sec_cm_exec_intersig_mubi | sram_ctrl_executable | 29.903m | 135.810ms | 50 | 50 | 100.00 |
| V2S | sec_cm_lc_hw_debug_en_intersig_mubi | sram_ctrl_executable | 29.903m | 135.810ms | 50 | 50 | 100.00 |
| V2S | sec_cm_lc_escalate_en_intersig_mubi | sram_ctrl_lc_escalation | 12.380s | 10.743ms | 50 | 50 | 100.00 |
| V2S | sec_cm_mem_integrity | sram_ctrl_passthru_mem_tl_intg_err | 3.990s | 745.430us | 20 | 20 | 100.00 |
| V2S | sec_cm_mem_scramble | sram_ctrl_smoke | 2.688m | 630.847us | 50 | 50 | 100.00 |
| V2S | sec_cm_addr_scramble | sram_ctrl_smoke | 2.688m | 630.847us | 50 | 50 | 100.00 |
| V2S | sec_cm_instr_bus_lc_gated | sram_ctrl_executable | 29.903m | 135.810ms | 50 | 50 | 100.00 |
| V2S | sec_cm_ram_tl_lc_gate_fsm_sparse | sram_ctrl_sec_cm | 5.680s | 4.546ms | 5 | 5 | 100.00 |
| V2S | sec_cm_key_global_esc | sram_ctrl_lc_escalation | 12.380s | 10.743ms | 50 | 50 | 100.00 |
| V2S | sec_cm_key_local_esc | sram_ctrl_sec_cm | 5.680s | 4.546ms | 5 | 5 | 100.00 |
| V2S | sec_cm_init_ctr_redun | sram_ctrl_sec_cm | 5.680s | 4.546ms | 5 | 5 | 100.00 |
| V2S | sec_cm_scramble_key_sideload | sram_ctrl_smoke | 2.688m | 630.847us | 50 | 50 | 100.00 |
| V2S | sec_cm_tlul_fifo_ctr_redun | sram_ctrl_sec_cm | 5.680s | 4.546ms | 5 | 5 | 100.00 |
| V2S | TOTAL | 45 | 45 | 100.00 | |||
| V3 | stress_all_with_rand_reset | sram_ctrl_stress_all_with_rand_reset | 13.068m | 1.870ms | 45 | 50 | 90.00 |
| V3 | TOTAL | 45 | 50 | 90.00 | |||
| TOTAL | 1024 | 1040 | 98.46 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 7 | 87.50 |
| V2 | 16 | 16 | 15 | 93.75 |
| V2S | 3 | 3 | 3 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 99.08 | 99.81 | 96.99 | 100.00 | 100.00 | 98.57 | 99.70 | 98.52 |
Offending '(((((((((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))))' has 6 failures:
11.sram_ctrl_stress_all.17338455070296210582939853434638460950399750841318190256678614872753910534920
Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/11.sram_ctrl_stress_all/latest/run.log
Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
UVM_ERROR @ 235399370 ps: (tlul_assert.sv:277) [ASSERT FAILED] dDataKnown_A
UVM_INFO @ 235399370 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
24.sram_ctrl_stress_all.100361584784579366731702878431634236359413670417910500233577272616903816897190
Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/24.sram_ctrl_stress_all/latest/run.log
Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
UVM_ERROR @ 174053222 ps: (tlul_assert.sv:277) [ASSERT FAILED] dDataKnown_A
UVM_INFO @ 174053222 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
UVM_ERROR (cip_base_vseq.sv:829) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 5 failures:
2.sram_ctrl_stress_all_with_rand_reset.3883072292862818984393618615832619053408564399591207545988291677164845305996
Line 278, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/2.sram_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 555291114 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 555291114 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.sram_ctrl_stress_all_with_rand_reset.402574681081593439857478347119000358111773859375791364898953922581488610123
Line 304, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/7.sram_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1504416454 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1504416454 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
Offending '(!$isunknown(rdata_o))' has 1 failures:
15.sram_ctrl_stress_all.1128279656177348242809687803255317456200972216922027708455431800279936699885
Line 279, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/15.sram_ctrl_stress_all/latest/run.log
Offending '(!$isunknown(rdata_o))'
UVM_ERROR @ 319077040 ps: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 319077040 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.scr_key_valid reset value: * has 1 failures:
16.sram_ctrl_csr_mem_rw_with_rand_reset.11541030246581931472417170344143273052273921038333256773632668992933462304536
Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/16.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 47506303 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status.scr_key_valid reset value: 0x0
UVM_INFO @ 47506303 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: * has 1 failures:
17.sram_ctrl_csr_mem_rw_with_rand_reset.101377577838472284952352846946898885664315054691092341412568280280741947719482
Line 273, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/17.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 46762456 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (13 [0xd] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: 0x9
UVM_INFO @ 46762456 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=* has 1 failures:
28.sram_ctrl_stress_all.56109953348406468771982680849378861964472739351383010620884571276991571612682
Line 290, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/28.sram_ctrl_stress_all/latest/run.log
UVM_FATAL @ 54240803440 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0xd00c115d
UVM_INFO @ 54240803440 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_smoke_vseq] Timeout waiting tl_access : addr=* has 1 failures:
44.sram_ctrl_stress_all.111361086629172836649605803999022678053275470242541949748032639331029496329121
Line 281, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/44.sram_ctrl_stress_all/latest/run.log
UVM_FATAL @ 13914071069 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0xbfe69921
UVM_INFO @ 13914071069 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---