SRAM_CTRL/RET Simulation Results

Sunday May 12 2024 19:02:35 UTC

GitHub Revision: `69c572b503`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 72674276607041733394622960695970595070180537542023880499199659375034056632550

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.534m	141.287us	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.690s	16.592us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.750s	16.427us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.180s	319.040us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.730s	16.123us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	10.550s	10.004ms	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.750s	16.427us	20	20	100.00
		sram_ctrl_csr_aliasing	0.730s	16.123us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	11.040s	1.183ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	5.490s	2.687ms	50	50	100.00
V1		TOTAL			204	205	99.51
V2	multiple_keys	sram_ctrl_multiple_keys	29.850m	3.022ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.314m	15.811ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.396m	18.394ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	28.392m	32.671ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	11.060s	3.933ms	50	50	100.00
V2	executable	sram_ctrl_executable	41.346m	23.317ms	49	50	98.00
V2	partial_access	sram_ctrl_partial_access	2.838m	642.054us	50	50	100.00
		sram_ctrl_partial_access_b2b	8.968m	22.329ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.393m	911.391us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.674m	155.667us	50	50	100.00
V2	regwen	sram_ctrl_regwen	35.426m	14.346ms	49	50	98.00
V2	ram_cfg	sram_ctrl_ram_cfg	0.860s	61.044us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.562h	321.600ms	44	50	88.00
V2	alert_test	sram_ctrl_alert_test	0.710s	14.571us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.920s	178.478us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.920s	178.478us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.690s	16.592us	5	5	100.00
		sram_ctrl_csr_rw	0.750s	16.427us	20	20	100.00
		sram_ctrl_csr_aliasing	0.730s	16.123us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.800s	28.636us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.690s	16.592us	5	5	100.00
		sram_ctrl_csr_rw	0.750s	16.427us	20	20	100.00
		sram_ctrl_csr_aliasing	0.730s	16.123us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.800s	28.636us	20	20	100.00
V2		TOTAL			732	740	98.92
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	3.620s	1.610ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	3.240s	1.182ms	5	5	100.00
		sram_ctrl_tl_intg_err	3.220s	708.740us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	3.240s	1.182ms	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	3.220s	708.740us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	35.426m	14.346ms	49	50	98.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.750s	16.427us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	41.346m	23.317ms	49	50	98.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	41.346m	23.317ms	49	50	98.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	41.346m	23.317ms	49	50	98.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	11.060s	3.933ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	3.620s	1.610ms	20	20	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.534m	141.287us	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.534m	141.287us	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	41.346m	23.317ms	49	50	98.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	3.240s	1.182ms	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	11.060s	3.933ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	3.240s	1.182ms	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	3.240s	1.182ms	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.534m	141.287us	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	3.240s	1.182ms	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	14.545m	13.344ms	43	50	86.00
V3		TOTAL			43	50	86.00
		TOTAL			1024	1040	98.46

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	16	16	13	81.25
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.08	99.81	96.99	100.00	100.00	98.57	99.70	98.52

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 7 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 7 failures.
  - 5.sram_ctrl_stress_all_with_rand_reset.42102586827439887959240916162012399643111981531217503751826335886273636275233
    Line 316, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/5.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1488601210 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1488601210 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 16.sram_ctrl_stress_all_with_rand_reset.75320543277270096871448031597657113742415021597620349206316087054721314003766
    Line 323, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/16.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1457431626 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1457431626 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.

Offending '(((((((((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))))' has 5 failures:

Test sram_ctrl_stress_all has 5 failures.

20.sram_ctrl_stress_all.34010118039816378322376942851566361238498089566893221053520000058394559454297
Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/20.sram_ctrl_stress_all/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @  32706981 ps: (tlul_assert.sv:277) [ASSERT FAILED] dDataKnown_A
  UVM_INFO @  32706981 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

34.sram_ctrl_stress_all.77238666610118148107205498308850396344025743761807042096409031352306609581820
Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/34.sram_ctrl_stress_all/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @ 1054239022 ps: (tlul_assert.sv:277) [ASSERT FAILED] dDataKnown_A
  UVM_INFO @ 1054239022 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_regwen has 1 failures.
  - 17.sram_ctrl_regwen.108618899730020701858324458181674734286808174229974285681621763706766157803710
    Line 286, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/17.sram_ctrl_regwen/latest/run.log
```
  UVM_FATAL @ 39535933222 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0x7d230b97
  UVM_INFO @ 39535933222 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (sram_ctrl_base_vseq.sv:92) [sram_ctrl_common_vseq] Timed out waiting for initialization done has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 19.sram_ctrl_csr_mem_rw_with_rand_reset.33363607175542910388137119746382156867409879380481476022323410670128499320074
    Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/19.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10003870204 ps: (sram_ctrl_base_vseq.sv:92) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Timed out waiting for initialization done
  UVM_INFO @ 10003870204 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(!$isunknown(rdata_o))' has 1 failures:
- Test sram_ctrl_stress_all has 1 failures.
  - 30.sram_ctrl_stress_all.60390697292537377538138963410075613923159646096371497706289044419308641052822
    Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/30.sram_ctrl_stress_all/latest/run.log
```
      Offending '(!$isunknown(rdata_o))'
  UVM_ERROR @ 499073959 ps: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
  UVM_INFO @ 499073959 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_executable has 1 failures.
  - 31.sram_ctrl_executable.98095772632303722950427301549622641451737412961378572544465286105031458904606
    Line 302, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/31.sram_ctrl_executable/latest/run.log
```
  UVM_FATAL @ 132927176166 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0xde7788f9
  UVM_INFO @ 132927176166 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```