SRAM_CTRL/RET Simulation Results

Monday June 10 2024 23:28:43 UTC

GitHub Revision: a8c9c17a8c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 72227341233107832543509484606850665418885932500709631655793413524197290927900

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sram_ctrl_smoke 2.669m 150.982us 50 50 100.00
V1 csr_hw_reset sram_ctrl_csr_hw_reset 0.740s 27.359us 5 5 100.00
V1 csr_rw sram_ctrl_csr_rw 0.720s 35.591us 20 20 100.00
V1 csr_bit_bash sram_ctrl_csr_bit_bash 1.890s 624.311us 5 5 100.00
V1 csr_aliasing sram_ctrl_csr_aliasing 0.810s 26.178us 5 5 100.00
V1 csr_mem_rw_with_rand_reset sram_ctrl_csr_mem_rw_with_rand_reset 2.860s 47.433us 18 20 90.00
V1 regwen_csr_and_corresponding_lockable_csr sram_ctrl_csr_rw 0.720s 35.591us 20 20 100.00
sram_ctrl_csr_aliasing 0.810s 26.178us 5 5 100.00
V1 mem_walk sram_ctrl_mem_walk 13.760s 13.055ms 50 50 100.00
V1 mem_partial_access sram_ctrl_mem_partial_access 6.480s 1.669ms 50 50 100.00
V1 TOTAL 203 205 99.02
V2 multiple_keys sram_ctrl_multiple_keys 39.255m 5.132ms 49 50 98.00
V2 stress_pipeline sram_ctrl_stress_pipeline 7.391m 36.480ms 50 50 100.00
V2 bijection sram_ctrl_bijection 1.566m 9.559ms 50 50 100.00
V2 access_during_key_req sram_ctrl_access_during_key_req 31.902m 20.388ms 50 50 100.00
V2 lc_escalation sram_ctrl_lc_escalation 10.250s 1.016ms 50 50 100.00
V2 executable sram_ctrl_executable 33.205m 17.716ms 50 50 100.00
V2 partial_access sram_ctrl_partial_access 2.117m 2.773ms 50 50 100.00
sram_ctrl_partial_access_b2b 10.793m 316.290ms 50 50 100.00
V2 max_throughput sram_ctrl_max_throughput 2.682m 530.446us 50 50 100.00
sram_ctrl_throughput_w_partial_write 2.788m 300.612us 50 50 100.00
V2 regwen sram_ctrl_regwen 30.974m 46.632ms 49 50 98.00
V2 ram_cfg sram_ctrl_ram_cfg 0.840s 195.309us 50 50 100.00
V2 stress_all sram_ctrl_stress_all 1.593h 247.251ms 49 50 98.00
V2 alert_test sram_ctrl_alert_test 0.700s 47.227us 50 50 100.00
V2 tl_d_oob_addr_access sram_ctrl_tl_errors 5.460s 615.287us 20 20 100.00
V2 tl_d_illegal_access sram_ctrl_tl_errors 5.460s 615.287us 20 20 100.00
V2 tl_d_outstanding_access sram_ctrl_csr_hw_reset 0.740s 27.359us 5 5 100.00
sram_ctrl_csr_rw 0.720s 35.591us 20 20 100.00
sram_ctrl_csr_aliasing 0.810s 26.178us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.890s 80.956us 20 20 100.00
V2 tl_d_partial_access sram_ctrl_csr_hw_reset 0.740s 27.359us 5 5 100.00
sram_ctrl_csr_rw 0.720s 35.591us 20 20 100.00
sram_ctrl_csr_aliasing 0.810s 26.178us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.890s 80.956us 20 20 100.00
V2 TOTAL 737 740 99.59
V2S passthru_mem_tl_intg_err sram_ctrl_passthru_mem_tl_intg_err 4.830s 1.097ms 20 20 100.00
V2S tl_intg_err sram_ctrl_sec_cm 0.690s 15.961us 0 5 0.00
sram_ctrl_tl_intg_err 2.500s 209.465us 20 20 100.00
V2S prim_count_check sram_ctrl_sec_cm 0.690s 15.961us 0 5 0.00
V2S sec_cm_bus_integrity sram_ctrl_tl_intg_err 2.500s 209.465us 20 20 100.00
V2S sec_cm_ctrl_config_regwen sram_ctrl_regwen 30.974m 46.632ms 49 50 98.00
V2S sec_cm_exec_config_regwen sram_ctrl_csr_rw 0.720s 35.591us 20 20 100.00
V2S sec_cm_exec_config_mubi sram_ctrl_executable 33.205m 17.716ms 50 50 100.00
V2S sec_cm_exec_intersig_mubi sram_ctrl_executable 33.205m 17.716ms 50 50 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi sram_ctrl_executable 33.205m 17.716ms 50 50 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi sram_ctrl_lc_escalation 10.250s 1.016ms 50 50 100.00
V2S sec_cm_mem_integrity sram_ctrl_passthru_mem_tl_intg_err 4.830s 1.097ms 20 20 100.00
V2S sec_cm_mem_readback sram_ctrl_smoke 2.669m 150.982us 50 50 100.00
V2S sec_cm_mem_scramble sram_ctrl_smoke 2.669m 150.982us 50 50 100.00
V2S sec_cm_addr_scramble sram_ctrl_smoke 2.669m 150.982us 50 50 100.00
V2S sec_cm_instr_bus_lc_gated sram_ctrl_executable 33.205m 17.716ms 50 50 100.00
V2S sec_cm_ram_tl_lc_gate_fsm_sparse sram_ctrl_sec_cm 0.690s 15.961us 0 5 0.00
V2S sec_cm_key_global_esc sram_ctrl_lc_escalation 10.250s 1.016ms 50 50 100.00
V2S sec_cm_key_local_esc sram_ctrl_sec_cm 0.690s 15.961us 0 5 0.00
V2S sec_cm_init_ctr_redun sram_ctrl_sec_cm 0.690s 15.961us 0 5 0.00
V2S sec_cm_scramble_key_sideload sram_ctrl_smoke 2.669m 150.982us 50 50 100.00
V2S sec_cm_tlul_fifo_ctr_redun sram_ctrl_sec_cm 0.690s 15.961us 0 5 0.00
V2S TOTAL 40 45 88.89
V3 stress_all_with_rand_reset sram_ctrl_stress_all_with_rand_reset 9.540m 6.961ms 42 50 84.00
V3 TOTAL 42 50 84.00
TOTAL 1022 1040 98.27

Testplan Progress

Items Total Written Passing Progress
V1 8 8 7 87.50
V2 16 16 13 81.25
V2S 3 3 2 66.67
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.33 98.99 92.48 99.31 100.00 95.26 98.38 96.89

Failure Buckets

Past Results