SRAM_CTRL/RET Simulation Results

Thursday June 13 2024 19:02:12 UTC

GitHub Revision: 548a3880d8

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 95435389850697596633112362018639443702533575559488568730544091582583938649085

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sram_ctrl_smoke 2.612m 6.423ms 50 50 100.00
V1 csr_hw_reset sram_ctrl_csr_hw_reset 0.740s 33.242us 5 5 100.00
V1 csr_rw sram_ctrl_csr_rw 0.740s 57.341us 20 20 100.00
V1 csr_bit_bash sram_ctrl_csr_bit_bash 2.170s 1.052ms 5 5 100.00
V1 csr_aliasing sram_ctrl_csr_aliasing 0.830s 147.749us 5 5 100.00
V1 csr_mem_rw_with_rand_reset sram_ctrl_csr_mem_rw_with_rand_reset 2.710s 80.949us 19 20 95.00
V1 regwen_csr_and_corresponding_lockable_csr sram_ctrl_csr_rw 0.740s 57.341us 20 20 100.00
sram_ctrl_csr_aliasing 0.830s 147.749us 5 5 100.00
V1 mem_walk sram_ctrl_mem_walk 15.130s 11.386ms 50 50 100.00
V1 mem_partial_access sram_ctrl_mem_partial_access 6.220s 1.425ms 50 50 100.00
V1 TOTAL 204 205 99.51
V2 multiple_keys sram_ctrl_multiple_keys 38.697m 41.437ms 49 50 98.00
V2 stress_pipeline sram_ctrl_stress_pipeline 7.104m 4.022ms 50 50 100.00
V2 bijection sram_ctrl_bijection 1.545m 16.735ms 50 50 100.00
V2 access_during_key_req sram_ctrl_access_during_key_req 31.263m 10.147ms 50 50 100.00
V2 lc_escalation sram_ctrl_lc_escalation 10.710s 917.148us 50 50 100.00
V2 executable sram_ctrl_executable 28.442m 29.403ms 50 50 100.00
V2 partial_access sram_ctrl_partial_access 2.974m 713.878us 50 50 100.00
sram_ctrl_partial_access_b2b 10.461m 25.780ms 50 50 100.00
V2 max_throughput sram_ctrl_max_throughput 2.743m 139.058us 50 50 100.00
sram_ctrl_throughput_w_partial_write 2.536m 151.459us 50 50 100.00
V2 regwen sram_ctrl_regwen 34.116m 20.396ms 50 50 100.00
V2 ram_cfg sram_ctrl_ram_cfg 0.920s 88.889us 50 50 100.00
V2 stress_all sram_ctrl_stress_all 1.447h 357.319ms 47 50 94.00
V2 alert_test sram_ctrl_alert_test 0.710s 36.458us 50 50 100.00
V2 tl_d_oob_addr_access sram_ctrl_tl_errors 5.170s 270.869us 20 20 100.00
V2 tl_d_illegal_access sram_ctrl_tl_errors 5.170s 270.869us 20 20 100.00
V2 tl_d_outstanding_access sram_ctrl_csr_hw_reset 0.740s 33.242us 5 5 100.00
sram_ctrl_csr_rw 0.740s 57.341us 20 20 100.00
sram_ctrl_csr_aliasing 0.830s 147.749us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.830s 75.206us 20 20 100.00
V2 tl_d_partial_access sram_ctrl_csr_hw_reset 0.740s 33.242us 5 5 100.00
sram_ctrl_csr_rw 0.740s 57.341us 20 20 100.00
sram_ctrl_csr_aliasing 0.830s 147.749us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.830s 75.206us 20 20 100.00
V2 TOTAL 736 740 99.46
V2S passthru_mem_tl_intg_err sram_ctrl_passthru_mem_tl_intg_err 4.850s 6.283ms 20 20 100.00
V2S tl_intg_err sram_ctrl_sec_cm 3.180s 669.175us 5 5 100.00
sram_ctrl_tl_intg_err 2.650s 2.563ms 20 20 100.00
V2S prim_count_check sram_ctrl_sec_cm 3.180s 669.175us 5 5 100.00
V2S sec_cm_bus_integrity sram_ctrl_tl_intg_err 2.650s 2.563ms 20 20 100.00
V2S sec_cm_ctrl_config_regwen sram_ctrl_regwen 34.116m 20.396ms 50 50 100.00
V2S sec_cm_exec_config_regwen sram_ctrl_csr_rw 0.740s 57.341us 20 20 100.00
V2S sec_cm_exec_config_mubi sram_ctrl_executable 28.442m 29.403ms 50 50 100.00
V2S sec_cm_exec_intersig_mubi sram_ctrl_executable 28.442m 29.403ms 50 50 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi sram_ctrl_executable 28.442m 29.403ms 50 50 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi sram_ctrl_lc_escalation 10.710s 917.148us 50 50 100.00
V2S sec_cm_mem_integrity sram_ctrl_passthru_mem_tl_intg_err 4.850s 6.283ms 20 20 100.00
V2S sec_cm_mem_readback sram_ctrl_smoke 2.612m 6.423ms 50 50 100.00
V2S sec_cm_mem_scramble sram_ctrl_smoke 2.612m 6.423ms 50 50 100.00
V2S sec_cm_addr_scramble sram_ctrl_smoke 2.612m 6.423ms 50 50 100.00
V2S sec_cm_instr_bus_lc_gated sram_ctrl_executable 28.442m 29.403ms 50 50 100.00
V2S sec_cm_ram_tl_lc_gate_fsm_sparse sram_ctrl_sec_cm 3.180s 669.175us 5 5 100.00
V2S sec_cm_key_global_esc sram_ctrl_lc_escalation 10.710s 917.148us 50 50 100.00
V2S sec_cm_key_local_esc sram_ctrl_sec_cm 3.180s 669.175us 5 5 100.00
V2S sec_cm_init_ctr_redun sram_ctrl_sec_cm 3.180s 669.175us 5 5 100.00
V2S sec_cm_scramble_key_sideload sram_ctrl_smoke 2.612m 6.423ms 50 50 100.00
V2S sec_cm_tlul_fifo_ctr_redun sram_ctrl_sec_cm 3.180s 669.175us 5 5 100.00
V2S TOTAL 45 45 100.00
V3 stress_all_with_rand_reset sram_ctrl_stress_all_with_rand_reset 11.778m 2.298ms 47 50 94.00
V3 TOTAL 47 50 94.00
TOTAL 1032 1040 99.23

Testplan Progress

Items Total Written Passing Progress
V1 8 8 7 87.50
V2 16 16 14 87.50
V2S 3 3 3 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.98 99.16 94.27 99.72 100.00 95.95 99.12 97.62

Failure Buckets

Past Results