SRAM_CTRL/RET Simulation Results

Friday June 21 2024 23:02:45 UTC

GitHub Revision: de38ce313c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 40294666978553523170681160506532247841705182588034413483474981853853670477454

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sram_ctrl_smoke 2.030m 3.911ms 50 50 100.00
V1 csr_hw_reset sram_ctrl_csr_hw_reset 0.750s 122.254us 5 5 100.00
V1 csr_rw sram_ctrl_csr_rw 0.710s 22.713us 20 20 100.00
V1 csr_bit_bash sram_ctrl_csr_bit_bash 3.050s 2.815ms 5 5 100.00
V1 csr_aliasing sram_ctrl_csr_aliasing 0.760s 56.185us 5 5 100.00
V1 csr_mem_rw_with_rand_reset sram_ctrl_csr_mem_rw_with_rand_reset 1.840s 126.240us 19 20 95.00
V1 regwen_csr_and_corresponding_lockable_csr sram_ctrl_csr_rw 0.710s 22.713us 20 20 100.00
sram_ctrl_csr_aliasing 0.760s 56.185us 5 5 100.00
V1 mem_walk sram_ctrl_mem_walk 11.930s 865.723us 50 50 100.00
V1 mem_partial_access sram_ctrl_mem_partial_access 6.240s 194.224us 50 50 100.00
V1 TOTAL 204 205 99.51
V2 multiple_keys sram_ctrl_multiple_keys 30.989m 53.939ms 50 50 100.00
V2 stress_pipeline sram_ctrl_stress_pipeline 8.106m 17.058ms 50 50 100.00
V2 bijection sram_ctrl_bijection 1.539m 41.650ms 50 50 100.00
V2 access_during_key_req sram_ctrl_access_during_key_req 25.608m 8.056ms 50 50 100.00
V2 lc_escalation sram_ctrl_lc_escalation 11.770s 4.031ms 50 50 100.00
V2 executable sram_ctrl_executable 37.440m 18.046ms 50 50 100.00
V2 partial_access sram_ctrl_partial_access 2.407m 214.521us 50 50 100.00
sram_ctrl_partial_access_b2b 11.460m 57.577ms 50 50 100.00
V2 max_throughput sram_ctrl_max_throughput 2.508m 518.944us 50 50 100.00
sram_ctrl_throughput_w_partial_write 2.745m 509.454us 50 50 100.00
V2 regwen sram_ctrl_regwen 28.221m 68.319ms 50 50 100.00
V2 ram_cfg sram_ctrl_ram_cfg 0.890s 86.215us 50 50 100.00
V2 stress_all sram_ctrl_stress_all 1.506h 215.415ms 42 50 84.00
V2 alert_test sram_ctrl_alert_test 0.750s 22.586us 50 50 100.00
V2 tl_d_oob_addr_access sram_ctrl_tl_errors 5.030s 628.959us 20 20 100.00
V2 tl_d_illegal_access sram_ctrl_tl_errors 5.030s 628.959us 20 20 100.00
V2 tl_d_outstanding_access sram_ctrl_csr_hw_reset 0.750s 122.254us 5 5 100.00
sram_ctrl_csr_rw 0.710s 22.713us 20 20 100.00
sram_ctrl_csr_aliasing 0.760s 56.185us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.850s 29.499us 20 20 100.00
V2 tl_d_partial_access sram_ctrl_csr_hw_reset 0.750s 122.254us 5 5 100.00
sram_ctrl_csr_rw 0.710s 22.713us 20 20 100.00
sram_ctrl_csr_aliasing 0.760s 56.185us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.850s 29.499us 20 20 100.00
V2 TOTAL 732 740 98.92
V2S passthru_mem_tl_intg_err sram_ctrl_passthru_mem_tl_intg_err 3.770s 685.501us 20 20 100.00
V2S tl_intg_err sram_ctrl_sec_cm 5.760s 1.304ms 5 5 100.00
sram_ctrl_tl_intg_err 2.820s 1.156ms 20 20 100.00
V2S prim_count_check sram_ctrl_sec_cm 5.760s 1.304ms 5 5 100.00
V2S sec_cm_bus_integrity sram_ctrl_tl_intg_err 2.820s 1.156ms 20 20 100.00
V2S sec_cm_ctrl_config_regwen sram_ctrl_regwen 28.221m 68.319ms 50 50 100.00
V2S sec_cm_exec_config_regwen sram_ctrl_csr_rw 0.710s 22.713us 20 20 100.00
V2S sec_cm_exec_config_mubi sram_ctrl_executable 37.440m 18.046ms 50 50 100.00
V2S sec_cm_exec_intersig_mubi sram_ctrl_executable 37.440m 18.046ms 50 50 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi sram_ctrl_executable 37.440m 18.046ms 50 50 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi sram_ctrl_lc_escalation 11.770s 4.031ms 50 50 100.00
V2S sec_cm_mem_integrity sram_ctrl_passthru_mem_tl_intg_err 3.770s 685.501us 20 20 100.00
V2S sec_cm_mem_readback sram_ctrl_smoke 2.030m 3.911ms 50 50 100.00
V2S sec_cm_mem_scramble sram_ctrl_smoke 2.030m 3.911ms 50 50 100.00
V2S sec_cm_addr_scramble sram_ctrl_smoke 2.030m 3.911ms 50 50 100.00
V2S sec_cm_instr_bus_lc_gated sram_ctrl_executable 37.440m 18.046ms 50 50 100.00
V2S sec_cm_ram_tl_lc_gate_fsm_sparse sram_ctrl_sec_cm 5.760s 1.304ms 5 5 100.00
V2S sec_cm_key_global_esc sram_ctrl_lc_escalation 11.770s 4.031ms 50 50 100.00
V2S sec_cm_key_local_esc sram_ctrl_sec_cm 5.760s 1.304ms 5 5 100.00
V2S sec_cm_init_ctr_redun sram_ctrl_sec_cm 5.760s 1.304ms 5 5 100.00
V2S sec_cm_scramble_key_sideload sram_ctrl_smoke 2.030m 3.911ms 50 50 100.00
V2S sec_cm_tlul_fifo_ctr_redun sram_ctrl_sec_cm 5.760s 1.304ms 5 5 100.00
V2S TOTAL 45 45 100.00
V3 stress_all_with_rand_reset sram_ctrl_stress_all_with_rand_reset 12.494m 9.022ms 45 50 90.00
V3 TOTAL 45 50 90.00
TOTAL 1026 1040 98.65

Testplan Progress

Items Total Written Passing Progress
V1 8 8 7 87.50
V2 16 16 15 93.75
V2S 3 3 3 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.93 99.16 94.27 99.72 100.00 95.95 99.12 97.26

Failure Buckets

Past Results