SRAM_CTRL/RET Simulation Results

Tuesday July 02 2024 14:17:13 UTC

GitHub Revision: `abd7ce57f2`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 7120396591488306882161367642496372905152431708445539866860566607772054886363

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.082m	3.487ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.660s	49.710us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.740s	14.487us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.290s	723.034us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.710s	64.137us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.390s	90.240us	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.740s	14.487us	20	20	100.00
		sram_ctrl_csr_aliasing	0.710s	64.137us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	12.140s	2.631ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	6.140s	171.452us	50	50	100.00
V1		TOTAL			204	205	99.51
V2	multiple_keys	sram_ctrl_multiple_keys	35.293m	65.035ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	7.165m	8.278ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.321m	13.879ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	28.636m	3.911ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	11.530s	3.622ms	50	50	100.00
V2	executable	sram_ctrl_executable	33.431m	22.835ms	49	50	98.00
V2	partial_access	sram_ctrl_partial_access	1.967m	187.553us	50	50	100.00
		sram_ctrl_partial_access_b2b	11.755m	329.228ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.697m	139.818us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.519m	155.235us	50	50	100.00
V2	regwen	sram_ctrl_regwen	42.907m	4.538ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	0.890s	32.563us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.520h	473.359ms	46	50	92.00
V2	alert_test	sram_ctrl_alert_test	0.720s	14.842us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.690s	293.456us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.690s	293.456us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.660s	49.710us	5	5	100.00
		sram_ctrl_csr_rw	0.740s	14.487us	20	20	100.00
		sram_ctrl_csr_aliasing	0.710s	64.137us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.820s	77.369us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.660s	49.710us	5	5	100.00
		sram_ctrl_csr_rw	0.740s	14.487us	20	20	100.00
		sram_ctrl_csr_aliasing	0.710s	64.137us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.820s	77.369us	20	20	100.00
V2		TOTAL			735	740	99.32
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	4.830s	5.540ms	19	20	95.00
V2S	tl_intg_err	sram_ctrl_sec_cm	3.450s	963.101us	5	5	100.00
		sram_ctrl_tl_intg_err	2.660s	1.412ms	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	3.450s	963.101us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.660s	1.412ms	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	42.907m	4.538ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.740s	14.487us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	33.431m	22.835ms	49	50	98.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	33.431m	22.835ms	49	50	98.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	33.431m	22.835ms	49	50	98.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	11.530s	3.622ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	4.830s	5.540ms	19	20	95.00
V2S	sec_cm_mem_readback	sram_ctrl_smoke	2.082m	3.487ms	50	50	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.082m	3.487ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.082m	3.487ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	33.431m	22.835ms	49	50	98.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	3.450s	963.101us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	11.530s	3.622ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	3.450s	963.101us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	3.450s	963.101us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.082m	3.487ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	3.450s	963.101us	5	5	100.00
V2S		TOTAL			44	45	97.78
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	12.957m	2.661ms	48	50	96.00
V3		TOTAL			48	50	96.00
		TOTAL			1031	1040	99.13

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	16	16	14	87.50
V2S	3	3	2	66.67
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.95	99.16	94.27	99.72	100.00	95.95	99.12	97.44

Failure Buckets

Offending '(((((((((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))))' has 3 failures:

Test sram_ctrl_stress_all has 3 failures.

31.sram_ctrl_stress_all.31820543776387977016846798800516543688054618649355699917800670912743526028509
Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/31.sram_ctrl_stress_all/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @ 392938871 ps: (tlul_assert.sv:277) [ASSERT FAILED] dDataKnown_A
  UVM_INFO @ 392938871 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

40.sram_ctrl_stress_all.61526427124235414192459384748608598064342002425673436162134927990865038818251
Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/40.sram_ctrl_stress_all/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @  79894778 ps: (tlul_assert.sv:277) [ASSERT FAILED] dDataKnown_A
  UVM_INFO @  79894778 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (cip_base_vseq.sv:825) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 2 failures.
  - 10.sram_ctrl_stress_all_with_rand_reset.114165955654666602666235468480106027415173862923482282570739844616629577501434
    Line 312, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/10.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2518834878 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2518834878 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 41.sram_ctrl_stress_all_with_rand_reset.106686756507701154970847215357348365049895932773197242219239990315837853446856
    Line 305, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/41.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 618408728 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 618408728 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(!$isunknown(rdata_o))' has 1 failures:
- Test sram_ctrl_stress_all has 1 failures.
  - 6.sram_ctrl_stress_all.35529574988445121375563501063635567951514355394065969501856378753008820898484
    Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/6.sram_ctrl_stress_all/latest/run.log
```
      Offending '(!$isunknown(rdata_o))'
  UVM_ERROR @ 123656434 ps: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
  UVM_INFO @ 123656434 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status reset value: * has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 14.sram_ctrl_csr_mem_rw_with_rand_reset.69232359140230180849656127829733528274850167684100165296718767505368984355718
    Line 280, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/14.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  69870967 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (56 [0x38] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status reset value: 0x0
  UVM_INFO @  69870967 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 1 failures:
- Test sram_ctrl_passthru_mem_tl_intg_err has 1 failures.
  - 19.sram_ctrl_passthru_mem_tl_intg_err.43470447912317720658585506138567565873513094977427323867421192611736189121199
    Line 319, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/19.sram_ctrl_passthru_mem_tl_intg_err/latest/run.log
```
  UVM_ERROR @ 505584015 ps: uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.sequencer [uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.sequencer] get_next_item/try_next_item called twice without item_done or get in between
  UVM_INFO @ 505584015 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:267) [sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_executable has 1 failures.
  - 36.sram_ctrl_executable.78550687943545001560024727030188920965956035487613272789762856573789336093811
    Line 278, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/36.sram_ctrl_executable/latest/run.log
```
  UVM_FATAL @ 27071485443 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0xa8f558a
  UVM_INFO @ 27071485443 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```