SRAM_CTRL/RET Simulation Results

Thursday June 27 2024 23:02:31 UTC

GitHub Revision: 8db2a18db1

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 100513533386727882033709335126269317053614297947080434367729937568368619502352

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sram_ctrl_smoke 2.489m 4.327ms 50 50 100.00
V1 csr_hw_reset sram_ctrl_csr_hw_reset 0.730s 31.695us 5 5 100.00
V1 csr_rw sram_ctrl_csr_rw 0.730s 199.037us 20 20 100.00
V1 csr_bit_bash sram_ctrl_csr_bit_bash 2.220s 163.724us 5 5 100.00
V1 csr_aliasing sram_ctrl_csr_aliasing 0.740s 73.087us 5 5 100.00
V1 csr_mem_rw_with_rand_reset sram_ctrl_csr_mem_rw_with_rand_reset 2.770s 148.487us 18 20 90.00
V1 regwen_csr_and_corresponding_lockable_csr sram_ctrl_csr_rw 0.730s 199.037us 20 20 100.00
sram_ctrl_csr_aliasing 0.740s 73.087us 5 5 100.00
V1 mem_walk sram_ctrl_mem_walk 12.180s 1.844ms 50 50 100.00
V1 mem_partial_access sram_ctrl_mem_partial_access 6.780s 2.703ms 50 50 100.00
V1 TOTAL 203 205 99.02
V2 multiple_keys sram_ctrl_multiple_keys 26.087m 50.374ms 50 50 100.00
V2 stress_pipeline sram_ctrl_stress_pipeline 7.017m 17.749ms 50 50 100.00
V2 bijection sram_ctrl_bijection 1.484m 90.099ms 50 50 100.00
V2 access_during_key_req sram_ctrl_access_during_key_req 32.120m 17.911ms 50 50 100.00
V2 lc_escalation sram_ctrl_lc_escalation 10.240s 10.773ms 50 50 100.00
V2 executable sram_ctrl_executable 35.307m 21.188ms 50 50 100.00
V2 partial_access sram_ctrl_partial_access 2.439m 1.061ms 50 50 100.00
sram_ctrl_partial_access_b2b 9.811m 122.673ms 50 50 100.00
V2 max_throughput sram_ctrl_max_throughput 2.660m 139.970us 50 50 100.00
sram_ctrl_throughput_w_partial_write 2.477m 610.707us 50 50 100.00
V2 regwen sram_ctrl_regwen 26.453m 146.516ms 50 50 100.00
V2 ram_cfg sram_ctrl_ram_cfg 0.850s 34.758us 50 50 100.00
V2 stress_all sram_ctrl_stress_all 2.111h 64.468ms 41 50 82.00
V2 alert_test sram_ctrl_alert_test 0.730s 26.188us 50 50 100.00
V2 tl_d_oob_addr_access sram_ctrl_tl_errors 5.120s 673.931us 20 20 100.00
V2 tl_d_illegal_access sram_ctrl_tl_errors 5.120s 673.931us 20 20 100.00
V2 tl_d_outstanding_access sram_ctrl_csr_hw_reset 0.730s 31.695us 5 5 100.00
sram_ctrl_csr_rw 0.730s 199.037us 20 20 100.00
sram_ctrl_csr_aliasing 0.740s 73.087us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.830s 324.202us 20 20 100.00
V2 tl_d_partial_access sram_ctrl_csr_hw_reset 0.730s 31.695us 5 5 100.00
sram_ctrl_csr_rw 0.730s 199.037us 20 20 100.00
sram_ctrl_csr_aliasing 0.740s 73.087us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.830s 324.202us 20 20 100.00
V2 TOTAL 731 740 98.78
V2S passthru_mem_tl_intg_err sram_ctrl_passthru_mem_tl_intg_err 3.640s 591.753us 20 20 100.00
V2S tl_intg_err sram_ctrl_sec_cm 3.250s 248.503us 5 5 100.00
sram_ctrl_tl_intg_err 2.580s 436.271us 20 20 100.00
V2S prim_count_check sram_ctrl_sec_cm 3.250s 248.503us 5 5 100.00
V2S sec_cm_bus_integrity sram_ctrl_tl_intg_err 2.580s 436.271us 20 20 100.00
V2S sec_cm_ctrl_config_regwen sram_ctrl_regwen 26.453m 146.516ms 50 50 100.00
V2S sec_cm_exec_config_regwen sram_ctrl_csr_rw 0.730s 199.037us 20 20 100.00
V2S sec_cm_exec_config_mubi sram_ctrl_executable 35.307m 21.188ms 50 50 100.00
V2S sec_cm_exec_intersig_mubi sram_ctrl_executable 35.307m 21.188ms 50 50 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi sram_ctrl_executable 35.307m 21.188ms 50 50 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi sram_ctrl_lc_escalation 10.240s 10.773ms 50 50 100.00
V2S sec_cm_mem_integrity sram_ctrl_passthru_mem_tl_intg_err 3.640s 591.753us 20 20 100.00
V2S sec_cm_mem_readback sram_ctrl_smoke 2.489m 4.327ms 50 50 100.00
V2S sec_cm_mem_scramble sram_ctrl_smoke 2.489m 4.327ms 50 50 100.00
V2S sec_cm_addr_scramble sram_ctrl_smoke 2.489m 4.327ms 50 50 100.00
V2S sec_cm_instr_bus_lc_gated sram_ctrl_executable 35.307m 21.188ms 50 50 100.00
V2S sec_cm_ram_tl_lc_gate_fsm_sparse sram_ctrl_sec_cm 3.250s 248.503us 5 5 100.00
V2S sec_cm_key_global_esc sram_ctrl_lc_escalation 10.240s 10.773ms 50 50 100.00
V2S sec_cm_key_local_esc sram_ctrl_sec_cm 3.250s 248.503us 5 5 100.00
V2S sec_cm_init_ctr_redun sram_ctrl_sec_cm 3.250s 248.503us 5 5 100.00
V2S sec_cm_scramble_key_sideload sram_ctrl_smoke 2.489m 4.327ms 50 50 100.00
V2S sec_cm_tlul_fifo_ctr_redun sram_ctrl_sec_cm 3.250s 248.503us 5 5 100.00
V2S TOTAL 45 45 100.00
V3 stress_all_with_rand_reset sram_ctrl_stress_all_with_rand_reset 17.613m 2.475ms 45 50 90.00
V3 TOTAL 45 50 90.00
TOTAL 1024 1040 98.46

Testplan Progress

Items Total Written Passing Progress
V1 8 8 7 87.50
V2 16 16 15 93.75
V2S 3 3 3 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.95 99.16 94.27 99.72 100.00 95.95 99.12 97.44

Failure Buckets

Past Results