SRAM_CTRL/RET Simulation Results

Thursday June 27 2024 23:02:31 UTC

GitHub Revision: `8db2a18db1`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 100513533386727882033709335126269317053614297947080434367729937568368619502352

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.489m	4.327ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.730s	31.695us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.730s	199.037us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.220s	163.724us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.740s	73.087us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.770s	148.487us	18	20	90.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.730s	199.037us	20	20	100.00
		sram_ctrl_csr_aliasing	0.740s	73.087us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	12.180s	1.844ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	6.780s	2.703ms	50	50	100.00
V1		TOTAL			203	205	99.02
V2	multiple_keys	sram_ctrl_multiple_keys	26.087m	50.374ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	7.017m	17.749ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.484m	90.099ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	32.120m	17.911ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	10.240s	10.773ms	50	50	100.00
V2	executable	sram_ctrl_executable	35.307m	21.188ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	2.439m	1.061ms	50	50	100.00
		sram_ctrl_partial_access_b2b	9.811m	122.673ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.660m	139.970us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.477m	610.707us	50	50	100.00
V2	regwen	sram_ctrl_regwen	26.453m	146.516ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	0.850s	34.758us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.111h	64.468ms	41	50	82.00
V2	alert_test	sram_ctrl_alert_test	0.730s	26.188us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	5.120s	673.931us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	5.120s	673.931us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.730s	31.695us	5	5	100.00
		sram_ctrl_csr_rw	0.730s	199.037us	20	20	100.00
		sram_ctrl_csr_aliasing	0.740s	73.087us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.830s	324.202us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.730s	31.695us	5	5	100.00
		sram_ctrl_csr_rw	0.730s	199.037us	20	20	100.00
		sram_ctrl_csr_aliasing	0.740s	73.087us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.830s	324.202us	20	20	100.00
V2		TOTAL			731	740	98.78
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	3.640s	591.753us	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	3.250s	248.503us	5	5	100.00
		sram_ctrl_tl_intg_err	2.580s	436.271us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	3.250s	248.503us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.580s	436.271us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	26.453m	146.516ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.730s	199.037us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	35.307m	21.188ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	35.307m	21.188ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	35.307m	21.188ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	10.240s	10.773ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	3.640s	591.753us	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_smoke	2.489m	4.327ms	50	50	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.489m	4.327ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.489m	4.327ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	35.307m	21.188ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	3.250s	248.503us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	10.240s	10.773ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	3.250s	248.503us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	3.250s	248.503us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.489m	4.327ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	3.250s	248.503us	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	17.613m	2.475ms	45	50	90.00
V3		TOTAL			45	50	90.00
		TOTAL			1024	1040	98.46

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	16	16	15	93.75
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.95	99.16	94.27	99.72	100.00	95.95	99.12	97.44

Failure Buckets

Offending '(((((((((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))))' has 7 failures:

Test sram_ctrl_stress_all has 7 failures.

3.sram_ctrl_stress_all.4886532329018697739350204133479799814800956181688750160942712238092763031269
Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/3.sram_ctrl_stress_all/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @  69235134 ps: (tlul_assert.sv:277) [ASSERT FAILED] dDataKnown_A
  UVM_INFO @  69235134 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.sram_ctrl_stress_all.79212374978557551428230503516973054765695388771182926040479449472933589933586
Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/5.sram_ctrl_stress_all/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @ 606977356 ps: (tlul_assert.sv:277) [ASSERT FAILED] dDataKnown_A
  UVM_INFO @ 606977356 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_ERROR (cip_base_vseq.sv:828) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 5 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 5 failures.
  - 5.sram_ctrl_stress_all_with_rand_reset.29802568468908331743416538566600175951493341004155816398080444543504380536564
    Line 324, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/5.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1453243130 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1453243130 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 6.sram_ctrl_stress_all_with_rand_reset.93297693977235395039457204975015487236676958127847988794439667831496977082528
    Line 341, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/6.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3377700874 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3377700874 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status reset value: * has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 3.sram_ctrl_csr_mem_rw_with_rand_reset.95550768846675977755221233161603797633247298424141576395535542423933049992398
    Line 280, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/3.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 130421059 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (56 [0x38] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status reset value: 0x0
  UVM_INFO @ 130421059 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: * has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 6.sram_ctrl_csr_mem_rw_with_rand_reset.114167231337746949681874068776915623502471948014491863537004250484390659483969
    Line 280, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/6.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  56999518 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (13 [0xd] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: 0x9
  UVM_INFO @  56999518 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_stress_all has 1 failures.
  - 27.sram_ctrl_stress_all.90656977172150147432823490873524836679101451413397483054535560702473560976751
    Line 332, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/27.sram_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 182912033342 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0x4fbb0e23
  UVM_INFO @ 182912033342 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(!$isunknown(rdata_o))' has 1 failures:
- Test sram_ctrl_stress_all has 1 failures.
  - 42.sram_ctrl_stress_all.77199317048462905085323238735187225036686604720159706622927431808215180736901
    Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/42.sram_ctrl_stress_all/latest/run.log
```
      Offending '(!$isunknown(rdata_o))'
  UVM_ERROR @ 114847122 ps: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
  UVM_INFO @ 114847122 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```