SRAM_CTRL/RET Simulation Results

Sunday June 30 2024 23:02:20 UTC

GitHub Revision: `b33f0bcb4a`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 105302396297609026156504164956156290718642058150905320202190590799028860124396

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.475m	2.836ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.740s	96.291us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.750s	16.538us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.330s	1.903ms	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.770s	263.571us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.960s	480.865us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.750s	16.538us	20	20	100.00
		sram_ctrl_csr_aliasing	0.770s	263.571us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	11.920s	602.436us	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	6.390s	191.415us	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	26.906m	19.976ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.908m	26.159ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.438m	26.527ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	33.266m	28.174ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	11.540s	5.780ms	50	50	100.00
V2	executable	sram_ctrl_executable	36.819m	20.868ms	49	50	98.00
V2	partial_access	sram_ctrl_partial_access	2.371m	1.201ms	49	50	98.00
		sram_ctrl_partial_access_b2b	10.248m	144.831ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.534m	183.507us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.432m	598.758us	50	50	100.00
V2	regwen	sram_ctrl_regwen	33.650m	3.186ms	48	50	96.00
V2	ram_cfg	sram_ctrl_ram_cfg	0.890s	58.787us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.414h	73.885ms	46	50	92.00
V2	alert_test	sram_ctrl_alert_test	0.720s	18.058us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	5.190s	260.357us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	5.190s	260.357us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.740s	96.291us	5	5	100.00
		sram_ctrl_csr_rw	0.750s	16.538us	20	20	100.00
		sram_ctrl_csr_aliasing	0.770s	263.571us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.800s	41.153us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.740s	96.291us	5	5	100.00
		sram_ctrl_csr_rw	0.750s	16.538us	20	20	100.00
		sram_ctrl_csr_aliasing	0.770s	263.571us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.800s	41.153us	20	20	100.00
V2		TOTAL			732	740	98.92
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	3.670s	1.973ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	3.610s	982.594us	5	5	100.00
		sram_ctrl_tl_intg_err	2.710s	2.388ms	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	3.610s	982.594us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.710s	2.388ms	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	33.650m	3.186ms	48	50	96.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.750s	16.538us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	36.819m	20.868ms	49	50	98.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	36.819m	20.868ms	49	50	98.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	36.819m	20.868ms	49	50	98.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	11.540s	5.780ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	3.670s	1.973ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_smoke	2.475m	2.836ms	50	50	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.475m	2.836ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.475m	2.836ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	36.819m	20.868ms	49	50	98.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	3.610s	982.594us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	11.540s	5.780ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	3.610s	982.594us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	3.610s	982.594us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.475m	2.836ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	3.610s	982.594us	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	15.270m	13.056ms	46	50	92.00
V3		TOTAL			46	50	92.00
		TOTAL			1028	1040	98.85

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	16	16	12	75.00
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.95	99.16	94.27	99.72	100.00	95.95	99.12	97.44

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:828) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 4 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 4 failures.
  - 27.sram_ctrl_stress_all_with_rand_reset.110682375516743516360117172190791830134127426703067350856998232870951857043007
    Line 278, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/27.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 7098049250 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 7098049250 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 32.sram_ctrl_stress_all_with_rand_reset.66122878930153019218446216313358039409745274504283781198717572974931857655423
    Line 373, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/32.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1001841541 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1001841541 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.

Offending '(((((((((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))))' has 3 failures:

Test sram_ctrl_stress_all has 3 failures.

26.sram_ctrl_stress_all.97985825071174296416450576506103950670517744136233596268326342360739357364953
Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/26.sram_ctrl_stress_all/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @ 167654239 ps: (tlul_assert.sv:277) [ASSERT FAILED] dDataKnown_A
  UVM_INFO @ 167654239 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

34.sram_ctrl_stress_all.9912396365294870815600143204695912867134732217841174952472030985273911412053
Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/34.sram_ctrl_stress_all/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @  82204835 ps: (tlul_assert.sv:277) [ASSERT FAILED] dDataKnown_A
  UVM_INFO @  82204835 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=* has 2 failures:
- Test sram_ctrl_regwen has 2 failures.
  - 28.sram_ctrl_regwen.105012259903076922950029861364302662612650323455784963166005441279519704585482
    Line 291, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/28.sram_ctrl_regwen/latest/run.log
```
  UVM_FATAL @ 45024324680 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0x46f4729
  UVM_INFO @ 45024324680 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 29.sram_ctrl_regwen.115737577575954770032509039641666188471228321601427827137962030761171369677885
    Line 284, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/29.sram_ctrl_regwen/latest/run.log
```
  UVM_FATAL @ 36699337669 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0x1a5023af
  UVM_INFO @ 36699337669 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(!$isunknown(rdata_o))' has 1 failures:
- Test sram_ctrl_stress_all has 1 failures.
  - 4.sram_ctrl_stress_all.86323607185573441118056420814705527107571357112261897258514028165065712429195
    Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/4.sram_ctrl_stress_all/latest/run.log
```
      Offending '(!$isunknown(rdata_o))'
  UVM_ERROR @ 449635491 ps: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
  UVM_INFO @ 449635491 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_smoke_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_partial_access has 1 failures.
  - 16.sram_ctrl_partial_access.16889074703027232695151533077102507078502789670926068167021282882036620509275
    Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/16.sram_ctrl_partial_access/latest/run.log
```
  UVM_FATAL @ 10463178779 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0xa566616f
  UVM_INFO @ 10463178779 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_executable has 1 failures.
  - 32.sram_ctrl_executable.23603569132518772800007376635760262477555101877700577989255983189422138292776
    Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/32.sram_ctrl_executable/latest/run.log
```
  UVM_FATAL @ 10486733268 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0x737c112f
  UVM_INFO @ 10486733268 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```