SRAM_CTRL/RET Simulation Results

Friday June 28 2024 23:02:02 UTC

GitHub Revision: 3d5220a43f

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 73442097946972310753089853920865571566707682704390544987111276126114608747389

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sram_ctrl_smoke 2.456m 660.856us 50 50 100.00
V1 csr_hw_reset sram_ctrl_csr_hw_reset 0.720s 186.950us 5 5 100.00
V1 csr_rw sram_ctrl_csr_rw 0.750s 14.651us 20 20 100.00
V1 csr_bit_bash sram_ctrl_csr_bit_bash 2.180s 171.060us 5 5 100.00
V1 csr_aliasing sram_ctrl_csr_aliasing 0.770s 32.467us 5 5 100.00
V1 csr_mem_rw_with_rand_reset sram_ctrl_csr_mem_rw_with_rand_reset 2.560s 43.677us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr sram_ctrl_csr_rw 0.750s 14.651us 20 20 100.00
sram_ctrl_csr_aliasing 0.770s 32.467us 5 5 100.00
V1 mem_walk sram_ctrl_mem_walk 14.610s 8.099ms 50 50 100.00
V1 mem_partial_access sram_ctrl_mem_partial_access 6.010s 170.769us 50 50 100.00
V1 TOTAL 205 205 100.00
V2 multiple_keys sram_ctrl_multiple_keys 32.167m 40.047ms 50 50 100.00
V2 stress_pipeline sram_ctrl_stress_pipeline 6.785m 7.739ms 50 50 100.00
V2 bijection sram_ctrl_bijection 1.677m 58.201ms 50 50 100.00
V2 access_during_key_req sram_ctrl_access_during_key_req 25.808m 3.384ms 50 50 100.00
V2 lc_escalation sram_ctrl_lc_escalation 10.900s 1.825ms 50 50 100.00
V2 executable sram_ctrl_executable 30.686m 56.786ms 50 50 100.00
V2 partial_access sram_ctrl_partial_access 2.450m 893.894us 50 50 100.00
sram_ctrl_partial_access_b2b 9.012m 111.575ms 50 50 100.00
V2 max_throughput sram_ctrl_max_throughput 2.500m 2.534ms 50 50 100.00
sram_ctrl_throughput_w_partial_write 2.574m 607.572us 50 50 100.00
V2 regwen sram_ctrl_regwen 30.361m 12.484ms 50 50 100.00
V2 ram_cfg sram_ctrl_ram_cfg 0.840s 46.046us 50 50 100.00
V2 stress_all sram_ctrl_stress_all 1.579h 62.527ms 46 50 92.00
V2 alert_test sram_ctrl_alert_test 0.710s 42.273us 50 50 100.00
V2 tl_d_oob_addr_access sram_ctrl_tl_errors 5.350s 312.014us 20 20 100.00
V2 tl_d_illegal_access sram_ctrl_tl_errors 5.350s 312.014us 20 20 100.00
V2 tl_d_outstanding_access sram_ctrl_csr_hw_reset 0.720s 186.950us 5 5 100.00
sram_ctrl_csr_rw 0.750s 14.651us 20 20 100.00
sram_ctrl_csr_aliasing 0.770s 32.467us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.830s 235.591us 20 20 100.00
V2 tl_d_partial_access sram_ctrl_csr_hw_reset 0.720s 186.950us 5 5 100.00
sram_ctrl_csr_rw 0.750s 14.651us 20 20 100.00
sram_ctrl_csr_aliasing 0.770s 32.467us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.830s 235.591us 20 20 100.00
V2 TOTAL 736 740 99.46
V2S passthru_mem_tl_intg_err sram_ctrl_passthru_mem_tl_intg_err 3.640s 549.738us 20 20 100.00
V2S tl_intg_err sram_ctrl_sec_cm 2.900s 218.562us 5 5 100.00
sram_ctrl_tl_intg_err 2.440s 1.193ms 20 20 100.00
V2S prim_count_check sram_ctrl_sec_cm 2.900s 218.562us 5 5 100.00
V2S sec_cm_bus_integrity sram_ctrl_tl_intg_err 2.440s 1.193ms 20 20 100.00
V2S sec_cm_ctrl_config_regwen sram_ctrl_regwen 30.361m 12.484ms 50 50 100.00
V2S sec_cm_exec_config_regwen sram_ctrl_csr_rw 0.750s 14.651us 20 20 100.00
V2S sec_cm_exec_config_mubi sram_ctrl_executable 30.686m 56.786ms 50 50 100.00
V2S sec_cm_exec_intersig_mubi sram_ctrl_executable 30.686m 56.786ms 50 50 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi sram_ctrl_executable 30.686m 56.786ms 50 50 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi sram_ctrl_lc_escalation 10.900s 1.825ms 50 50 100.00
V2S sec_cm_mem_integrity sram_ctrl_passthru_mem_tl_intg_err 3.640s 549.738us 20 20 100.00
V2S sec_cm_mem_readback sram_ctrl_smoke 2.456m 660.856us 50 50 100.00
V2S sec_cm_mem_scramble sram_ctrl_smoke 2.456m 660.856us 50 50 100.00
V2S sec_cm_addr_scramble sram_ctrl_smoke 2.456m 660.856us 50 50 100.00
V2S sec_cm_instr_bus_lc_gated sram_ctrl_executable 30.686m 56.786ms 50 50 100.00
V2S sec_cm_ram_tl_lc_gate_fsm_sparse sram_ctrl_sec_cm 2.900s 218.562us 5 5 100.00
V2S sec_cm_key_global_esc sram_ctrl_lc_escalation 10.900s 1.825ms 50 50 100.00
V2S sec_cm_key_local_esc sram_ctrl_sec_cm 2.900s 218.562us 5 5 100.00
V2S sec_cm_init_ctr_redun sram_ctrl_sec_cm 2.900s 218.562us 5 5 100.00
V2S sec_cm_scramble_key_sideload sram_ctrl_smoke 2.456m 660.856us 50 50 100.00
V2S sec_cm_tlul_fifo_ctr_redun sram_ctrl_sec_cm 2.900s 218.562us 5 5 100.00
V2S TOTAL 45 45 100.00
V3 stress_all_with_rand_reset sram_ctrl_stress_all_with_rand_reset 13.286m 3.070ms 47 50 94.00
V3 TOTAL 47 50 94.00
TOTAL 1033 1040 99.33

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 16 16 15 93.75
V2S 3 3 3 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.95 99.16 94.27 99.72 100.00 95.95 99.12 97.44

Failure Buckets

Past Results