SRAM_CTRL/RET Simulation Results

Wednesday June 26 2024 23:02:36 UTC

GitHub Revision: `be1c4a4f52`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 44766564427213563291105655232733134394512207819884794315335669279596867428010

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.432m	3.287ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.690s	28.727us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.720s	49.950us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.220s	127.403us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.790s	207.040us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.290s	73.551us	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.720s	49.950us	20	20	100.00
		sram_ctrl_csr_aliasing	0.790s	207.040us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	12.120s	2.583ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	6.650s	1.103ms	50	50	100.00
V1		TOTAL			204	205	99.51
V2	multiple_keys	sram_ctrl_multiple_keys	31.381m	190.942ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.557m	13.170ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.525m	35.938ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	30.699m	25.854ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	9.000s	2.134ms	50	50	100.00
V2	executable	sram_ctrl_executable	29.504m	9.878ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	3.015m	1.595ms	50	50	100.00
		sram_ctrl_partial_access_b2b	10.330m	91.278ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.692m	170.011us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.614m	151.913us	50	50	100.00
V2	regwen	sram_ctrl_regwen	34.239m	31.721ms	49	50	98.00
V2	ram_cfg	sram_ctrl_ram_cfg	0.880s	26.727us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.479h	52.561ms	47	50	94.00
V2	alert_test	sram_ctrl_alert_test	0.770s	30.793us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	5.400s	529.182us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	5.400s	529.182us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.690s	28.727us	5	5	100.00
		sram_ctrl_csr_rw	0.720s	49.950us	20	20	100.00
		sram_ctrl_csr_aliasing	0.790s	207.040us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.880s	39.499us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.690s	28.727us	5	5	100.00
		sram_ctrl_csr_rw	0.720s	49.950us	20	20	100.00
		sram_ctrl_csr_aliasing	0.790s	207.040us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.880s	39.499us	20	20	100.00
V2		TOTAL			736	740	99.46
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	3.700s	526.621us	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	3.490s	1.676ms	5	5	100.00
		sram_ctrl_tl_intg_err	2.600s	2.053ms	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	3.490s	1.676ms	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.600s	2.053ms	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	34.239m	31.721ms	49	50	98.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.720s	49.950us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	29.504m	9.878ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	29.504m	9.878ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	29.504m	9.878ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	9.000s	2.134ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	3.700s	526.621us	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_smoke	2.432m	3.287ms	50	50	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.432m	3.287ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.432m	3.287ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	29.504m	9.878ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	3.490s	1.676ms	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	9.000s	2.134ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	3.490s	1.676ms	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	3.490s	1.676ms	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.432m	3.287ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	3.490s	1.676ms	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	14.095m	1.068ms	42	50	84.00
V3		TOTAL			42	50	84.00
		TOTAL			1027	1040	98.75

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	16	16	14	87.50
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.95	99.16	94.27	99.72	100.00	95.95	99.12	97.44

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:828) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 7 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 7 failures.
  - 17.sram_ctrl_stress_all_with_rand_reset.104222110955797135493666874347679185423845804893776383608585388143603471177002
    Line 340, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/17.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4375150278 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 4375150278 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 30.sram_ctrl_stress_all_with_rand_reset.91136929524920647064472387200828323242261186310328610907728325099595957406504
    Line 327, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/30.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2051811963 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2051811963 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.

Offending '(((((((((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))))' has 2 failures:

Test sram_ctrl_stress_all has 2 failures.

0.sram_ctrl_stress_all.24854440714774680001835471553649860204425505846512879747425281455738191115618
Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/0.sram_ctrl_stress_all/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @  37661083 ps: (tlul_assert.sv:277) [ASSERT FAILED] dDataKnown_A
  UVM_INFO @  37661083 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

40.sram_ctrl_stress_all.92358789242128348541608761079253329652748046809324531512179372164895539725065
Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/40.sram_ctrl_stress_all/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @  51721665 ps: (tlul_assert.sv:277) [ASSERT FAILED] dDataKnown_A
  UVM_INFO @  51721665 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_regwen has 1 failures.
  - 13.sram_ctrl_regwen.104611181422401941853964460047925989546199550687870332609808990551800664651534
    Line 303, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/13.sram_ctrl_regwen/latest/run.log
```
  UVM_FATAL @ 76726787149 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0x13cbb7f7
  UVM_INFO @ 76726787149 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status reset value: * has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 13.sram_ctrl_csr_mem_rw_with_rand_reset.88829050976987315370653779559680064245381879671018891893650739335607450395592
    Line 280, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/13.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  69730098 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (56 [0x38] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status reset value: 0x0
  UVM_INFO @  69730098 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 1 failures.
  - 22.sram_ctrl_stress_all_with_rand_reset.29359090116996145094186652690948550961333807997371034113791452486458442610588
    Line 329, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/22.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 32776241099 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0x5f91f6a6
  UVM_INFO @ 32776241099 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (mem_model.sv:48) [exp_mem_sram_ctrl_prim_reg_block] Check failed act_data === system_memory[addr] (* [*] vs * [*]) addr * read out mismatch has 1 failures:
- Test sram_ctrl_stress_all has 1 failures.
  - 38.sram_ctrl_stress_all.49369233639725626914607246285418445586557641412644380077437305216917519281767
    Line 272, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/38.sram_ctrl_stress_all/latest/run.log
```
  UVM_ERROR @ 839604838 ps: (mem_model.sv:48) [exp_mem_sram_ctrl_prim_reg_block] Check failed act_data === system_memory[addr] (0xd3 [11010011] vs 0x38 [111000]) addr 0xffde8930 read out mismatch
  UVM_INFO @ 839604838 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```