SRAM_CTRL/RET Simulation Results

Saturday June 29 2024 23:02:35 UTC

GitHub Revision: `b33f0bcb4a`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 9407974028806500767465982655187958599819354731549473124644158596869486113221

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.667m	1.291ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.720s	36.484us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.740s	12.397us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.350s	718.889us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.780s	35.442us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.380s	114.182us	18	20	90.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.740s	12.397us	20	20	100.00
		sram_ctrl_csr_aliasing	0.780s	35.442us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	11.700s	2.725ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	6.360s	803.403us	50	50	100.00
V1		TOTAL			203	205	99.02
V2	multiple_keys	sram_ctrl_multiple_keys	29.242m	37.203ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.503m	45.186ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.622m	38.608ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	47.253m	8.532ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	10.050s	1.730ms	50	50	100.00
V2	executable	sram_ctrl_executable	32.157m	39.555ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	2.531m	2.477ms	50	50	100.00
		sram_ctrl_partial_access_b2b	8.958m	20.815ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.513m	139.926us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.343m	306.084us	50	50	100.00
V2	regwen	sram_ctrl_regwen	37.757m	71.145ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	0.940s	97.301us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.113h	417.053ms	48	50	96.00
V2	alert_test	sram_ctrl_alert_test	0.750s	25.857us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.560s	293.919us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.560s	293.919us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.720s	36.484us	5	5	100.00
		sram_ctrl_csr_rw	0.740s	12.397us	20	20	100.00
		sram_ctrl_csr_aliasing	0.780s	35.442us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.800s	22.093us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.720s	36.484us	5	5	100.00
		sram_ctrl_csr_rw	0.740s	12.397us	20	20	100.00
		sram_ctrl_csr_aliasing	0.780s	35.442us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.800s	22.093us	20	20	100.00
V2		TOTAL			738	740	99.73
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	3.530s	1.618ms	19	20	95.00
V2S	tl_intg_err	sram_ctrl_sec_cm	3.170s	904.744us	5	5	100.00
		sram_ctrl_tl_intg_err	2.790s	478.233us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	3.170s	904.744us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.790s	478.233us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	37.757m	71.145ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.740s	12.397us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	32.157m	39.555ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	32.157m	39.555ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	32.157m	39.555ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	10.050s	1.730ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	3.530s	1.618ms	19	20	95.00
V2S	sec_cm_mem_readback	sram_ctrl_smoke	2.667m	1.291ms	50	50	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.667m	1.291ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.667m	1.291ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	32.157m	39.555ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	3.170s	904.744us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	10.050s	1.730ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	3.170s	904.744us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	3.170s	904.744us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.667m	1.291ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	3.170s	904.744us	5	5	100.00
V2S		TOTAL			44	45	97.78
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	12.088m	2.284ms	41	50	82.00
V3		TOTAL			41	50	82.00
		TOTAL			1026	1040	98.65

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	16	16	15	93.75
V2S	3	3	2	66.67
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.95	99.16	94.27	99.72	100.00	95.95	99.12	97.44

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:828) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 9 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 9 failures.
  - 4.sram_ctrl_stress_all_with_rand_reset.54088849317286074104872467571178754887556113375462944068225463581940817658715
    Line 393, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/4.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 11603467694 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 11603467694 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 5.sram_ctrl_stress_all_with_rand_reset.89869287691998513157578288025966075224372918265627993262558763421906726400338
    Line 311, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/5.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 702657313 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 702657313 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.

Offending '(((((((((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))))' has 2 failures:

Test sram_ctrl_stress_all has 2 failures.

7.sram_ctrl_stress_all.85020107054506939555195582334034846527685685439316319688952898645738583454450
Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/7.sram_ctrl_stress_all/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @ 199250661 ps: (tlul_assert.sv:277) [ASSERT FAILED] dDataKnown_A
  UVM_INFO @ 199250661 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

40.sram_ctrl_stress_all.41605113802494122665349404908099947044545900478067318881837516451234410053873
Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/40.sram_ctrl_stress_all/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @ 210424994 ps: (tlul_assert.sv:277) [ASSERT FAILED] dDataKnown_A
  UVM_INFO @ 210424994 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status reset value: * has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 3.sram_ctrl_csr_mem_rw_with_rand_reset.11541085081528681383148920771716494895180111843272026336744363539506538990808
    Line 280, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/3.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  79685462 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (56 [0x38] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status reset value: 0x0
  UVM_INFO @  79685462 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_tl_seq_item.sv:223) sequencer [req] d_user.data_intg act (*) != exp (*) has 1 failures:
- Test sram_ctrl_passthru_mem_tl_intg_err has 1 failures.
  - 17.sram_ctrl_passthru_mem_tl_intg_err.8250753221159160998212251524636902903082777581599107127509847347675797991682
    Line 299, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/17.sram_ctrl_passthru_mem_tl_intg_err/latest/run.log
```
  UVM_ERROR @ 216761031 ps: (cip_tl_seq_item.sv:223) uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq.tl_seq.req] d_user.data_intg act (0x45) != exp (0x17)
  UVM_INFO @ 216761031 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.scr_key_valid reset value: * has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 19.sram_ctrl_csr_mem_rw_with_rand_reset.27072730252807919187961842967775156946452621534396457988071854034451397464533
    Line 280, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/19.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 114182186 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status.scr_key_valid reset value: 0x0
  UVM_INFO @ 114182186 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```