SRAM_CTRL/RET Simulation Results

Wednesday July 03 2024 23:02:32 UTC

GitHub Revision: `e6706fcc7b`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 8083624550445280117614176890238357255195852125596561370221115831648066795492

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.679m	661.380us	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.670s	175.071us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.680s	13.850us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.080s	546.027us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.780s	169.728us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.400s	69.150us	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.680s	13.850us	20	20	100.00
		sram_ctrl_csr_aliasing	0.780s	169.728us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	12.180s	2.705ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	6.780s	3.328ms	50	50	100.00
V1		TOTAL			204	205	99.51
V2	multiple_keys	sram_ctrl_multiple_keys	31.312m	28.524ms	49	50	98.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.547m	3.883ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.502m	20.738ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	29.771m	8.344ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	11.020s	16.999ms	50	50	100.00
V2	executable	sram_ctrl_executable	30.503m	104.696ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	2.358m	408.830us	50	50	100.00
		sram_ctrl_partial_access_b2b	10.999m	46.869ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.464m	542.848us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.493m	608.325us	50	50	100.00
V2	regwen	sram_ctrl_regwen	30.074m	36.443ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	0.830s	40.390us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.093h	405.862ms	46	50	92.00
V2	alert_test	sram_ctrl_alert_test	0.720s	49.948us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.600s	64.111us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.600s	64.111us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.670s	175.071us	5	5	100.00
		sram_ctrl_csr_rw	0.680s	13.850us	20	20	100.00
		sram_ctrl_csr_aliasing	0.780s	169.728us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.810s	20.451us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.670s	175.071us	5	5	100.00
		sram_ctrl_csr_rw	0.680s	13.850us	20	20	100.00
		sram_ctrl_csr_aliasing	0.780s	169.728us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.810s	20.451us	20	20	100.00
V2		TOTAL			735	740	99.32
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	3.780s	1.195ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	3.480s	566.334us	5	5	100.00
		sram_ctrl_tl_intg_err	3.280s	645.320us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	3.480s	566.334us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	3.280s	645.320us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	30.074m	36.443ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.680s	13.850us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	30.503m	104.696ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	30.503m	104.696ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	30.503m	104.696ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	11.020s	16.999ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	3.780s	1.195ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_smoke	2.679m	661.380us	50	50	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.679m	661.380us	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.679m	661.380us	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	30.503m	104.696ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	3.480s	566.334us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	11.020s	16.999ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	3.480s	566.334us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	3.480s	566.334us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.679m	661.380us	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	3.480s	566.334us	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	17.374m	9.517ms	43	50	86.00
V3		TOTAL			43	50	86.00
		TOTAL			1027	1040	98.75

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	16	16	14	87.50
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.95	99.16	94.27	99.72	100.00	95.95	99.12	97.44

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:825) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 7 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 7 failures.
  - 2.sram_ctrl_stress_all_with_rand_reset.28082013556996971602611628334641198596725009468981135578563297876294657615929
    Line 278, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/2.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2346544879 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2346544879 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.sram_ctrl_stress_all_with_rand_reset.3800493259949315844110401021615787291251928976992636152421054770823226951808
    Line 292, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/3.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2178851936 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2178851936 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.

Offending '(((((((((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))))' has 3 failures:

Test sram_ctrl_stress_all has 3 failures.

7.sram_ctrl_stress_all.18835935849246852467800335444446365524591845579475985897476190612370774326697
Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/7.sram_ctrl_stress_all/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @  59368720 ps: (tlul_assert.sv:277) [ASSERT FAILED] dDataKnown_A
  UVM_INFO @  59368720 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

8.sram_ctrl_stress_all.12645245452634852768298837100102555220216841983870435266144927015381845001972
Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/8.sram_ctrl_stress_all/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @ 207949300 ps: (tlul_assert.sv:277) [ASSERT FAILED] dDataKnown_A
  UVM_INFO @ 207949300 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status reset value: * has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 2.sram_ctrl_csr_mem_rw_with_rand_reset.105730818784906207774294413940831053872617249420066366462907055582069864094880
    Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/2.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 163923682 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (40 [0x28] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status reset value: 0x0
  UVM_INFO @ 163923682 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (mem_model.sv:48) [exp_mem_sram_ctrl_prim_reg_block] Check failed act_data === system_memory[addr] (* [*] vs * [*]) addr * read out mismatch has 1 failures:
- Test sram_ctrl_stress_all has 1 failures.
  - 13.sram_ctrl_stress_all.51320159596967662074453254995161863082263836782460039284725980545716395777724
    Line 563, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/13.sram_ctrl_stress_all/latest/run.log
```
  UVM_ERROR @ 41030036868 ps: (mem_model.sv:48) [exp_mem_sram_ctrl_prim_reg_block] Check failed act_data === system_memory[addr] (0x2f [101111] vs 0x37 [110111]) addr 0x9f7e6554 read out mismatch
  UVM_INFO @ 41030036868 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:267) [sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_multiple_keys has 1 failures.
  - 31.sram_ctrl_multiple_keys.100697099081037419123046900122202756321747179672201822586309823905037313896925
    Line 278, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/31.sram_ctrl_multiple_keys/latest/run.log
```
  UVM_FATAL @ 19611944547 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0xd65691d4
  UVM_INFO @ 19611944547 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```