SRAM_CTRL/RET Simulation Results

Thursday July 04 2024 23:02:28 UTC

GitHub Revision: 3e678c112b

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 94940390549829454688103081328166376218078465228811124044523808815554354133843

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sram_ctrl_smoke 2.674m 1.379ms 50 50 100.00
V1 csr_hw_reset sram_ctrl_csr_hw_reset 0.740s 29.398us 5 5 100.00
V1 csr_rw sram_ctrl_csr_rw 0.760s 19.845us 20 20 100.00
V1 csr_bit_bash sram_ctrl_csr_bit_bash 2.410s 688.335us 5 5 100.00
V1 csr_aliasing sram_ctrl_csr_aliasing 0.780s 56.542us 5 5 100.00
V1 csr_mem_rw_with_rand_reset sram_ctrl_csr_mem_rw_with_rand_reset 2.520s 38.634us 19 20 95.00
V1 regwen_csr_and_corresponding_lockable_csr sram_ctrl_csr_rw 0.760s 19.845us 20 20 100.00
sram_ctrl_csr_aliasing 0.780s 56.542us 5 5 100.00
V1 mem_walk sram_ctrl_mem_walk 13.020s 1.274ms 50 50 100.00
V1 mem_partial_access sram_ctrl_mem_partial_access 6.220s 2.085ms 50 50 100.00
V1 TOTAL 204 205 99.51
V2 multiple_keys sram_ctrl_multiple_keys 36.392m 4.740ms 50 50 100.00
V2 stress_pipeline sram_ctrl_stress_pipeline 8.321m 5.173ms 50 50 100.00
V2 bijection sram_ctrl_bijection 1.453m 5.419ms 50 50 100.00
V2 access_during_key_req sram_ctrl_access_during_key_req 33.215m 8.671ms 50 50 100.00
V2 lc_escalation sram_ctrl_lc_escalation 9.820s 1.130ms 50 50 100.00
V2 executable sram_ctrl_executable 47.578m 14.744ms 49 50 98.00
V2 partial_access sram_ctrl_partial_access 2.600m 2.289ms 50 50 100.00
sram_ctrl_partial_access_b2b 9.443m 24.363ms 50 50 100.00
V2 max_throughput sram_ctrl_max_throughput 2.366m 136.135us 50 50 100.00
sram_ctrl_throughput_w_partial_write 2.659m 201.313us 50 50 100.00
V2 regwen sram_ctrl_regwen 38.539m 19.013ms 48 50 96.00
V2 ram_cfg sram_ctrl_ram_cfg 0.860s 42.215us 50 50 100.00
V2 stress_all sram_ctrl_stress_all 2.031h 565.545ms 49 50 98.00
V2 alert_test sram_ctrl_alert_test 0.720s 15.140us 50 50 100.00
V2 tl_d_oob_addr_access sram_ctrl_tl_errors 5.410s 373.912us 20 20 100.00
V2 tl_d_illegal_access sram_ctrl_tl_errors 5.410s 373.912us 20 20 100.00
V2 tl_d_outstanding_access sram_ctrl_csr_hw_reset 0.740s 29.398us 5 5 100.00
sram_ctrl_csr_rw 0.760s 19.845us 20 20 100.00
sram_ctrl_csr_aliasing 0.780s 56.542us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.840s 23.964us 20 20 100.00
V2 tl_d_partial_access sram_ctrl_csr_hw_reset 0.740s 29.398us 5 5 100.00
sram_ctrl_csr_rw 0.760s 19.845us 20 20 100.00
sram_ctrl_csr_aliasing 0.780s 56.542us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.840s 23.964us 20 20 100.00
V2 TOTAL 736 740 99.46
V2S passthru_mem_tl_intg_err sram_ctrl_passthru_mem_tl_intg_err 3.760s 1.579ms 20 20 100.00
V2S tl_intg_err sram_ctrl_sec_cm 3.340s 1.009ms 5 5 100.00
sram_ctrl_tl_intg_err 3.570s 2.470ms 20 20 100.00
V2S prim_count_check sram_ctrl_sec_cm 3.340s 1.009ms 5 5 100.00
V2S sec_cm_bus_integrity sram_ctrl_tl_intg_err 3.570s 2.470ms 20 20 100.00
V2S sec_cm_ctrl_config_regwen sram_ctrl_regwen 38.539m 19.013ms 48 50 96.00
V2S sec_cm_exec_config_regwen sram_ctrl_csr_rw 0.760s 19.845us 20 20 100.00
V2S sec_cm_exec_config_mubi sram_ctrl_executable 47.578m 14.744ms 49 50 98.00
V2S sec_cm_exec_intersig_mubi sram_ctrl_executable 47.578m 14.744ms 49 50 98.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi sram_ctrl_executable 47.578m 14.744ms 49 50 98.00
V2S sec_cm_lc_escalate_en_intersig_mubi sram_ctrl_lc_escalation 9.820s 1.130ms 50 50 100.00
V2S sec_cm_mem_integrity sram_ctrl_passthru_mem_tl_intg_err 3.760s 1.579ms 20 20 100.00
V2S sec_cm_mem_readback sram_ctrl_smoke 2.674m 1.379ms 50 50 100.00
V2S sec_cm_mem_scramble sram_ctrl_smoke 2.674m 1.379ms 50 50 100.00
V2S sec_cm_addr_scramble sram_ctrl_smoke 2.674m 1.379ms 50 50 100.00
V2S sec_cm_instr_bus_lc_gated sram_ctrl_executable 47.578m 14.744ms 49 50 98.00
V2S sec_cm_ram_tl_lc_gate_fsm_sparse sram_ctrl_sec_cm 3.340s 1.009ms 5 5 100.00
V2S sec_cm_key_global_esc sram_ctrl_lc_escalation 9.820s 1.130ms 50 50 100.00
V2S sec_cm_key_local_esc sram_ctrl_sec_cm 3.340s 1.009ms 5 5 100.00
V2S sec_cm_init_ctr_redun sram_ctrl_sec_cm 3.340s 1.009ms 5 5 100.00
V2S sec_cm_scramble_key_sideload sram_ctrl_smoke 2.674m 1.379ms 50 50 100.00
V2S sec_cm_tlul_fifo_ctr_redun sram_ctrl_sec_cm 3.340s 1.009ms 5 5 100.00
V2S TOTAL 45 45 100.00
V3 stress_all_with_rand_reset sram_ctrl_stress_all_with_rand_reset 12.326m 3.195ms 44 50 88.00
V3 TOTAL 44 50 88.00
TOTAL 1029 1040 98.94

Testplan Progress

Items Total Written Passing Progress
V1 8 8 7 87.50
V2 16 16 13 81.25
V2S 3 3 3 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.95 99.16 94.27 99.72 100.00 95.95 99.12 97.44

Failure Buckets

Past Results