SRAM_CTRL/RET Simulation Results

Friday July 05 2024 23:02:55 UTC

GitHub Revision: `9edf84e236`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 47623749544922802985321435118963335754001495105472137721881337469861493653463

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.817m	555.591us	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.690s	29.509us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.690s	44.216us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.800s	161.181us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.760s	66.194us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.430s	143.152us	18	20	90.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.690s	44.216us	20	20	100.00
		sram_ctrl_csr_aliasing	0.760s	66.194us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	12.850s	4.025ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	6.340s	2.388ms	50	50	100.00
V1		TOTAL			203	205	99.02
V2	multiple_keys	sram_ctrl_multiple_keys	32.766m	271.149ms	49	50	98.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.497m	28.783ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.357m	7.351ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	33.557m	28.373ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	11.270s	1.261ms	50	50	100.00
V2	executable	sram_ctrl_executable	29.746m	52.524ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	2.712m	1.250ms	50	50	100.00
		sram_ctrl_partial_access_b2b	11.243m	539.596ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.645m	517.427us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.640m	158.111us	50	50	100.00
V2	regwen	sram_ctrl_regwen	27.471m	4.124ms	49	50	98.00
V2	ram_cfg	sram_ctrl_ram_cfg	0.880s	82.901us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.742h	15.136ms	47	50	94.00
V2	alert_test	sram_ctrl_alert_test	0.810s	33.507us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.170s	42.466us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.170s	42.466us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.690s	29.509us	5	5	100.00
		sram_ctrl_csr_rw	0.690s	44.216us	20	20	100.00
		sram_ctrl_csr_aliasing	0.760s	66.194us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.820s	81.572us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.690s	29.509us	5	5	100.00
		sram_ctrl_csr_rw	0.690s	44.216us	20	20	100.00
		sram_ctrl_csr_aliasing	0.760s	66.194us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.820s	81.572us	20	20	100.00
V2		TOTAL			735	740	99.32
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	3.920s	4.955ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	3.690s	426.089us	5	5	100.00
		sram_ctrl_tl_intg_err	2.580s	296.278us	19	20	95.00
V2S	prim_count_check	sram_ctrl_sec_cm	3.690s	426.089us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.580s	296.278us	19	20	95.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	27.471m	4.124ms	49	50	98.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.690s	44.216us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	29.746m	52.524ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	29.746m	52.524ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	29.746m	52.524ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	11.270s	1.261ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	3.920s	4.955ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_smoke	2.817m	555.591us	50	50	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.817m	555.591us	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.817m	555.591us	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	29.746m	52.524ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	3.690s	426.089us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	11.270s	1.261ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	3.690s	426.089us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	3.690s	426.089us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.817m	555.591us	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	3.690s	426.089us	5	5	100.00
V2S		TOTAL			44	45	97.78
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	13.220m	2.000ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			1031	1040	99.13

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	16	16	13	81.25
V2S	3	3	2	66.67
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.95	99.16	94.27	99.72	100.00	95.95	99.12	97.44

Failure Buckets

Offending '(((((((((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))))' has 3 failures:

Test sram_ctrl_stress_all has 3 failures.

15.sram_ctrl_stress_all.24450301219893280279788007551472093912093557766064594004101877826564230108893
Line 279, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/15.sram_ctrl_stress_all/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @  68114277 ps: (tlul_assert.sv:277) [ASSERT FAILED] dDataKnown_A
  UVM_INFO @  68114277 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

38.sram_ctrl_stress_all.57158059527171443873795277413666509949452806097526792879437360241145633176653
Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/38.sram_ctrl_stress_all/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @  14676260 ps: (tlul_assert.sv:277) [ASSERT FAILED] dDataKnown_A
  UVM_INFO @  14676260 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: * has 2 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 2 failures.
  - 10.sram_ctrl_csr_mem_rw_with_rand_reset.46519689790571689048434425925392804954412369698043523935121791991259376017594
    Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/10.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  36106744 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (7 [0x7] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: 0x9
  UVM_INFO @  36106744 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 19.sram_ctrl_csr_mem_rw_with_rand_reset.65483993540399371466841237074399934791290651848412844955704518775055989826135
    Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/19.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  27230644 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: 0x9
  UVM_INFO @  27230644 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 1 failures:
- Test sram_ctrl_tl_intg_err has 1 failures.
  - 2.sram_ctrl_tl_intg_err.57574357121006548395457085286279233393462091749303049605125043420821525292099
    Line 446, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/2.sram_ctrl_tl_intg_err/latest/run.log
```
  UVM_ERROR @ 134150234 ps: uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.sequencer [uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.sequencer] get_next_item/try_next_item called twice without item_done or get in between
  UVM_INFO @ 134150234 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:267) [sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_regwen has 1 failures.
  - 23.sram_ctrl_regwen.44371165535975493402537565523960533905725561383514695777773455511301828173418
    Line 291, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/23.sram_ctrl_regwen/latest/run.log
```
  UVM_FATAL @ 41886331259 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0xbe560c0
  UVM_INFO @ 41886331259 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:267) [sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_multiple_keys has 1 failures.
  - 25.sram_ctrl_multiple_keys.27516076869898254529115497009885794571760290845460590444269397008487286857869
    Line 302, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/25.sram_ctrl_multiple_keys/latest/run.log
```
  UVM_FATAL @ 100204523696 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0xfdbfea4d
  UVM_INFO @ 100204523696 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:267) [sram_ctrl_smoke_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 1 failures.
  - 44.sram_ctrl_stress_all_with_rand_reset.115372252142910858458995816805676528151427136325614311007627631486118524208143
    Line 278, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/44.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 11324976418 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.sram_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x87317295
  UVM_INFO @ 11324976418 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```