SRAM_CTRL/RET Simulation Results

Saturday July 06 2024 23:02:28 UTC

GitHub Revision: c42c47ec2d

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 3200059823452722292543998130245428086525417237473114929151723951411399280153

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sram_ctrl_smoke 2.473m 7.646ms 50 50 100.00
V1 csr_hw_reset sram_ctrl_csr_hw_reset 0.680s 22.608us 5 5 100.00
V1 csr_rw sram_ctrl_csr_rw 0.740s 14.855us 20 20 100.00
V1 csr_bit_bash sram_ctrl_csr_bit_bash 2.880s 1.840ms 5 5 100.00
V1 csr_aliasing sram_ctrl_csr_aliasing 0.750s 60.101us 5 5 100.00
V1 csr_mem_rw_with_rand_reset sram_ctrl_csr_mem_rw_with_rand_reset 2.490s 42.501us 19 20 95.00
V1 regwen_csr_and_corresponding_lockable_csr sram_ctrl_csr_rw 0.740s 14.855us 20 20 100.00
sram_ctrl_csr_aliasing 0.750s 60.101us 5 5 100.00
V1 mem_walk sram_ctrl_mem_walk 13.560s 6.297ms 50 50 100.00
V1 mem_partial_access sram_ctrl_mem_partial_access 6.490s 663.146us 50 50 100.00
V1 TOTAL 204 205 99.51
V2 multiple_keys sram_ctrl_multiple_keys 28.778m 77.667ms 50 50 100.00
V2 stress_pipeline sram_ctrl_stress_pipeline 6.709m 8.142ms 50 50 100.00
V2 bijection sram_ctrl_bijection 1.428m 5.502ms 50 50 100.00
V2 access_during_key_req sram_ctrl_access_during_key_req 36.050m 4.694ms 50 50 100.00
V2 lc_escalation sram_ctrl_lc_escalation 11.510s 3.821ms 50 50 100.00
V2 executable sram_ctrl_executable 31.257m 5.211ms 50 50 100.00
V2 partial_access sram_ctrl_partial_access 2.492m 799.704us 50 50 100.00
sram_ctrl_partial_access_b2b 10.246m 283.632ms 50 50 100.00
V2 max_throughput sram_ctrl_max_throughput 2.413m 135.719us 50 50 100.00
sram_ctrl_throughput_w_partial_write 2.655m 301.303us 50 50 100.00
V2 regwen sram_ctrl_regwen 28.664m 3.353ms 50 50 100.00
V2 ram_cfg sram_ctrl_ram_cfg 0.830s 354.014us 50 50 100.00
V2 stress_all sram_ctrl_stress_all 1.863h 19.123ms 46 50 92.00
V2 alert_test sram_ctrl_alert_test 0.740s 97.093us 50 50 100.00
V2 tl_d_oob_addr_access sram_ctrl_tl_errors 4.110s 131.272us 20 20 100.00
V2 tl_d_illegal_access sram_ctrl_tl_errors 4.110s 131.272us 20 20 100.00
V2 tl_d_outstanding_access sram_ctrl_csr_hw_reset 0.680s 22.608us 5 5 100.00
sram_ctrl_csr_rw 0.740s 14.855us 20 20 100.00
sram_ctrl_csr_aliasing 0.750s 60.101us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.870s 48.002us 20 20 100.00
V2 tl_d_partial_access sram_ctrl_csr_hw_reset 0.680s 22.608us 5 5 100.00
sram_ctrl_csr_rw 0.740s 14.855us 20 20 100.00
sram_ctrl_csr_aliasing 0.750s 60.101us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.870s 48.002us 20 20 100.00
V2 TOTAL 736 740 99.46
V2S passthru_mem_tl_intg_err sram_ctrl_passthru_mem_tl_intg_err 3.430s 4.310ms 20 20 100.00
V2S tl_intg_err sram_ctrl_sec_cm 3.220s 821.204us 5 5 100.00
sram_ctrl_tl_intg_err 2.480s 364.518us 20 20 100.00
V2S prim_count_check sram_ctrl_sec_cm 3.220s 821.204us 5 5 100.00
V2S sec_cm_bus_integrity sram_ctrl_tl_intg_err 2.480s 364.518us 20 20 100.00
V2S sec_cm_ctrl_config_regwen sram_ctrl_regwen 28.664m 3.353ms 50 50 100.00
V2S sec_cm_exec_config_regwen sram_ctrl_csr_rw 0.740s 14.855us 20 20 100.00
V2S sec_cm_exec_config_mubi sram_ctrl_executable 31.257m 5.211ms 50 50 100.00
V2S sec_cm_exec_intersig_mubi sram_ctrl_executable 31.257m 5.211ms 50 50 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi sram_ctrl_executable 31.257m 5.211ms 50 50 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi sram_ctrl_lc_escalation 11.510s 3.821ms 50 50 100.00
V2S sec_cm_mem_integrity sram_ctrl_passthru_mem_tl_intg_err 3.430s 4.310ms 20 20 100.00
V2S sec_cm_mem_readback sram_ctrl_smoke 2.473m 7.646ms 50 50 100.00
V2S sec_cm_mem_scramble sram_ctrl_smoke 2.473m 7.646ms 50 50 100.00
V2S sec_cm_addr_scramble sram_ctrl_smoke 2.473m 7.646ms 50 50 100.00
V2S sec_cm_instr_bus_lc_gated sram_ctrl_executable 31.257m 5.211ms 50 50 100.00
V2S sec_cm_ram_tl_lc_gate_fsm_sparse sram_ctrl_sec_cm 3.220s 821.204us 5 5 100.00
V2S sec_cm_key_global_esc sram_ctrl_lc_escalation 11.510s 3.821ms 50 50 100.00
V2S sec_cm_key_local_esc sram_ctrl_sec_cm 3.220s 821.204us 5 5 100.00
V2S sec_cm_init_ctr_redun sram_ctrl_sec_cm 3.220s 821.204us 5 5 100.00
V2S sec_cm_scramble_key_sideload sram_ctrl_smoke 2.473m 7.646ms 50 50 100.00
V2S sec_cm_tlul_fifo_ctr_redun sram_ctrl_sec_cm 3.220s 821.204us 5 5 100.00
V2S TOTAL 45 45 100.00
V3 stress_all_with_rand_reset sram_ctrl_stress_all_with_rand_reset 17.459m 1.694ms 40 50 80.00
V3 TOTAL 40 50 80.00
TOTAL 1025 1040 98.56

Testplan Progress

Items Total Written Passing Progress
V1 8 8 7 87.50
V2 16 16 15 93.75
V2S 3 3 3 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.95 99.16 94.27 99.72 100.00 95.95 99.12 97.44

Failure Buckets

Past Results