SRAM_CTRL/RET Simulation Results

Sunday July 07 2024 23:02:38 UTC

GitHub Revision: `2e5d86c9b5`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 75221189197949424635294305394615322888112457483844341597147780944629972574676

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.673m	733.517us	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.720s	49.840us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.730s	25.064us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.730s	2.436ms	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.760s	20.233us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.300s	38.250us	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.730s	25.064us	20	20	100.00
		sram_ctrl_csr_aliasing	0.760s	20.233us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	14.050s	8.860ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	6.350s	178.858us	50	50	100.00
V1		TOTAL			204	205	99.51
V2	multiple_keys	sram_ctrl_multiple_keys	25.259m	40.740ms	49	50	98.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	7.690m	18.871ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.450m	15.011ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	31.314m	13.237ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	11.160s	5.308ms	50	50	100.00
V2	executable	sram_ctrl_executable	31.434m	84.436ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	2.953m	435.884us	50	50	100.00
		sram_ctrl_partial_access_b2b	10.581m	91.657ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.467m	135.104us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.796m	150.491us	50	50	100.00
V2	regwen	sram_ctrl_regwen	36.437m	20.945ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	0.830s	191.386us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.522h	161.593ms	44	50	88.00
V2	alert_test	sram_ctrl_alert_test	0.740s	11.953us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	5.480s	2.147ms	19	20	95.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	5.480s	2.147ms	19	20	95.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.720s	49.840us	5	5	100.00
		sram_ctrl_csr_rw	0.730s	25.064us	20	20	100.00
		sram_ctrl_csr_aliasing	0.760s	20.233us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.870s	116.807us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.720s	49.840us	5	5	100.00
		sram_ctrl_csr_rw	0.730s	25.064us	20	20	100.00
		sram_ctrl_csr_aliasing	0.760s	20.233us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.870s	116.807us	20	20	100.00
V2		TOTAL			732	740	98.92
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	4.670s	812.784us	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	3.340s	703.361us	5	5	100.00
		sram_ctrl_tl_intg_err	3.280s	738.637us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	3.340s	703.361us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	3.280s	738.637us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	36.437m	20.945ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.730s	25.064us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	31.434m	84.436ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	31.434m	84.436ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	31.434m	84.436ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	11.160s	5.308ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	4.670s	812.784us	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_smoke	2.673m	733.517us	50	50	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.673m	733.517us	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.673m	733.517us	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	31.434m	84.436ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	3.340s	703.361us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	11.160s	5.308ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	3.340s	703.361us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	3.340s	703.361us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.673m	733.517us	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	3.340s	703.361us	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	18.117m	4.000ms	37	50	74.00
V3		TOTAL			37	50	74.00
		TOTAL			1018	1040	97.88

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	16	16	13	81.25
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.95	99.16	94.27	99.72	100.00	95.95	99.12	97.44

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:825) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 13 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 13 failures.
  - 1.sram_ctrl_stress_all_with_rand_reset.114634838979688661531537271520270645755237970329682088409479942990488522481643
    Line 293, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/1.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1050580553 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1050580553 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.sram_ctrl_stress_all_with_rand_reset.49237991334198368915304394388454746261184385239573901067570733576856777401424
    Line 369, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/4.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4360397365 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 4360397365 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 11 more failures.

Offending '(((((((((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))))' has 5 failures:

Test sram_ctrl_stress_all has 5 failures.

3.sram_ctrl_stress_all.49961373645594245190789252851576941874960169207126984870378647768653290213236
Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/3.sram_ctrl_stress_all/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @ 450056137 ps: (tlul_assert.sv:277) [ASSERT FAILED] dDataKnown_A
  UVM_INFO @ 450056137 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

16.sram_ctrl_stress_all.64452790400448001832065836818866603598182104303521931786305161467808404790674
Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/16.sram_ctrl_stress_all/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @ 395432369 ps: (tlul_assert.sv:277) [ASSERT FAILED] dDataKnown_A
  UVM_INFO @ 395432369 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Offending '((pend_req[*].pend == *'b0) || $test$plusargs("disable_assert_final_checks"))' has 1 failures:
- Test sram_ctrl_tl_errors has 1 failures.
  - 8.sram_ctrl_tl_errors.103580340561846778733522354463422996361915469454206904401368945460638897018279
    Line 309, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/8.sram_ctrl_tl_errors/latest/run.log
```
      Offending '((pend_req[115].pend == 1'b0) || $test$plusargs("disable_assert_final_checks"))'
  UVM_ERROR @ 514526648 ps: (tlul_assert.sv:301) [ASSERT FAILED] noOutstandingReqsAtEndOfSim_A
  UVM_INFO @ 514526648 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:267) [sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_multiple_keys has 1 failures.
  - 11.sram_ctrl_multiple_keys.101968563381502241825061373534900449079469252077329146837212537498565478759460
    Line 306, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/11.sram_ctrl_multiple_keys/latest/run.log
```
  UVM_FATAL @ 115003856887 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0x273ae9e5
  UVM_INFO @ 115003856887 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status reset value: * has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 14.sram_ctrl_csr_mem_rw_with_rand_reset.59795080768928216813797591856722395857461056470544072211900547676036592203844
    Line 280, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/14.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  35873626 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (56 [0x38] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status reset value: 0x0
  UVM_INFO @  35873626 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(!$isunknown(rdata_o))' has 1 failures:
- Test sram_ctrl_stress_all has 1 failures.
  - 23.sram_ctrl_stress_all.58054155451614597304070853916586399896555417178011950025699124305271410887236
    Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/23.sram_ctrl_stress_all/latest/run.log
```
      Offending '(!$isunknown(rdata_o))'
  UVM_ERROR @ 157403260 ps: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
  UVM_INFO @ 157403260 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```