SRAM_CTRL/RET Simulation Results

Friday July 12 2024 23:02:19 UTC

GitHub Revision: 5967df933a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 46476530947956470787268850137993439884379231200278174763551439909664842175844

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sram_ctrl_smoke 2.319m 738.205us 50 50 100.00
V1 csr_hw_reset sram_ctrl_csr_hw_reset 0.720s 159.836us 5 5 100.00
V1 csr_rw sram_ctrl_csr_rw 0.700s 23.325us 20 20 100.00
V1 csr_bit_bash sram_ctrl_csr_bit_bash 1.860s 78.429us 5 5 100.00
V1 csr_aliasing sram_ctrl_csr_aliasing 0.780s 248.102us 5 5 100.00
V1 csr_mem_rw_with_rand_reset sram_ctrl_csr_mem_rw_with_rand_reset 1.870s 44.235us 19 20 95.00
V1 regwen_csr_and_corresponding_lockable_csr sram_ctrl_csr_rw 0.700s 23.325us 20 20 100.00
sram_ctrl_csr_aliasing 0.780s 248.102us 5 5 100.00
V1 mem_walk sram_ctrl_mem_walk 12.480s 2.356ms 50 50 100.00
V1 mem_partial_access sram_ctrl_mem_partial_access 6.370s 200.578us 50 50 100.00
V1 TOTAL 204 205 99.51
V2 multiple_keys sram_ctrl_multiple_keys 30.595m 74.385ms 49 50 98.00
V2 stress_pipeline sram_ctrl_stress_pipeline 6.275m 32.662ms 50 50 100.00
V2 bijection sram_ctrl_bijection 1.337m 3.617ms 50 50 100.00
V2 access_during_key_req sram_ctrl_access_during_key_req 31.500m 30.415ms 50 50 100.00
V2 lc_escalation sram_ctrl_lc_escalation 10.450s 9.934ms 50 50 100.00
V2 executable sram_ctrl_executable 29.158m 21.123ms 50 50 100.00
V2 partial_access sram_ctrl_partial_access 2.440m 220.388us 50 50 100.00
sram_ctrl_partial_access_b2b 10.329m 220.142ms 50 50 100.00
V2 max_throughput sram_ctrl_max_throughput 2.851m 571.250us 50 50 100.00
sram_ctrl_throughput_w_partial_write 2.601m 444.809us 50 50 100.00
V2 regwen sram_ctrl_regwen 27.221m 15.075ms 50 50 100.00
V2 ram_cfg sram_ctrl_ram_cfg 0.850s 127.088us 50 50 100.00
V2 stress_all sram_ctrl_stress_all 2.100h 45.734ms 46 50 92.00
V2 alert_test sram_ctrl_alert_test 0.710s 45.575us 50 50 100.00
V2 tl_d_oob_addr_access sram_ctrl_tl_errors 5.350s 1.549ms 20 20 100.00
V2 tl_d_illegal_access sram_ctrl_tl_errors 5.350s 1.549ms 20 20 100.00
V2 tl_d_outstanding_access sram_ctrl_csr_hw_reset 0.720s 159.836us 5 5 100.00
sram_ctrl_csr_rw 0.700s 23.325us 20 20 100.00
sram_ctrl_csr_aliasing 0.780s 248.102us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.880s 78.922us 20 20 100.00
V2 tl_d_partial_access sram_ctrl_csr_hw_reset 0.720s 159.836us 5 5 100.00
sram_ctrl_csr_rw 0.700s 23.325us 20 20 100.00
sram_ctrl_csr_aliasing 0.780s 248.102us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.880s 78.922us 20 20 100.00
V2 TOTAL 735 740 99.32
V2S passthru_mem_tl_intg_err sram_ctrl_passthru_mem_tl_intg_err 3.420s 1.581ms 20 20 100.00
V2S tl_intg_err sram_ctrl_sec_cm 3.640s 426.213us 5 5 100.00
sram_ctrl_tl_intg_err 2.760s 1.588ms 20 20 100.00
V2S prim_count_check sram_ctrl_sec_cm 3.640s 426.213us 5 5 100.00
V2S sec_cm_bus_integrity sram_ctrl_tl_intg_err 2.760s 1.588ms 20 20 100.00
V2S sec_cm_ctrl_config_regwen sram_ctrl_regwen 27.221m 15.075ms 50 50 100.00
V2S sec_cm_exec_config_regwen sram_ctrl_csr_rw 0.700s 23.325us 20 20 100.00
V2S sec_cm_exec_config_mubi sram_ctrl_executable 29.158m 21.123ms 50 50 100.00
V2S sec_cm_exec_intersig_mubi sram_ctrl_executable 29.158m 21.123ms 50 50 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi sram_ctrl_executable 29.158m 21.123ms 50 50 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi sram_ctrl_lc_escalation 10.450s 9.934ms 50 50 100.00
V2S sec_cm_mem_integrity sram_ctrl_passthru_mem_tl_intg_err 3.420s 1.581ms 20 20 100.00
V2S sec_cm_mem_readback sram_ctrl_smoke 2.319m 738.205us 50 50 100.00
V2S sec_cm_mem_scramble sram_ctrl_smoke 2.319m 738.205us 50 50 100.00
V2S sec_cm_addr_scramble sram_ctrl_smoke 2.319m 738.205us 50 50 100.00
V2S sec_cm_instr_bus_lc_gated sram_ctrl_executable 29.158m 21.123ms 50 50 100.00
V2S sec_cm_ram_tl_lc_gate_fsm_sparse sram_ctrl_sec_cm 3.640s 426.213us 5 5 100.00
V2S sec_cm_key_global_esc sram_ctrl_lc_escalation 10.450s 9.934ms 50 50 100.00
V2S sec_cm_key_local_esc sram_ctrl_sec_cm 3.640s 426.213us 5 5 100.00
V2S sec_cm_init_ctr_redun sram_ctrl_sec_cm 3.640s 426.213us 5 5 100.00
V2S sec_cm_scramble_key_sideload sram_ctrl_smoke 2.319m 738.205us 50 50 100.00
V2S sec_cm_tlul_fifo_ctr_redun sram_ctrl_sec_cm 3.640s 426.213us 5 5 100.00
V2S TOTAL 45 45 100.00
V3 stress_all_with_rand_reset sram_ctrl_stress_all_with_rand_reset 7.790m 1.719ms 40 50 80.00
V3 TOTAL 40 50 80.00
TOTAL 1024 1040 98.46

Testplan Progress

Items Total Written Passing Progress
V1 8 8 7 87.50
V2 16 16 14 87.50
V2S 3 3 3 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.95 99.16 94.27 99.72 100.00 95.95 99.12 97.44

Failure Buckets

Past Results