SRAM_CTRL/RET Simulation Results

Wednesday July 10 2024 23:02:26 UTC

GitHub Revision: `39211701b5`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 52262812535389540465251148247405743574935129745685597413714598750252192397067

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.800m	1.373ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.720s	12.844us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.730s	18.016us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.260s	172.107us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.770s	21.667us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.430s	149.225us	17	20	85.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.730s	18.016us	20	20	100.00
		sram_ctrl_csr_aliasing	0.770s	21.667us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	12.330s	2.706ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	6.430s	755.535us	50	50	100.00
V1		TOTAL			202	205	98.54
V2	multiple_keys	sram_ctrl_multiple_keys	34.428m	58.386ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	8.158m	10.591ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.439m	10.566ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	35.934m	3.716ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	10.450s	949.620us	50	50	100.00
V2	executable	sram_ctrl_executable	33.415m	12.690ms	49	50	98.00
V2	partial_access	sram_ctrl_partial_access	2.786m	2.500ms	50	50	100.00
		sram_ctrl_partial_access_b2b	9.887m	148.978ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.474m	269.130us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.769m	158.991us	50	50	100.00
V2	regwen	sram_ctrl_regwen	37.216m	44.809ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	0.870s	57.802us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.617h	206.587ms	44	50	88.00
V2	alert_test	sram_ctrl_alert_test	0.780s	15.285us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	5.790s	587.982us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	5.790s	587.982us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.720s	12.844us	5	5	100.00
		sram_ctrl_csr_rw	0.730s	18.016us	20	20	100.00
		sram_ctrl_csr_aliasing	0.770s	21.667us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.840s	64.802us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.720s	12.844us	5	5	100.00
		sram_ctrl_csr_rw	0.730s	18.016us	20	20	100.00
		sram_ctrl_csr_aliasing	0.770s	21.667us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.840s	64.802us	20	20	100.00
V2		TOTAL			733	740	99.05
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	4.270s	3.470ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	4.830s	3.033ms	5	5	100.00
		sram_ctrl_tl_intg_err	3.600s	2.330ms	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	4.830s	3.033ms	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	3.600s	2.330ms	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	37.216m	44.809ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.730s	18.016us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	33.415m	12.690ms	49	50	98.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	33.415m	12.690ms	49	50	98.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	33.415m	12.690ms	49	50	98.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	10.450s	949.620us	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	4.270s	3.470ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_smoke	2.800m	1.373ms	50	50	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.800m	1.373ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.800m	1.373ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	33.415m	12.690ms	49	50	98.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	4.830s	3.033ms	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	10.450s	949.620us	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	4.830s	3.033ms	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	4.830s	3.033ms	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.800m	1.373ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	4.830s	3.033ms	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	22.941m	2.265ms	45	50	90.00
V3		TOTAL			45	50	90.00
		TOTAL			1025	1040	98.56

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	16	16	14	87.50
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.95	99.16	94.27	99.72	100.00	95.95	99.12	97.44

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:825) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 5 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 5 failures.
  - 5.sram_ctrl_stress_all_with_rand_reset.89897605051030664905664504043539260377438796413520571808044054762112494229538
    Line 279, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/5.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 583388266 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 583388266 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 8.sram_ctrl_stress_all_with_rand_reset.80871415792044213094146144893585620733677429293929781886090092661583157346176
    Line 341, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/8.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2941565683 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2941565683 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.

Offending '(((((((((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))))' has 4 failures:

Test sram_ctrl_stress_all has 4 failures.

25.sram_ctrl_stress_all.19633381289878763174762855750662728523974671318844207069198698758092004025495
Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/25.sram_ctrl_stress_all/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @  96216308 ps: (tlul_assert.sv:277) [ASSERT FAILED] dDataKnown_A
  UVM_INFO @  96216308 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

28.sram_ctrl_stress_all.108299375979213220751097044351697295937161717494870293269252146349227568517813
Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/28.sram_ctrl_stress_all/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @ 171230862 ps: (tlul_assert.sv:277) [ASSERT FAILED] dDataKnown_A
  UVM_INFO @ 171230862 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_FATAL (cip_base_vseq.sv:267) [sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=* has 2 failures:
- Test sram_ctrl_stress_all has 1 failures.
  - 3.sram_ctrl_stress_all.86208419088636851427421742322185300459825827387056903726416220826554927318865
    Line 289, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/3.sram_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 57672459968 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0xe2a07d7d
  UVM_INFO @ 57672459968 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test sram_ctrl_executable has 1 failures.
  - 34.sram_ctrl_executable.24726165032430317033551782363636979528169178858916028509982879858523136791378
    Line 284, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/34.sram_ctrl_executable/latest/run.log
```
  UVM_FATAL @ 33174863414 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0x7e2dd8f2
  UVM_INFO @ 33174863414 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status reset value: * has 2 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 2 failures.
  - 12.sram_ctrl_csr_mem_rw_with_rand_reset.16507132010404284160999291662867052116357160311961770595118324583679846674995
    Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/12.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 199040033 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (56 [0x38] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status reset value: 0x0
  UVM_INFO @ 199040033 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 13.sram_ctrl_csr_mem_rw_with_rand_reset.96238291311037373378009683702847181314892853205478809983324818301347286061353
    Line 280, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/13.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  95681441 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (40 [0x28] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status reset value: 0x0
  UVM_INFO @  95681441 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: * has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 18.sram_ctrl_csr_mem_rw_with_rand_reset.70390400692204504578633578480199225863577226105597761575185465917129315081512
    Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/18.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  29778998 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (10 [0xa] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: 0x9
  UVM_INFO @  29778998 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(!$isunknown(rdata_o))' has 1 failures:
- Test sram_ctrl_stress_all has 1 failures.
  - 46.sram_ctrl_stress_all.61003328427213157535845735334767331359523643265832414955389075741324343291421
    Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/46.sram_ctrl_stress_all/latest/run.log
```
      Offending '(!$isunknown(rdata_o))'
  UVM_ERROR @  40269186 ps: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
  UVM_INFO @  40269186 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```