SRAM_CTRL/RET Simulation Results

Saturday July 13 2024 23:02:33 UTC

GitHub Revision: `d51405297e`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 101086804359139103922259090811397817605469534164678958852189348539757618502888

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	3.054m	640.534us	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.680s	24.715us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.740s	145.157us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.410s	887.113us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.750s	160.941us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.040s	195.132us	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.740s	145.157us	20	20	100.00
		sram_ctrl_csr_aliasing	0.750s	160.941us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	12.940s	3.577ms	49	50	98.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	6.130s	440.329us	50	50	100.00
V1		TOTAL			203	205	99.02
V2	multiple_keys	sram_ctrl_multiple_keys	36.249m	107.461ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	7.292m	4.380ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.479m	90.933ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	34.748m	8.678ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	13.600s	7.884ms	50	50	100.00
V2	executable	sram_ctrl_executable	33.615m	169.672ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	2.483m	4.898ms	50	50	100.00
		sram_ctrl_partial_access_b2b	9.378m	99.587ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.680m	651.062us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.753m	153.278us	50	50	100.00
V2	regwen	sram_ctrl_regwen	31.859m	82.807ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.010s	97.082us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.248h	92.086ms	45	50	90.00
V2	alert_test	sram_ctrl_alert_test	0.730s	13.825us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.510s	784.175us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.510s	784.175us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.680s	24.715us	5	5	100.00
		sram_ctrl_csr_rw	0.740s	145.157us	20	20	100.00
		sram_ctrl_csr_aliasing	0.750s	160.941us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.830s	78.924us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.680s	24.715us	5	5	100.00
		sram_ctrl_csr_rw	0.740s	145.157us	20	20	100.00
		sram_ctrl_csr_aliasing	0.750s	160.941us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.830s	78.924us	20	20	100.00
V2		TOTAL			735	740	99.32
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	4.450s	4.079ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	5.880s	1.151ms	5	5	100.00
		sram_ctrl_tl_intg_err	3.400s	3.120ms	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	5.880s	1.151ms	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	3.400s	3.120ms	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	31.859m	82.807ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.740s	145.157us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	33.615m	169.672ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	33.615m	169.672ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	33.615m	169.672ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	13.600s	7.884ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	4.450s	4.079ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_smoke	3.054m	640.534us	50	50	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	3.054m	640.534us	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	3.054m	640.534us	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	33.615m	169.672ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	5.880s	1.151ms	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	13.600s	7.884ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	5.880s	1.151ms	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	5.880s	1.151ms	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	3.054m	640.534us	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	5.880s	1.151ms	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	15.298m	2.272ms	39	50	78.00
V3		TOTAL			39	50	78.00
		TOTAL			1022	1040	98.27

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	6	75.00
V2	16	16	15	93.75
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.95	99.16	94.27	99.72	100.00	95.95	99.12	97.44

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:825) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 10 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 10 failures.
  - 0.sram_ctrl_stress_all_with_rand_reset.107974194314322546097616309401579328218759818582418771145079029671844657371809
    Line 338, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/0.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1890728746 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1890728746 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 6.sram_ctrl_stress_all_with_rand_reset.47669310074128619461083582457929900562018480837642019709111850968754138074259
    Line 321, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/6.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1083022795 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1083022795 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 8 more failures.

Offending '(((((((((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))))' has 4 failures:

Test sram_ctrl_stress_all has 4 failures.

15.sram_ctrl_stress_all.3087132088643861768743176889660090258277130060022746140323362857740335660461
Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/15.sram_ctrl_stress_all/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @  24307680 ps: (tlul_assert.sv:277) [ASSERT FAILED] dDataKnown_A
  UVM_INFO @  24307680 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

30.sram_ctrl_stress_all.18228170270024563589385592917836766316419759786242912207857820595208829219076
Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/30.sram_ctrl_stress_all/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @  99817508 ps: (tlul_assert.sv:277) [ASSERT FAILED] dDataKnown_A
  UVM_INFO @  99817508 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Offending '((pend_req[*].pend == *'b0) || $test$plusargs("disable_assert_final_checks"))' has 1 failures:
- Test sram_ctrl_mem_walk has 1 failures.
  - 12.sram_ctrl_mem_walk.7168947172834868223841307087435691048874483925559297324966375234572845015309
    Line 334, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/12.sram_ctrl_mem_walk/latest/run.log
```
      Offending '((pend_req[2].pend == 1'b0) || $test$plusargs("disable_assert_final_checks"))'
  UVM_ERROR @ 1768462875 ps: (tlul_assert.sv:301) [ASSERT FAILED] noOutstandingReqsAtEndOfSim_A
  UVM_INFO @ 1768462875 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:267) [sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 1 failures.
  - 12.sram_ctrl_stress_all_with_rand_reset.114649435405467442954889655944351804963388078502656235025624841497343510500393
    Line 315, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/12.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 17477743039 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0x84d4636f
  UVM_INFO @ 17477743039 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_done reset value: * has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 19.sram_ctrl_csr_mem_rw_with_rand_reset.5197729762848725505695186407343009495601441919911839501646839653368481650408
    Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/19.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  23884424 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status.init_done reset value: 0x0
  UVM_INFO @  23884424 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:267) [sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_stress_all has 1 failures.
  - 37.sram_ctrl_stress_all.59324864504251542179809029192012120527486269558160107891917488313551994509811
    Line 293, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/37.sram_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 52987278205 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0xa4f0f67f
  UVM_INFO @ 52987278205 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```