SRAM_CTRL/RET Simulation Results

Sunday July 14 2024 23:02:31 UTC

GitHub Revision: `c04cc5d074`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 63544391231451201456762274895161998707503467555380647510071702152169450996489

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	3.044m	643.396us	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.760s	31.447us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.720s	13.035us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.230s	474.599us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.770s	36.330us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	11.220s	10.005ms	16	20	80.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.720s	13.035us	20	20	100.00
		sram_ctrl_csr_aliasing	0.770s	36.330us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	14.630s	4.370ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	6.790s	2.878ms	50	50	100.00
V1		TOTAL			201	205	98.05
V2	multiple_keys	sram_ctrl_multiple_keys	36.131m	45.174ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	7.150m	4.526ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.389m	45.476ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	31.670m	4.378ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	10.160s	6.836ms	50	50	100.00
V2	executable	sram_ctrl_executable	37.473m	57.601ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	2.829m	1.552ms	50	50	100.00
		sram_ctrl_partial_access_b2b	11.548m	24.087ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.690m	2.132ms	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.982m	161.031us	50	50	100.00
V2	regwen	sram_ctrl_regwen	54.025m	53.443ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	0.870s	57.359us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.300h	18.472ms	47	50	94.00
V2	alert_test	sram_ctrl_alert_test	0.760s	41.301us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.920s	498.304us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.920s	498.304us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.760s	31.447us	5	5	100.00
		sram_ctrl_csr_rw	0.720s	13.035us	20	20	100.00
		sram_ctrl_csr_aliasing	0.770s	36.330us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.860s	45.690us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.760s	31.447us	5	5	100.00
		sram_ctrl_csr_rw	0.720s	13.035us	20	20	100.00
		sram_ctrl_csr_aliasing	0.770s	36.330us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.860s	45.690us	20	20	100.00
V2		TOTAL			737	740	99.59
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	3.760s	4.875ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	3.190s	908.491us	5	5	100.00
		sram_ctrl_tl_intg_err	2.690s	329.438us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	3.190s	908.491us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.690s	329.438us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	54.025m	53.443ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.720s	13.035us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	37.473m	57.601ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	37.473m	57.601ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	37.473m	57.601ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	10.160s	6.836ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	3.760s	4.875ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_smoke	3.044m	643.396us	50	50	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	3.044m	643.396us	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	3.044m	643.396us	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	37.473m	57.601ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	3.190s	908.491us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	10.160s	6.836ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	3.190s	908.491us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	3.190s	908.491us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	3.044m	643.396us	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	3.190s	908.491us	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	19.545m	10.813ms	40	50	80.00
V3		TOTAL			40	50	80.00
		TOTAL			1023	1040	98.37

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	16	16	15	93.75
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.95	99.16	94.27	99.72	100.00	95.95	99.12	97.44

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:825) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 10 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 10 failures.
  - 0.sram_ctrl_stress_all_with_rand_reset.62503643939386813913043956755376961538844861688925401122410769125104884620081
    Line 407, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/0.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3157205085 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3157205085 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 10.sram_ctrl_stress_all_with_rand_reset.103632496343290418481548510888559667563120371244004710255375840599202124962477
    Line 293, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/10.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2786196348 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2786196348 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 8 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: * has 2 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 2 failures.
  - 4.sram_ctrl_csr_mem_rw_with_rand_reset.42571642038876538892875283639252359439039894838439381260794665669997947376381
    Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/4.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  94811238 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (12 [0xc] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: 0x9
  UVM_INFO @  94811238 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 13.sram_ctrl_csr_mem_rw_with_rand_reset.26641300466478727003897090849519286833335082850977523744630019162745375357543
    Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/13.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  25069949 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (12 [0xc] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: 0x9
  UVM_INFO @  25069949 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Offending '(((((((((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))))' has 2 failures:

Test sram_ctrl_stress_all has 2 failures.

6.sram_ctrl_stress_all.87756680624600755911060634928074595494342001866876261951305830600927972119948
Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/6.sram_ctrl_stress_all/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @ 811111288 ps: (tlul_assert.sv:277) [ASSERT FAILED] dDataKnown_A
  UVM_INFO @ 811111288 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

9.sram_ctrl_stress_all.20468324034341119657123136192006851633996368244225186365626926509454125464303
Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/9.sram_ctrl_stress_all/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @  23999375 ps: (tlul_assert.sv:277) [ASSERT FAILED] dDataKnown_A
  UVM_INFO @  23999375 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: * has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 1.sram_ctrl_csr_mem_rw_with_rand_reset.12764867091138198592892483980159236023236309522960287609796893674836159259082
    Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/1.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  93603282 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (14 [0xe] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: 0x9
  UVM_INFO @  93603282 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (sram_ctrl_base_vseq.sv:149) [sram_ctrl_common_vseq] Timed out waiting for initialization done has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 15.sram_ctrl_csr_mem_rw_with_rand_reset.10179282821115070810927805249558266054903301777537121683052696494928984599104
    Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/15.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10004517347 ps: (sram_ctrl_base_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Timed out waiting for initialization done
  UVM_INFO @ 10004517347 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(!$isunknown(rdata_o))' has 1 failures:
- Test sram_ctrl_stress_all has 1 failures.
  - 26.sram_ctrl_stress_all.29112040021829698086438339571713991730708589715868195730226701253219036319103
    Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/26.sram_ctrl_stress_all/latest/run.log
```
      Offending '(!$isunknown(rdata_o))'
  UVM_ERROR @  74104961 ps: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
  UVM_INFO @  74104961 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```