SRAM_CTRL/RET Simulation Results

Monday July 15 2024 23:02:37 UTC

GitHub Revision: a04e34f557

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 78455839157994684327892029952813991699715169368132023215715425571513813941951

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sram_ctrl_smoke 2.757m 514.426us 50 50 100.00
V1 csr_hw_reset sram_ctrl_csr_hw_reset 0.710s 31.594us 5 5 100.00
V1 csr_rw sram_ctrl_csr_rw 0.750s 13.247us 20 20 100.00
V1 csr_bit_bash sram_ctrl_csr_bit_bash 1.990s 120.139us 5 5 100.00
V1 csr_aliasing sram_ctrl_csr_aliasing 0.760s 22.115us 5 5 100.00
V1 csr_mem_rw_with_rand_reset sram_ctrl_csr_mem_rw_with_rand_reset 3.110s 387.733us 18 20 90.00
V1 regwen_csr_and_corresponding_lockable_csr sram_ctrl_csr_rw 0.750s 13.247us 20 20 100.00
sram_ctrl_csr_aliasing 0.760s 22.115us 5 5 100.00
V1 mem_walk sram_ctrl_mem_walk 12.750s 653.977us 50 50 100.00
V1 mem_partial_access sram_ctrl_mem_partial_access 6.740s 370.946us 50 50 100.00
V1 TOTAL 203 205 99.02
V2 multiple_keys sram_ctrl_multiple_keys 47.404m 209.851ms 50 50 100.00
V2 stress_pipeline sram_ctrl_stress_pipeline 7.418m 15.895ms 50 50 100.00
V2 bijection sram_ctrl_bijection 1.621m 15.038ms 50 50 100.00
V2 access_during_key_req sram_ctrl_access_during_key_req 55.979m 9.243ms 50 50 100.00
V2 lc_escalation sram_ctrl_lc_escalation 10.900s 759.750us 50 50 100.00
V2 executable sram_ctrl_executable 38.404m 69.753ms 49 50 98.00
V2 partial_access sram_ctrl_partial_access 2.983m 3.064ms 50 50 100.00
sram_ctrl_partial_access_b2b 11.093m 333.805ms 50 50 100.00
V2 max_throughput sram_ctrl_max_throughput 2.626m 140.252us 50 50 100.00
sram_ctrl_throughput_w_partial_write 2.715m 597.156us 50 50 100.00
V2 regwen sram_ctrl_regwen 40.039m 16.879ms 50 50 100.00
V2 ram_cfg sram_ctrl_ram_cfg 0.860s 35.302us 50 50 100.00
V2 stress_all sram_ctrl_stress_all 1.491h 15.782ms 47 50 94.00
V2 alert_test sram_ctrl_alert_test 0.710s 15.393us 50 50 100.00
V2 tl_d_oob_addr_access sram_ctrl_tl_errors 5.470s 1.793ms 20 20 100.00
V2 tl_d_illegal_access sram_ctrl_tl_errors 5.470s 1.793ms 20 20 100.00
V2 tl_d_outstanding_access sram_ctrl_csr_hw_reset 0.710s 31.594us 5 5 100.00
sram_ctrl_csr_rw 0.750s 13.247us 20 20 100.00
sram_ctrl_csr_aliasing 0.760s 22.115us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.880s 28.490us 20 20 100.00
V2 tl_d_partial_access sram_ctrl_csr_hw_reset 0.710s 31.594us 5 5 100.00
sram_ctrl_csr_rw 0.750s 13.247us 20 20 100.00
sram_ctrl_csr_aliasing 0.760s 22.115us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.880s 28.490us 20 20 100.00
V2 TOTAL 736 740 99.46
V2S passthru_mem_tl_intg_err sram_ctrl_passthru_mem_tl_intg_err 4.460s 717.936us 20 20 100.00
V2S tl_intg_err sram_ctrl_sec_cm 3.180s 229.825us 5 5 100.00
sram_ctrl_tl_intg_err 2.810s 347.194us 20 20 100.00
V2S prim_count_check sram_ctrl_sec_cm 3.180s 229.825us 5 5 100.00
V2S sec_cm_bus_integrity sram_ctrl_tl_intg_err 2.810s 347.194us 20 20 100.00
V2S sec_cm_ctrl_config_regwen sram_ctrl_regwen 40.039m 16.879ms 50 50 100.00
V2S sec_cm_exec_config_regwen sram_ctrl_csr_rw 0.750s 13.247us 20 20 100.00
V2S sec_cm_exec_config_mubi sram_ctrl_executable 38.404m 69.753ms 49 50 98.00
V2S sec_cm_exec_intersig_mubi sram_ctrl_executable 38.404m 69.753ms 49 50 98.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi sram_ctrl_executable 38.404m 69.753ms 49 50 98.00
V2S sec_cm_lc_escalate_en_intersig_mubi sram_ctrl_lc_escalation 10.900s 759.750us 50 50 100.00
V2S sec_cm_mem_integrity sram_ctrl_passthru_mem_tl_intg_err 4.460s 717.936us 20 20 100.00
V2S sec_cm_mem_readback sram_ctrl_smoke 2.757m 514.426us 50 50 100.00
V2S sec_cm_mem_scramble sram_ctrl_smoke 2.757m 514.426us 50 50 100.00
V2S sec_cm_addr_scramble sram_ctrl_smoke 2.757m 514.426us 50 50 100.00
V2S sec_cm_instr_bus_lc_gated sram_ctrl_executable 38.404m 69.753ms 49 50 98.00
V2S sec_cm_ram_tl_lc_gate_fsm_sparse sram_ctrl_sec_cm 3.180s 229.825us 5 5 100.00
V2S sec_cm_key_global_esc sram_ctrl_lc_escalation 10.900s 759.750us 50 50 100.00
V2S sec_cm_key_local_esc sram_ctrl_sec_cm 3.180s 229.825us 5 5 100.00
V2S sec_cm_init_ctr_redun sram_ctrl_sec_cm 3.180s 229.825us 5 5 100.00
V2S sec_cm_scramble_key_sideload sram_ctrl_smoke 2.757m 514.426us 50 50 100.00
V2S sec_cm_tlul_fifo_ctr_redun sram_ctrl_sec_cm 3.180s 229.825us 5 5 100.00
V2S TOTAL 45 45 100.00
V3 stress_all_with_rand_reset sram_ctrl_stress_all_with_rand_reset 14.572m 8.506ms 40 50 80.00
V3 TOTAL 40 50 80.00
TOTAL 1024 1040 98.46

Testplan Progress

Items Total Written Passing Progress
V1 8 8 7 87.50
V2 16 16 14 87.50
V2S 3 3 3 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.95 99.16 94.27 99.72 100.00 95.95 99.12 97.44

Failure Buckets

Past Results