SRAM_CTRL/RET Simulation Results

Tuesday July 16 2024 23:15:02 UTC

GitHub Revision: aad711e1bc

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 38297581588405771015102977205739484163575733999253050480227719508149669635625

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sram_ctrl_smoke 2.944m 2.750ms 50 50 100.00
V1 csr_hw_reset sram_ctrl_csr_hw_reset 0.720s 45.800us 5 5 100.00
V1 csr_rw sram_ctrl_csr_rw 0.680s 40.433us 20 20 100.00
V1 csr_bit_bash sram_ctrl_csr_bit_bash 2.250s 296.575us 5 5 100.00
V1 csr_aliasing sram_ctrl_csr_aliasing 0.750s 85.203us 5 5 100.00
V1 csr_mem_rw_with_rand_reset sram_ctrl_csr_mem_rw_with_rand_reset 2.590s 42.217us 18 20 90.00
V1 regwen_csr_and_corresponding_lockable_csr sram_ctrl_csr_rw 0.680s 40.433us 20 20 100.00
sram_ctrl_csr_aliasing 0.750s 85.203us 5 5 100.00
V1 mem_walk sram_ctrl_mem_walk 12.050s 9.296ms 50 50 100.00
V1 mem_partial_access sram_ctrl_mem_partial_access 6.170s 1.419ms 50 50 100.00
V1 TOTAL 203 205 99.02
V2 multiple_keys sram_ctrl_multiple_keys 31.561m 36.236ms 50 50 100.00
V2 stress_pipeline sram_ctrl_stress_pipeline 6.315m 16.145ms 50 50 100.00
V2 bijection sram_ctrl_bijection 1.511m 30.078ms 50 50 100.00
V2 access_during_key_req sram_ctrl_access_during_key_req 36.444m 4.891ms 50 50 100.00
V2 lc_escalation sram_ctrl_lc_escalation 10.680s 3.429ms 50 50 100.00
V2 executable sram_ctrl_executable 32.667m 23.033ms 50 50 100.00
V2 partial_access sram_ctrl_partial_access 2.556m 3.305ms 50 50 100.00
sram_ctrl_partial_access_b2b 8.955m 77.254ms 50 50 100.00
V2 max_throughput sram_ctrl_max_throughput 2.189m 437.439us 50 50 100.00
sram_ctrl_throughput_w_partial_write 2.565m 161.458us 50 50 100.00
V2 regwen sram_ctrl_regwen 32.679m 19.233ms 50 50 100.00
V2 ram_cfg sram_ctrl_ram_cfg 0.820s 46.081us 50 50 100.00
V2 stress_all sram_ctrl_stress_all 1.742h 191.940ms 48 50 96.00
V2 alert_test sram_ctrl_alert_test 0.700s 19.422us 50 50 100.00
V2 tl_d_oob_addr_access sram_ctrl_tl_errors 5.860s 314.120us 20 20 100.00
V2 tl_d_illegal_access sram_ctrl_tl_errors 5.860s 314.120us 20 20 100.00
V2 tl_d_outstanding_access sram_ctrl_csr_hw_reset 0.720s 45.800us 5 5 100.00
sram_ctrl_csr_rw 0.680s 40.433us 20 20 100.00
sram_ctrl_csr_aliasing 0.750s 85.203us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.850s 26.374us 20 20 100.00
V2 tl_d_partial_access sram_ctrl_csr_hw_reset 0.720s 45.800us 5 5 100.00
sram_ctrl_csr_rw 0.680s 40.433us 20 20 100.00
sram_ctrl_csr_aliasing 0.750s 85.203us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.850s 26.374us 20 20 100.00
V2 TOTAL 738 740 99.73
V2S passthru_mem_tl_intg_err sram_ctrl_passthru_mem_tl_intg_err 3.840s 1.517ms 20 20 100.00
V2S tl_intg_err sram_ctrl_sec_cm 3.410s 749.492us 5 5 100.00
sram_ctrl_tl_intg_err 2.620s 193.276us 20 20 100.00
V2S prim_count_check sram_ctrl_sec_cm 3.410s 749.492us 5 5 100.00
V2S sec_cm_bus_integrity sram_ctrl_tl_intg_err 2.620s 193.276us 20 20 100.00
V2S sec_cm_ctrl_config_regwen sram_ctrl_regwen 32.679m 19.233ms 50 50 100.00
V2S sec_cm_exec_config_regwen sram_ctrl_csr_rw 0.680s 40.433us 20 20 100.00
V2S sec_cm_exec_config_mubi sram_ctrl_executable 32.667m 23.033ms 50 50 100.00
V2S sec_cm_exec_intersig_mubi sram_ctrl_executable 32.667m 23.033ms 50 50 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi sram_ctrl_executable 32.667m 23.033ms 50 50 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi sram_ctrl_lc_escalation 10.680s 3.429ms 50 50 100.00
V2S sec_cm_mem_integrity sram_ctrl_passthru_mem_tl_intg_err 3.840s 1.517ms 20 20 100.00
V2S sec_cm_mem_readback sram_ctrl_smoke 2.944m 2.750ms 50 50 100.00
V2S sec_cm_mem_scramble sram_ctrl_smoke 2.944m 2.750ms 50 50 100.00
V2S sec_cm_addr_scramble sram_ctrl_smoke 2.944m 2.750ms 50 50 100.00
V2S sec_cm_instr_bus_lc_gated sram_ctrl_executable 32.667m 23.033ms 50 50 100.00
V2S sec_cm_ram_tl_lc_gate_fsm_sparse sram_ctrl_sec_cm 3.410s 749.492us 5 5 100.00
V2S sec_cm_key_global_esc sram_ctrl_lc_escalation 10.680s 3.429ms 50 50 100.00
V2S sec_cm_key_local_esc sram_ctrl_sec_cm 3.410s 749.492us 5 5 100.00
V2S sec_cm_init_ctr_redun sram_ctrl_sec_cm 3.410s 749.492us 5 5 100.00
V2S sec_cm_scramble_key_sideload sram_ctrl_smoke 2.944m 2.750ms 50 50 100.00
V2S sec_cm_tlul_fifo_ctr_redun sram_ctrl_sec_cm 3.410s 749.492us 5 5 100.00
V2S TOTAL 45 45 100.00
V3 stress_all_with_rand_reset sram_ctrl_stress_all_with_rand_reset 12.460m 15.620ms 44 50 88.00
V3 TOTAL 44 50 88.00
TOTAL 1030 1040 99.04

Testplan Progress

Items Total Written Passing Progress
V1 8 8 7 87.50
V2 16 16 15 93.75
V2S 3 3 3 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.98 99.16 94.27 99.72 100.00 95.95 99.12 97.62

Failure Buckets

Past Results