Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
31.55	0.00	0.00	94.65				dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	68578499	10662	0	0
auto_block_debounce_ctl_rd_A	68578499	1236	0	0
auto_block_out_ctl_rd_A	68578499	1860	0	0
com_det_ctl_0_rd_A	68578499	1050	0	0
com_det_ctl_1_rd_A	68578499	1164	0	0
com_det_ctl_2_rd_A	68578499	1033	0	0
com_det_ctl_3_rd_A	68578499	1015	0	0
com_out_ctl_0_rd_A	68578499	1650	0	0
com_out_ctl_1_rd_A	68578499	1728	0	0
com_out_ctl_2_rd_A	68578499	1529	0	0
com_out_ctl_3_rd_A	68578499	1560	0	0
com_pre_det_ctl_0_rd_A	68578499	1056	0	0
com_pre_det_ctl_1_rd_A	68578499	1079	0	0
com_pre_det_ctl_2_rd_A	68578499	977	0	0
com_pre_det_ctl_3_rd_A	68578499	1011	0	0
com_pre_sel_ctl_0_rd_A	68578499	1897	0	0
com_pre_sel_ctl_1_rd_A	68578499	1927	0	0
com_pre_sel_ctl_2_rd_A	68578499	1668	0	0
com_pre_sel_ctl_3_rd_A	68578499	1609	0	0
com_sel_ctl_0_rd_A	68578499	1892	0	0
com_sel_ctl_1_rd_A	68578499	1640	0	0
com_sel_ctl_2_rd_A	68578499	1717	0	0
com_sel_ctl_3_rd_A	68578499	1996	0	0
ec_rst_ctl_rd_A	68578499	989	0	0
intr_enable_rd_A	68578499	1703	0	0
key_intr_ctl_rd_A	68578499	3120	0	0
key_intr_debounce_ctl_rd_A	68578499	1057	0	0
key_invert_ctl_rd_A	68578499	3023	0	0
pin_allowed_ctl_rd_A	68578499	3875	0	0
pin_out_ctl_rd_A	68578499	2414	0	0
pin_out_value_rd_A	68578499	2490	0	0
regwen_rd_A	68578499	1452	0	0
ulp_ac_debounce_ctl_rd_A	68578499	1036	0	0
ulp_ctl_rd_A	68578499	996	0	0
ulp_lid_debounce_ctl_rd_A	68578499	1053	0	0
ulp_pwrb_debounce_ctl_rd_A	68578499	1051	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	68578499	10662	0	0
T2	27860	9	0	0
T3	276048	0	0	0
T4	215809	5	0	0
T5	407814	6	0	0
T6	97015	0	0	0
T7	199481	470	0	0
T8	125112	0	0	0
T9	193492	0	0	0
T12	0	5	0	0
T14	210715	0	0	0
T15	119198	0	0	0
T16	0	592	0	0
T17	0	9	0	0
T18	0	546	0	0
T19	0	12	0	0
T20	0	771	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	68578499	1236	0	0
T1	650547	10	0	0
T2	27860	0	0	0
T3	276048	0	0	0
T4	215809	72	0	0
T5	407814	122	0	0
T6	97015	0	0	0
T7	199481	0	0	0
T8	125112	0	0	0
T13	0	74	0	0
T14	210715	0	0	0
T15	119198	0	0	0
T18	0	3	0	0
T20	0	21	0	0
T22	0	19	0	0
T29	0	258	0	0
T30	0	4	0	0
T44	0	12	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	68578499	1860	0	0
T1	650547	33	0	0
T2	27860	0	0	0
T3	276048	0	0	0
T4	215809	108	0	0
T5	407814	169	0	0
T6	97015	0	0	0
T7	199481	0	0	0
T8	125112	0	0	0
T13	0	80	0	0
T14	210715	0	0	0
T15	119198	0	0	0
T18	0	12	0	0
T20	0	2	0	0
T22	0	9	0	0
T29	0	298	0	0
T30	0	1	0	0
T44	0	3	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	68578499	1050	0	0
T1	650547	32	0	0
T2	27860	0	0	0
T3	276048	0	0	0
T4	215809	33	0	0
T5	407814	79	0	0
T6	97015	0	0	0
T7	199481	0	0	0
T8	125112	0	0	0
T13	0	88	0	0
T14	210715	0	0	0
T15	119198	0	0	0
T18	0	6	0	0
T20	0	8	0	0
T22	0	11	0	0
T29	0	293	0	0
T30	0	8	0	0
T44	0	7	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	68578499	1164	0	0
T1	650547	26	0	0
T2	27860	0	0	0
T3	276048	0	0	0
T4	215809	32	0	0
T5	407814	55	0	0
T6	97015	0	0	0
T7	199481	0	0	0
T8	125112	0	0	0
T13	0	81	0	0
T14	210715	0	0	0
T15	119198	0	0	0
T18	0	2	0	0
T20	0	16	0	0
T22	0	13	0	0
T29	0	355	0	0
T30	0	8	0	0
T44	0	25	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	68578499	1033	0	0
T1	650547	50	0	0
T2	27860	0	0	0
T3	276048	0	0	0
T4	215809	16	0	0
T5	407814	77	0	0
T6	97015	0	0	0
T7	199481	0	0	0
T8	125112	0	0	0
T13	0	79	0	0
T14	210715	0	0	0
T15	119198	0	0	0
T18	0	10	0	0
T20	0	3	0	0
T22	0	13	0	0
T29	0	256	0	0
T44	0	2	0	0
T52	0	25	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	68578499	1015	0	0
T4	215809	36	0	0
T5	407814	80	0	0
T7	199481	0	0	0
T8	125112	0	0	0
T9	193492	0	0	0
T11	79454	0	0	0
T13	0	58	0	0
T14	210715	0	0	0
T15	119198	0	0	0
T16	196247	0	0	0
T18	0	15	0	0
T20	0	5	0	0
T22	0	3	0	0
T23	34325	0	0	0
T29	0	288	0	0
T30	0	9	0	0
T44	0	16	0	0
T52	0	35	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	68578499	1650	0	0
T1	650547	58	0	0
T2	27860	0	0	0
T3	276048	0	0	0
T4	215809	85	0	0
T5	407814	223	0	0
T6	97015	0	0	0
T7	199481	0	0	0
T8	125112	0	0	0
T13	0	49	0	0
T14	210715	0	0	0
T15	119198	0	0	0
T18	0	8	0	0
T22	0	14	0	0
T29	0	302	0	0
T30	0	11	0	0
T44	0	45	0	0
T52	0	67	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	68578499	1728	0	0
T1	650547	26	0	0
T2	27860	0	0	0
T3	276048	0	0	0
T4	215809	102	0	0
T5	407814	184	0	0
T6	97015	0	0	0
T7	199481	0	0	0
T8	125112	0	0	0
T13	0	86	0	0
T14	210715	0	0	0
T15	119198	0	0	0
T18	0	11	0	0
T20	0	1	0	0
T22	0	36	0	0
T29	0	323	0	0
T30	0	3	0	0
T44	0	29	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	68578499	1529	0	0
T1	650547	44	0	0
T2	27860	0	0	0
T3	276048	0	0	0
T4	215809	66	0	0
T5	407814	129	0	0
T6	97015	0	0	0
T7	199481	0	0	0
T8	125112	0	0	0
T13	0	56	0	0
T14	210715	0	0	0
T15	119198	0	0	0
T18	0	7	0	0
T22	0	37	0	0
T29	0	277	0	0
T30	0	27	0	0
T44	0	8	0	0
T52	0	67	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	68578499	1560	0	0
T1	650547	38	0	0
T2	27860	0	0	0
T3	276048	0	0	0
T4	215809	77	0	0
T5	407814	126	0	0
T6	97015	0	0	0
T7	199481	0	0	0
T8	125112	0	0	0
T13	0	85	0	0
T14	210715	0	0	0
T15	119198	0	0	0
T18	0	8	0	0
T20	0	7	0	0
T22	0	17	0	0
T29	0	310	0	0
T44	0	31	0	0
T52	0	82	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	68578499	1056	0	0
T1	650547	48	0	0
T2	27860	0	0	0
T3	276048	0	0	0
T4	215809	30	0	0
T5	407814	72	0	0
T6	97015	0	0	0
T7	199481	0	0	0
T8	125112	0	0	0
T13	0	69	0	0
T14	210715	0	0	0
T15	119198	0	0	0
T18	0	1	0	0
T20	0	10	0	0
T22	0	22	0	0
T29	0	267	0	0
T30	0	4	0	0
T44	0	23	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	68578499	1079	0	0
T1	650547	31	0	0
T2	27860	0	0	0
T3	276048	0	0	0
T4	215809	38	0	0
T5	407814	75	0	0
T6	97015	0	0	0
T7	199481	0	0	0
T8	125112	0	0	0
T13	0	79	0	0
T14	210715	0	0	0
T15	119198	0	0	0
T18	0	8	0	0
T20	0	16	0	0
T22	0	20	0	0
T29	0	252	0	0
T30	0	7	0	0
T44	0	34	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	68578499	977	0	0
T1	650547	24	0	0
T2	27860	0	0	0
T3	276048	0	0	0
T4	215809	26	0	0
T5	407814	77	0	0
T6	97015	0	0	0
T7	199481	0	0	0
T8	125112	0	0	0
T13	0	76	0	0
T14	210715	0	0	0
T15	119198	0	0	0
T22	0	12	0	0
T29	0	295	0	0
T30	0	6	0	0
T36	0	88	0	0
T44	0	9	0	0
T52	0	26	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	68578499	1011	0	0
T1	650547	14	0	0
T2	27860	0	0	0
T3	276048	0	0	0
T4	215809	42	0	0
T5	407814	79	0	0
T6	97015	0	0	0
T7	199481	0	0	0
T8	125112	0	0	0
T13	0	74	0	0
T14	210715	0	0	0
T15	119198	0	0	0
T20	0	18	0	0
T22	0	12	0	0
T29	0	224	0	0
T36	0	82	0	0
T44	0	27	0	0
T52	0	35	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	68578499	1897	0	0
T1	650547	56	0	0
T2	27860	0	0	0
T3	276048	0	0	0
T4	215809	168	0	0
T5	407814	176	0	0
T6	97015	0	0	0
T7	199481	0	0	0
T8	125112	0	0	0
T13	0	47	0	0
T14	210715	0	0	0
T15	119198	0	0	0
T18	0	13	0	0
T20	0	17	0	0
T22	0	59	0	0
T29	0	312	0	0
T30	0	11	0	0
T44	0	5	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	68578499	1927	0	0
T1	650547	54	0	0
T2	27860	0	0	0
T3	276048	0	0	0
T4	215809	149	0	0
T5	407814	225	0	0
T6	97015	0	0	0
T7	199481	0	0	0
T8	125112	0	0	0
T13	0	82	0	0
T14	210715	0	0	0
T15	119198	0	0	0
T18	0	11	0	0
T20	0	7	0	0
T22	0	55	0	0
T29	0	254	0	0
T30	0	15	0	0
T44	0	7	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	68578499	1668	0	0
T1	650547	71	0	0
T2	27860	0	0	0
T3	276048	0	0	0
T4	215809	85	0	0
T5	407814	183	0	0
T6	97015	0	0	0
T7	199481	0	0	0
T8	125112	0	0	0
T13	0	78	0	0
T14	210715	0	0	0
T15	119198	0	0	0
T18	0	6	0	0
T20	0	13	0	0
T22	0	17	0	0
T29	0	291	0	0
T30	0	1	0	0
T44	0	20	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	68578499	1609	0	0
T1	650547	19	0	0
T2	27860	0	0	0
T3	276048	0	0	0
T4	215809	145	0	0
T5	407814	198	0	0
T6	97015	0	0	0
T7	199481	0	0	0
T8	125112	0	0	0
T13	0	71	0	0
T14	210715	0	0	0
T15	119198	0	0	0
T18	0	1	0	0
T22	0	43	0	0
T29	0	284	0	0
T30	0	19	0	0
T44	0	12	0	0
T52	0	53	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	68578499	1892	0	0
T1	650547	22	0	0
T2	27860	0	0	0
T3	276048	0	0	0
T4	215809	128	0	0
T5	407814	181	0	0
T6	97015	0	0	0
T7	199481	0	0	0
T8	125112	0	0	0
T13	0	65	0	0
T14	210715	0	0	0
T15	119198	0	0	0
T18	0	1	0	0
T20	0	11	0	0
T22	0	49	0	0
T29	0	263	0	0
T30	0	5	0	0
T44	0	28	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	68578499	1640	0	0
T1	650547	17	0	0
T2	27860	0	0	0
T3	276048	0	0	0
T4	215809	79	0	0
T5	407814	205	0	0
T6	97015	0	0	0
T7	199481	0	0	0
T8	125112	0	0	0
T13	0	60	0	0
T14	210715	0	0	0
T15	119198	0	0	0
T18	0	4	0	0
T20	0	8	0	0
T22	0	33	0	0
T29	0	300	0	0
T30	0	3	0	0
T44	0	8	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	68578499	1717	0	0
T1	650547	31	0	0
T2	27860	0	0	0
T3	276048	0	0	0
T4	215809	116	0	0
T5	407814	218	0	0
T6	97015	0	0	0
T7	199481	0	0	0
T8	125112	0	0	0
T13	0	59	0	0
T14	210715	0	0	0
T15	119198	0	0	0
T22	0	24	0	0
T29	0	295	0	0
T30	0	18	0	0
T36	0	89	0	0
T44	0	15	0	0
T52	0	65	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	68578499	1996	0	0
T1	650547	22	0	0
T2	27860	0	0	0
T3	276048	0	0	0
T4	215809	145	0	0
T5	407814	192	0	0
T6	97015	0	0	0
T7	199481	0	0	0
T8	125112	0	0	0
T13	0	54	0	0
T14	210715	0	0	0
T15	119198	0	0	0
T18	0	2	0	0
T22	0	30	0	0
T29	0	284	0	0
T30	0	25	0	0
T44	0	54	0	0
T52	0	113	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	68578499	989	0	0
T1	650547	34	0	0
T2	27860	0	0	0
T3	276048	0	0	0
T4	215809	45	0	0
T5	407814	66	0	0
T6	97015	0	0	0
T7	199481	0	0	0
T8	125112	0	0	0
T13	0	58	0	0
T14	210715	0	0	0
T15	119198	0	0	0
T20	0	7	0	0
T22	0	16	0	0
T29	0	294	0	0
T30	0	7	0	0
T44	0	6	0	0
T52	0	38	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	68578499	1703	0	0
T1	650547	62	0	0
T2	27860	0	0	0
T3	276048	0	0	0
T4	215809	37	0	0
T5	407814	88	0	0
T6	97015	0	0	0
T7	199481	0	0	0
T8	125112	0	0	0
T14	210715	0	0	0
T15	119198	0	0	0
T18	0	23	0	0
T20	0	10	0	0
T22	0	10	0	0
T29	0	340	0	0
T30	0	7	0	0
T39	0	8	0	0
T44	0	11	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	68578499	3120	0	0
T1	650547	59	0	0
T2	27860	0	0	0
T3	276048	0	0	0
T4	215809	190	0	0
T5	407814	409	0	0
T6	97015	0	0	0
T7	199481	0	0	0
T8	125112	0	0	0
T13	0	89	0	0
T14	210715	0	0	0
T15	119198	0	0	0
T20	0	9	0	0
T22	0	47	0	0
T29	0	294	0	0
T30	0	1	0	0
T44	0	30	0	0
T52	0	159	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	68578499	1057	0	0
T1	650547	27	0	0
T2	27860	0	0	0
T3	276048	0	0	0
T4	215809	29	0	0
T5	407814	76	0	0
T6	97015	0	0	0
T7	199481	0	0	0
T8	125112	0	0	0
T13	0	87	0	0
T14	210715	0	0	0
T15	119198	0	0	0
T18	0	31	0	0
T22	0	22	0	0
T29	0	287	0	0
T30	0	1	0	0
T44	0	9	0	0
T52	0	37	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	68578499	3023	0	0
T1	650547	36	0	0
T2	27860	0	0	0
T3	276048	0	0	0
T4	215809	247	0	0
T5	407814	504	0	0
T6	97015	0	0	0
T7	199481	0	0	0
T8	125112	0	0	0
T13	0	78	0	0
T14	210715	0	0	0
T15	119198	0	0	0
T18	0	8	0	0
T20	0	5	0	0
T22	0	5	0	0
T29	0	291	0	0
T30	0	34	0	0
T44	0	43	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	68578499	3875	0	0
T1	650547	84	0	0
T2	27860	0	0	0
T3	276048	0	0	0
T4	215809	267	0	0
T5	407814	558	0	0
T6	97015	0	0	0
T7	199481	0	0	0
T8	125112	0	0	0
T13	0	67	0	0
T14	210715	0	0	0
T15	119198	0	0	0
T20	0	2	0	0
T22	0	73	0	0
T29	0	234	0	0
T30	0	71	0	0
T44	0	13	0	0
T52	0	452	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	68578499	2414	0	0
T1	650547	25	0	0
T2	27860	0	0	0
T3	276048	0	0	0
T4	215809	179	0	0
T5	407814	367	0	0
T6	97015	0	0	0
T7	199481	0	0	0
T8	125112	0	0	0
T13	0	61	0	0
T14	210715	0	0	0
T15	119198	0	0	0
T18	0	4	0	0
T20	0	8	0	0
T22	0	48	0	0
T29	0	276	0	0
T30	0	3	0	0
T44	0	7	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	68578499	2490	0	0
T1	650547	36	0	0
T2	27860	0	0	0
T3	276048	0	0	0
T4	215809	195	0	0
T5	407814	342	0	0
T6	97015	0	0	0
T7	199481	0	0	0
T8	125112	0	0	0
T13	0	67	0	0
T14	210715	0	0	0
T15	119198	0	0	0
T18	0	11	0	0
T20	0	6	0	0
T22	0	72	0	0
T29	0	305	0	0
T30	0	27	0	0
T44	0	20	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	68578499	1452	0	0
T1	650547	55	0	0
T2	27860	0	0	0
T3	276048	0	0	0
T4	215809	44	0	0
T5	407814	90	0	0
T6	97015	0	0	0
T7	199481	0	0	0
T8	125112	0	0	0
T13	0	198	0	0
T14	210715	0	0	0
T15	119198	0	0	0
T18	0	9	0	0
T22	0	15	0	0
T29	0	341	0	0
T30	0	7	0	0
T44	0	31	0	0
T52	0	61	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	68578499	1036	0	0
T1	650547	78	0	0
T2	27860	0	0	0
T3	276048	0	0	0
T4	215809	38	0	0
T5	407814	55	0	0
T6	97015	0	0	0
T7	199481	0	0	0
T8	125112	0	0	0
T13	0	83	0	0
T14	210715	0	0	0
T15	119198	0	0	0
T18	0	4	0	0
T20	0	30	0	0
T22	0	24	0	0
T29	0	268	0	0
T44	0	35	0	0
T52	0	18	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	68578499	996	0	0
T1	650547	27	0	0
T2	27860	0	0	0
T3	276048	0	0	0
T4	215809	24	0	0
T5	407814	87	0	0
T6	97015	0	0	0
T7	199481	0	0	0
T8	125112	0	0	0
T13	0	69	0	0
T14	210715	0	0	0
T15	119198	0	0	0
T18	0	3	0	0
T20	0	7	0	0
T22	0	12	0	0
T29	0	258	0	0
T30	0	1	0	0
T44	0	20	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	68578499	1053	0	0
T1	650547	60	0	0
T2	27860	0	0	0
T3	276048	0	0	0
T4	215809	25	0	0
T5	407814	72	0	0
T6	97015	0	0	0
T7	199481	0	0	0
T8	125112	0	0	0
T13	0	85	0	0
T14	210715	0	0	0
T15	119198	0	0	0
T18	0	15	0	0
T20	0	1	0	0
T22	0	20	0	0
T29	0	304	0	0
T30	0	4	0	0
T44	0	6	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	68578499	1051	0	0
T1	650547	15	0	0
T2	27860	0	0	0
T3	276048	0	0	0
T4	215809	41	0	0
T5	407814	52	0	0
T6	97015	0	0	0
T7	199481	0	0	0
T8	125112	0	0	0
T13	0	51	0	0
T14	210715	0	0	0
T15	119198	0	0	0
T18	0	30	0	0
T22	0	19	0	0
T29	0	294	0	0
T30	0	7	0	0
T44	0	15	0	0
T52	0	37	0	0