Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_intr_status_obj::sysrst_ctrl_combo_intr_status_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_intr_status_obj::sysrst_ctrl_combo_intr_status_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
0.00	0.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_intr_status_cg	0.00	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_intr_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
0.00	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_intr_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	20	0	0.00
Crosses	384	384	0	0.00

Variables for Group Instance sysrst_ctrl_combo_intr_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	2	0	0.00	100	1	1	2
cp_combo0_h2l	2	2	0	0.00	100	1	1	2
cp_combo1_h2l	2	2	0	0.00	100	1	1	2
cp_combo2_h2l	2	2	0	0.00	100	1	1	2
cp_combo3_h2l	2	2	0	0.00	100	1	1	2
cp_interrupt	2	2	0	0.00	100	1	1	2
cp_key0_in_sel	2	2	0	0.00	100	1	1	2
cp_key1_in_sel	2	2	0	0.00	100	1	1	2
cp_key2_in_sel	2	2	0	0.00	100	1	1	2
cp_pwrb_in_sel	2	2	0	0.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_intr_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_combo0	96	96	0	0.00	100	1	1	0
cross_combo1	96	96	0	0.00	100	1	1	0
cross_combo2	96	96	0	0.00	100	1	1	0
cross_combo3	96	96	0	0.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for cp_ac_present_sel

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable cp_combo0_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for cp_combo0_h2l

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable cp_combo1_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for cp_combo1_h2l

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable cp_combo2_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for cp_combo2_h2l

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable cp_combo3_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for cp_combo3_h2l

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for cp_interrupt

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for cp_key0_in_sel

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for cp_key1_in_sel

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for cp_key2_in_sel

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for cp_pwrb_in_sel

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Cross cross_combo0

Samples crossed: cp_combo0_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	96	96	0	0.00	96
Automatically Generated Cross Bins	96	96	0	0.00	96
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_combo0

Element holes

cp_combo0_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	*	*	*	*	*	*	--	--	64
[auto[1]]	*	*	*	*	*	[auto[1]]	--	--	32

User Defined Cross Bins for cross_combo0

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded

---

Summary for Cross cross_combo1

Samples crossed: cp_combo1_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	96	96	0	0.00	96
Automatically Generated Cross Bins	96	96	0	0.00	96
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_combo1

Element holes

cp_combo1_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	*	*	*	*	*	*	--	--	64
[auto[1]]	*	*	*	*	*	[auto[1]]	--	--	32

User Defined Cross Bins for cross_combo1

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded

---

Summary for Cross cross_combo2

Samples crossed: cp_combo2_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	96	96	0	0.00	96
Automatically Generated Cross Bins	96	96	0	0.00	96
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_combo2

Element holes

cp_combo2_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	*	*	*	*	*	*	--	--	64
[auto[1]]	*	*	*	*	*	[auto[1]]	--	--	32

User Defined Cross Bins for cross_combo2

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded

---

Summary for Cross cross_combo3

Samples crossed: cp_combo3_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	96	96	0	0.00	96
Automatically Generated Cross Bins	96	96	0	0.00	96
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_combo3

Element holes

cp_combo3_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	*	*	*	*	*	*	--	--	64
[auto[1]]	*	*	*	*	*	[auto[1]]	--	--	32

User Defined Cross Bins for cross_combo3

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded