Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	56153	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

49111

1

T1

787

T2

65

T3

451

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	64152	1			T1	367		T2	124		T3	198
values[0x0]	20160	1			T1	218		T2	18		T3	128
values[0x1]	20952	1			T1	204		T2	26		T3	127

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	41921	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

63343

1

T1

788

T2

93

T3

451

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	336	1			T1	1		T14	17		T5	6
valid_sources[0x01]	366	1			T4	3		T14	4		T5	8
valid_sources[0x02]	427	1			T4	3		T14	2		T15	10
valid_sources[0x03]	356	1			T1	14		T4	15		T14	1
valid_sources[0x04]	338	1			T5	8		T11	1		T16	4
valid_sources[0x05]	865	1			T4	13		T14	1		T15	1
valid_sources[0x06]	392	1			T2	8		T4	13		T14	3
valid_sources[0x07]	713	1			T1	3		T4	1		T14	2
valid_sources[0x08]	344	1			T1	9		T2	4		T4	1
valid_sources[0x09]	316	1			T4	2		T5	9		T11	1
valid_sources[0x0a]	455	1			T1	21		T4	19		T14	4
valid_sources[0x0b]	377	1			T2	17		T4	34		T5	4
valid_sources[0x0c]	415	1			T4	23		T5	10		T11	2
valid_sources[0x0d]	412	1			T2	3		T4	1		T14	3
valid_sources[0x0e]	494	1			T1	20		T4	7		T14	1
valid_sources[0x0f]	295	1			T3	8		T14	1		T7	7
valid_sources[0x10]	262	1			T14	1		T5	11		T11	2
valid_sources[0x11]	384	1			T1	6		T14	1		T5	5
valid_sources[0x12]	651	1			T4	5		T5	10		T9	2
valid_sources[0x13]	424	1			T1	30		T4	2		T5	12
valid_sources[0x14]	836	1			T4	14		T14	2		T5	10
valid_sources[0x15]	496	1			T14	1		T5	13		T11	5
valid_sources[0x16]	497	1			T4	6		T5	7		T11	1
valid_sources[0x17]	533	1			T4	9		T14	4		T7	32
valid_sources[0x18]	476	1			T4	2		T14	3		T5	6
valid_sources[0x19]	329	1			T4	10		T14	1		T7	10
valid_sources[0x1a]	417	1			T1	1		T4	1		T14	6
valid_sources[0x1b]	380	1			T1	3		T14	8		T5	5
valid_sources[0x1c]	443	1			T1	8		T4	10		T15	27
valid_sources[0x1d]	415	1			T4	5		T14	7		T7	2
valid_sources[0x1e]	342	1			T5	12		T9	1		T11	4
valid_sources[0x1f]	352	1			T3	32		T6	21		T5	7
valid_sources[0x20]	358	1			T1	10		T4	6		T14	1
valid_sources[0x21]	552	1			T1	7		T2	6		T3	19
valid_sources[0x22]	360	1			T4	3		T7	25		T5	7
valid_sources[0x23]	327	1			T4	5		T14	2		T5	11
valid_sources[0x24]	503	1			T14	1		T5	7		T11	2
valid_sources[0x25]	406	1			T4	9		T5	10		T11	2
valid_sources[0x26]	418	1			T1	2		T4	23		T14	4
valid_sources[0x27]	406	1			T14	1		T5	14		T16	5
valid_sources[0x28]	513	1			T4	10		T14	2		T5	13
valid_sources[0x29]	345	1			T1	2		T5	8		T11	6
valid_sources[0x2a]	583	1			T4	12		T14	7		T15	28
valid_sources[0x2b]	709	1			T5	7		T23	6		T25	14
valid_sources[0x2c]	373	1			T1	7		T3	23		T4	2
valid_sources[0x2d]	317	1			T4	8		T14	4		T5	10
valid_sources[0x2e]	828	1			T2	5		T4	3		T14	3
valid_sources[0x2f]	349	1			T4	7		T5	15		T11	3
valid_sources[0x30]	356	1			T5	12		T11	2		T16	2
valid_sources[0x31]	286	1			T1	1		T2	16		T4	13
valid_sources[0x32]	485	1			T4	10		T14	3		T5	7
valid_sources[0x33]	506	1			T1	1		T3	4		T4	8
valid_sources[0x34]	472	1			T4	4		T14	12		T5	12
valid_sources[0x35]	489	1			T4	5		T5	6		T11	3
valid_sources[0x36]	336	1			T14	3		T15	25		T5	10
valid_sources[0x37]	454	1			T2	20		T4	6		T14	2
valid_sources[0x38]	310	1			T3	5		T4	12		T5	12
valid_sources[0x39]	389	1			T4	6		T14	7		T5	13
valid_sources[0x3a]	365	1			T5	12		T11	1		T16	4
valid_sources[0x3b]	294	1			T4	2		T7	6		T5	12
valid_sources[0x3c]	327	1			T1	17		T3	27		T14	1
valid_sources[0x3d]	410	1			T1	15		T4	3		T14	5
valid_sources[0x3e]	379	1			T3	14		T4	7		T14	1
valid_sources[0x3f]	462	1			T1	14		T4	25		T14	1
valid_sources[0x40]	354	1			T4	14		T7	5		T5	11
valid_sources[0x41]	645	1			T1	9		T4	3		T5	16
valid_sources[0x42]	391	1			T15	14		T7	2		T5	14
valid_sources[0x43]	390	1			T4	8		T5	12		T11	2
valid_sources[0x44]	427	1			T1	6		T15	4		T5	9
valid_sources[0x45]	385	1			T4	7		T5	6		T11	2
valid_sources[0x46]	436	1			T2	1		T4	5		T14	2
valid_sources[0x47]	388	1			T1	10		T2	7		T4	2
valid_sources[0x48]	928	1			T3	4		T14	1		T5	6
valid_sources[0x49]	507	1			T1	2		T3	11		T4	17
valid_sources[0x4a]	339	1			T4	1		T15	16		T5	9
valid_sources[0x4b]	268	1			T14	2		T15	7		T5	8
valid_sources[0x4c]	276	1			T5	5		T9	4		T11	2
valid_sources[0x4d]	392	1			T1	12		T5	6		T11	2
valid_sources[0x4e]	363	1			T4	2		T14	6		T15	7
valid_sources[0x4f]	324	1			T1	2		T4	14		T5	19
valid_sources[0x50]	607	1			T3	1		T14	8		T5	18
valid_sources[0x51]	337	1			T4	4		T5	10		T11	7
valid_sources[0x52]	286	1			T4	1		T15	12		T5	8
valid_sources[0x53]	333	1			T1	13		T4	3		T14	2
valid_sources[0x54]	394	1			T4	4		T5	10		T11	2
valid_sources[0x55]	617	1			T1	4		T2	9		T3	7
valid_sources[0x56]	404	1			T5	9		T11	2		T16	3
valid_sources[0x57]	279	1			T1	7		T4	8		T5	9
valid_sources[0x58]	305	1			T7	13		T5	7		T11	3
valid_sources[0x59]	336	1			T3	44		T4	4		T14	3
valid_sources[0x5a]	374	1			T4	5		T14	2		T5	10
valid_sources[0x5b]	705	1			T4	35		T5	10		T9	2
valid_sources[0x5c]	431	1			T15	24		T5	13		T11	5
valid_sources[0x5d]	362	1			T1	36		T2	1		T4	3
valid_sources[0x5e]	528	1			T1	2		T14	5		T15	1
valid_sources[0x5f]	557	1			T4	12		T5	8		T11	2
valid_sources[0x60]	512	1			T14	1		T5	14		T11	5
valid_sources[0x61]	289	1			T5	13		T11	5		T16	8
valid_sources[0x62]	324	1			T5	4		T11	2		T16	3
valid_sources[0x63]	268	1			T14	2		T5	11		T11	2
valid_sources[0x64]	297	1			T4	2		T14	5		T5	11
valid_sources[0x65]	542	1			T1	3		T4	2		T14	1
valid_sources[0x66]	300	1			T14	8		T5	9		T11	1
valid_sources[0x67]	304	1			T4	6		T15	4		T5	8
valid_sources[0x68]	356	1			T4	6		T14	4		T15	2
valid_sources[0x69]	484	1			T4	7		T5	14		T11	4
valid_sources[0x6a]	380	1			T2	16		T4	9		T14	1
valid_sources[0x6b]	343	1			T1	18		T4	9		T7	7
valid_sources[0x6c]	372	1			T1	32		T7	2		T5	10
valid_sources[0x6d]	613	1			T1	4		T3	2		T14	3
valid_sources[0x6e]	358	1			T4	4		T14	7		T15	17
valid_sources[0x6f]	273	1			T5	2		T11	2		T16	1
valid_sources[0x70]	470	1			T2	6		T14	4		T5	16
valid_sources[0x71]	400	1			T14	2		T5	8		T11	2
valid_sources[0x72]	363	1			T14	10		T5	8		T11	5
valid_sources[0x73]	458	1			T4	19		T15	3		T5	10
valid_sources[0x74]	488	1			T1	7		T5	10		T11	14
valid_sources[0x75]	520	1			T4	10		T14	1		T15	7
valid_sources[0x76]	383	1			T1	14		T4	12		T15	1
valid_sources[0x77]	350	1			T3	11		T5	10		T11	2
valid_sources[0x78]	392	1			T1	32		T2	8		T15	9
valid_sources[0x79]	744	1			T1	33		T5	12		T11	3
valid_sources[0x7a]	305	1			T4	9		T15	3		T5	10
valid_sources[0x7b]	431	1			T2	1		T4	9		T14	1
valid_sources[0x7c]	394	1			T7	9		T5	4		T11	3
valid_sources[0x7d]	304	1			T4	4		T15	12		T5	4
valid_sources[0x7e]	606	1			T3	12		T4	18		T14	6
valid_sources[0x7f]	372	1			T2	2		T15	7		T5	14
valid_sources[0x80]	474	1			T4	5		T14	3		T5	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

24602

1

T1

365

T2

43

T3

196

values[0x0]

all_enables

biggest_size

13386

1

T1

218

T2

12

T3

128

values[0x1]

all_enables

biggest_size

11123

1

T1

204

T2

10

T3

127