Unified Coverage Report :: Module :: prim_subreg_arb

Module : prim_subreg_arb

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.17	87.50	92.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_intr_state.wr_en_data_arb	50.00	50.00
tb.dut.u_reg.u_pin_in_value_pwrb_in.wr_en_data_arb	50.00	50.00
tb.dut.u_reg.u_pin_in_value_key0_in.wr_en_data_arb	50.00	50.00
tb.dut.u_reg.u_pin_in_value_key1_in.wr_en_data_arb	50.00	50.00
tb.dut.u_reg.u_pin_in_value_key2_in.wr_en_data_arb	50.00	50.00
tb.dut.u_reg.u_pin_in_value_lid_open.wr_en_data_arb	50.00	50.00
tb.dut.u_reg.u_pin_in_value_ac_present.wr_en_data_arb	50.00	50.00
tb.dut.u_reg.u_pin_in_value_ec_rst_l.wr_en_data_arb	50.00	50.00
tb.dut.u_reg.u_pin_in_value_flash_wp_l.wr_en_data_arb	50.00	50.00
tb.dut.u_reg.u_ulp_status.wr_en_data_arb	80.00	100.00	60.00
tb.dut.u_reg.u_wkup_status.wr_en_data_arb	80.00	100.00	60.00
tb.dut.u_reg.u_combo_intr_status_combo0_h2l.wr_en_data_arb	80.00	100.00	60.00
tb.dut.u_reg.u_combo_intr_status_combo1_h2l.wr_en_data_arb	80.00	100.00	60.00
tb.dut.u_reg.u_combo_intr_status_combo2_h2l.wr_en_data_arb	80.00	100.00	60.00
tb.dut.u_reg.u_combo_intr_status_combo3_h2l.wr_en_data_arb	80.00	100.00	60.00
tb.dut.u_reg.u_key_intr_status_pwrb_h2l.wr_en_data_arb	80.00	100.00	60.00
tb.dut.u_reg.u_key_intr_status_key0_in_h2l.wr_en_data_arb	80.00	100.00	60.00
tb.dut.u_reg.u_key_intr_status_key1_in_h2l.wr_en_data_arb	80.00	100.00	60.00
tb.dut.u_reg.u_key_intr_status_key2_in_h2l.wr_en_data_arb	80.00	100.00	60.00
tb.dut.u_reg.u_key_intr_status_ac_present_h2l.wr_en_data_arb	80.00	100.00	60.00
tb.dut.u_reg.u_key_intr_status_ec_rst_l_h2l.wr_en_data_arb	80.00	100.00	60.00
tb.dut.u_reg.u_key_intr_status_flash_wp_l_h2l.wr_en_data_arb	80.00	100.00	60.00
tb.dut.u_reg.u_key_intr_status_pwrb_l2h.wr_en_data_arb	80.00	100.00	60.00
tb.dut.u_reg.u_key_intr_status_key0_in_l2h.wr_en_data_arb	80.00	100.00	60.00
tb.dut.u_reg.u_key_intr_status_key1_in_l2h.wr_en_data_arb	80.00	100.00	60.00
tb.dut.u_reg.u_key_intr_status_key2_in_l2h.wr_en_data_arb	80.00	100.00	60.00
tb.dut.u_reg.u_key_intr_status_ac_present_l2h.wr_en_data_arb	80.00	100.00	60.00
tb.dut.u_reg.u_key_intr_status_ec_rst_l_l2h.wr_en_data_arb	80.00	100.00	60.00
tb.dut.u_reg.u_key_intr_status_flash_wp_l_l2h.wr_en_data_arb	80.00	100.00	60.00
tb.dut.u_reg.u_intr_enable.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_regwen.wr_en_data_arb	100.00	100.00	100.00
tb.dut.u_reg.u_ec_rst_ctl.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_ulp_ac_debounce_ctl.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_ulp_lid_debounce_ctl.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_ulp_ctl.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_key_invert_ctl_key0_in.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_key_invert_ctl_key0_out.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_key_invert_ctl_key1_in.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_key_invert_ctl_key1_out.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_key_invert_ctl_key2_in.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_key_invert_ctl_key2_out.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_key_invert_ctl_pwrb_in.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_key_invert_ctl_pwrb_out.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_key_invert_ctl_ac_present.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_key_invert_ctl_bat_disable.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_key_invert_ctl_lid_open.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_key_invert_ctl_z3_wakeup.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_pin_allowed_ctl_bat_disable_0.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_pin_allowed_ctl_ec_rst_l_0.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_pin_allowed_ctl_pwrb_out_0.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_pin_allowed_ctl_key0_out_0.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_pin_allowed_ctl_key1_out_0.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_pin_allowed_ctl_key2_out_0.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_pin_allowed_ctl_z3_wakeup_0.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_pin_allowed_ctl_flash_wp_l_0.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_pin_allowed_ctl_bat_disable_1.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_pin_allowed_ctl_ec_rst_l_1.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_pin_allowed_ctl_pwrb_out_1.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_pin_allowed_ctl_key0_out_1.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_pin_allowed_ctl_key1_out_1.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_pin_allowed_ctl_key2_out_1.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_pin_allowed_ctl_z3_wakeup_1.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_pin_allowed_ctl_flash_wp_l_1.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_pin_out_ctl_bat_disable.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_pin_out_ctl_ec_rst_l.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_pin_out_ctl_pwrb_out.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_pin_out_ctl_key0_out.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_pin_out_ctl_key1_out.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_pin_out_ctl_key2_out.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_pin_out_ctl_z3_wakeup.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_pin_out_ctl_flash_wp_l.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_pin_out_value_bat_disable.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_pin_out_value_ec_rst_l.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_pin_out_value_pwrb_out.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_pin_out_value_key0_out.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_pin_out_value_key1_out.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_pin_out_value_key2_out.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_pin_out_value_z3_wakeup.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_pin_out_value_flash_wp_l.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_key_intr_ctl_pwrb_in_h2l.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_key_intr_ctl_key0_in_h2l.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_key_intr_ctl_key1_in_h2l.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_key_intr_ctl_key2_in_h2l.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_key_intr_ctl_ac_present_h2l.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_key_intr_ctl_ec_rst_l_h2l.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_key_intr_ctl_flash_wp_l_h2l.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_key_intr_ctl_pwrb_in_l2h.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_key_intr_ctl_key0_in_l2h.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_key_intr_ctl_key1_in_l2h.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_key_intr_ctl_key2_in_l2h.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_key_intr_ctl_ac_present_l2h.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_key_intr_ctl_ec_rst_l_l2h.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_key_intr_ctl_flash_wp_l_l2h.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_key_intr_debounce_ctl.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_auto_block_debounce_ctl_debounce_timer.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_auto_block_debounce_ctl_auto_block_enable.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_auto_block_out_ctl_key0_out_sel.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_auto_block_out_ctl_key1_out_sel.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_auto_block_out_ctl_key2_out_sel.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_auto_block_out_ctl_key0_out_value.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_auto_block_out_ctl_key1_out_value.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_auto_block_out_ctl_key2_out_value.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_pre_sel_ctl_0_key0_in_sel_0.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_pre_sel_ctl_0_key1_in_sel_0.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_pre_sel_ctl_0_key2_in_sel_0.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_pre_sel_ctl_0_pwrb_in_sel_0.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_pre_sel_ctl_0_ac_present_sel_0.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_pre_sel_ctl_1_key0_in_sel_1.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_pre_sel_ctl_1_key1_in_sel_1.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_pre_sel_ctl_1_key2_in_sel_1.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_pre_sel_ctl_1_pwrb_in_sel_1.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_pre_sel_ctl_1_ac_present_sel_1.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_pre_sel_ctl_2_key0_in_sel_2.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_pre_sel_ctl_2_key1_in_sel_2.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_pre_sel_ctl_2_key2_in_sel_2.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_pre_sel_ctl_2_pwrb_in_sel_2.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_pre_sel_ctl_2_ac_present_sel_2.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_pre_sel_ctl_3_key0_in_sel_3.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_pre_sel_ctl_3_key1_in_sel_3.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_pre_sel_ctl_3_key2_in_sel_3.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_pre_sel_ctl_3_pwrb_in_sel_3.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_pre_sel_ctl_3_ac_present_sel_3.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_pre_det_ctl_0.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_pre_det_ctl_1.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_pre_det_ctl_2.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_pre_det_ctl_3.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_sel_ctl_0_key0_in_sel_0.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_sel_ctl_0_key1_in_sel_0.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_sel_ctl_0_key2_in_sel_0.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_sel_ctl_0_pwrb_in_sel_0.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_sel_ctl_0_ac_present_sel_0.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_sel_ctl_1_key0_in_sel_1.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_sel_ctl_1_key1_in_sel_1.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_sel_ctl_1_key2_in_sel_1.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_sel_ctl_1_pwrb_in_sel_1.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_sel_ctl_1_ac_present_sel_1.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_sel_ctl_2_key0_in_sel_2.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_sel_ctl_2_key1_in_sel_2.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_sel_ctl_2_key2_in_sel_2.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_sel_ctl_2_pwrb_in_sel_2.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_sel_ctl_2_ac_present_sel_2.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_sel_ctl_3_key0_in_sel_3.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_sel_ctl_3_key1_in_sel_3.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_sel_ctl_3_key2_in_sel_3.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_sel_ctl_3_pwrb_in_sel_3.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_sel_ctl_3_ac_present_sel_3.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_det_ctl_0.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_det_ctl_1.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_det_ctl_2.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_det_ctl_3.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_out_ctl_0_bat_disable_0.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_out_ctl_0_interrupt_0.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_out_ctl_0_ec_rst_0.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_out_ctl_0_rst_req_0.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_out_ctl_1_bat_disable_1.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_out_ctl_1_interrupt_1.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_out_ctl_1_ec_rst_1.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_out_ctl_1_rst_req_1.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_out_ctl_2_bat_disable_2.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_out_ctl_2_interrupt_2.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_out_ctl_2_ec_rst_2.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_out_ctl_2_rst_req_2.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_out_ctl_3_bat_disable_3.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_out_ctl_3_interrupt_3.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_out_ctl_3_ec_rst_3.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_out_ctl_3_rst_req_3.wr_en_data_arb	100.00	100.00	100.00			100.00

Line Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=1,Mubi=0 )
Line Coverage for Module self-instances :

SCORE	LINE
50.00	50.00

tb.dut.u_reg.u_intr_state.wr_en_data_arb

SCORE	LINE
50.00	50.00

tb.dut.u_reg.u_pin_in_value_pwrb_in.wr_en_data_arb

SCORE	LINE
50.00	50.00

tb.dut.u_reg.u_pin_in_value_key0_in.wr_en_data_arb

SCORE	LINE
50.00	50.00

tb.dut.u_reg.u_pin_in_value_key1_in.wr_en_data_arb

SCORE	LINE
50.00	50.00

tb.dut.u_reg.u_pin_in_value_key2_in.wr_en_data_arb

SCORE	LINE
50.00	50.00

tb.dut.u_reg.u_pin_in_value_lid_open.wr_en_data_arb

SCORE	LINE
50.00	50.00

tb.dut.u_reg.u_pin_in_value_ac_present.wr_en_data_arb

SCORE	LINE
50.00	50.00

tb.dut.u_reg.u_pin_in_value_ec_rst_l.wr_en_data_arb

SCORE	LINE
50.00	50.00

tb.dut.u_reg.u_pin_in_value_flash_wp_l.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	1	50.00
CONT_ASSIGN	43	1	0	0.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	51	0	0
CONT_ASSIGN	52	0	0
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
43	0	1
44	1	1
51		unreachable
52		unreachable
53		unreachable

---

Line Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=0,Mubi=0 + DW=16,SwAccess=0,Mubi=0 + DW=32,SwAccess=0,Mubi=0 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_intr_enable.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_ec_rst_ctl.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_ulp_ac_debounce_ctl.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_ulp_lid_debounce_ctl.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_ulp_pwrb_debounce_ctl.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_ulp_ctl.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_key_invert_ctl_key0_in.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_key_invert_ctl_key0_out.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_key_invert_ctl_key1_in.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_key_invert_ctl_key1_out.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_key_invert_ctl_key2_in.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_key_invert_ctl_key2_out.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_key_invert_ctl_pwrb_in.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_key_invert_ctl_pwrb_out.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_key_invert_ctl_ac_present.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_key_invert_ctl_bat_disable.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_key_invert_ctl_lid_open.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_key_invert_ctl_z3_wakeup.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_pin_allowed_ctl_bat_disable_0.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_pin_allowed_ctl_ec_rst_l_0.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_pin_allowed_ctl_pwrb_out_0.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_pin_allowed_ctl_key0_out_0.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_pin_allowed_ctl_key1_out_0.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_pin_allowed_ctl_key2_out_0.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_pin_allowed_ctl_z3_wakeup_0.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_pin_allowed_ctl_flash_wp_l_0.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_pin_allowed_ctl_bat_disable_1.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_pin_allowed_ctl_ec_rst_l_1.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_pin_allowed_ctl_pwrb_out_1.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_pin_allowed_ctl_key0_out_1.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_pin_allowed_ctl_key1_out_1.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_pin_allowed_ctl_key2_out_1.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_pin_allowed_ctl_z3_wakeup_1.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_pin_allowed_ctl_flash_wp_l_1.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_pin_out_ctl_bat_disable.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_pin_out_ctl_ec_rst_l.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_pin_out_ctl_pwrb_out.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_pin_out_ctl_key0_out.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_pin_out_ctl_key1_out.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_pin_out_ctl_key2_out.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_pin_out_ctl_z3_wakeup.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_pin_out_ctl_flash_wp_l.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_pin_out_value_bat_disable.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_pin_out_value_ec_rst_l.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_pin_out_value_pwrb_out.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_pin_out_value_key0_out.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_pin_out_value_key1_out.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_pin_out_value_key2_out.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_pin_out_value_z3_wakeup.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_pin_out_value_flash_wp_l.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_key_intr_ctl_pwrb_in_h2l.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_key_intr_ctl_key0_in_h2l.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_key_intr_ctl_key1_in_h2l.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_key_intr_ctl_key2_in_h2l.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_key_intr_ctl_ac_present_h2l.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_key_intr_ctl_ec_rst_l_h2l.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_key_intr_ctl_flash_wp_l_h2l.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_key_intr_ctl_pwrb_in_l2h.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_key_intr_ctl_key0_in_l2h.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_key_intr_ctl_key1_in_l2h.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_key_intr_ctl_key2_in_l2h.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_key_intr_ctl_ac_present_l2h.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_key_intr_ctl_ec_rst_l_l2h.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_key_intr_ctl_flash_wp_l_l2h.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_key_intr_debounce_ctl.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_auto_block_debounce_ctl_debounce_timer.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_auto_block_debounce_ctl_auto_block_enable.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_auto_block_out_ctl_key0_out_sel.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_auto_block_out_ctl_key1_out_sel.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_auto_block_out_ctl_key2_out_sel.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_auto_block_out_ctl_key0_out_value.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_auto_block_out_ctl_key1_out_value.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_auto_block_out_ctl_key2_out_value.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_0_key0_in_sel_0.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_0_key1_in_sel_0.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_0_key2_in_sel_0.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_0_pwrb_in_sel_0.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_0_ac_present_sel_0.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_1_key0_in_sel_1.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_1_key1_in_sel_1.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_1_key2_in_sel_1.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_1_pwrb_in_sel_1.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_1_ac_present_sel_1.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_2_key0_in_sel_2.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_2_key1_in_sel_2.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_2_key2_in_sel_2.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_2_pwrb_in_sel_2.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_2_ac_present_sel_2.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_3_key0_in_sel_3.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_3_key1_in_sel_3.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_3_key2_in_sel_3.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_3_pwrb_in_sel_3.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_3_ac_present_sel_3.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_pre_det_ctl_0.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_pre_det_ctl_1.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_pre_det_ctl_2.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_pre_det_ctl_3.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_0_key0_in_sel_0.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_0_key1_in_sel_0.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_0_key2_in_sel_0.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_0_pwrb_in_sel_0.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_0_ac_present_sel_0.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_1_key0_in_sel_1.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_1_key1_in_sel_1.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_1_key2_in_sel_1.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_1_pwrb_in_sel_1.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_1_ac_present_sel_1.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_2_key0_in_sel_2.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_2_key1_in_sel_2.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_2_key2_in_sel_2.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_2_pwrb_in_sel_2.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_2_ac_present_sel_2.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_3_key0_in_sel_3.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_3_key1_in_sel_3.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_3_key2_in_sel_3.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_3_pwrb_in_sel_3.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_3_ac_present_sel_3.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_det_ctl_0.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_det_ctl_1.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_det_ctl_2.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_det_ctl_3.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_out_ctl_0_bat_disable_0.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_out_ctl_0_interrupt_0.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_out_ctl_0_ec_rst_0.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_out_ctl_0_rst_req_0.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_out_ctl_1_bat_disable_1.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_out_ctl_1_interrupt_1.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_out_ctl_1_ec_rst_1.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_out_ctl_1_rst_req_1.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_out_ctl_2_bat_disable_2.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_out_ctl_2_interrupt_2.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_out_ctl_2_ec_rst_2.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_out_ctl_2_rst_req_2.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_out_ctl_3_bat_disable_3.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_out_ctl_3_interrupt_3.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_out_ctl_3_ec_rst_3.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_out_ctl_3_rst_req_3.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	33	1	1	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	39	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1
34	1	1
39		unreachable

---

Line Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=5,Mubi=0 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_regwen.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	135	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
113	1	1
135	1	1

---

Line Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=3,Mubi=0 )
Line Coverage for Module self-instances :

SCORE	LINE
80.00	100.00

tb.dut.u_reg.u_ulp_status.wr_en_data_arb

SCORE	LINE
80.00	100.00

tb.dut.u_reg.u_wkup_status.wr_en_data_arb

SCORE	LINE
80.00	100.00

tb.dut.u_reg.u_combo_intr_status_combo0_h2l.wr_en_data_arb

SCORE	LINE
80.00	100.00

tb.dut.u_reg.u_combo_intr_status_combo1_h2l.wr_en_data_arb

SCORE	LINE
80.00	100.00

tb.dut.u_reg.u_combo_intr_status_combo2_h2l.wr_en_data_arb

SCORE	LINE
80.00	100.00

tb.dut.u_reg.u_combo_intr_status_combo3_h2l.wr_en_data_arb

SCORE	LINE
80.00	100.00

tb.dut.u_reg.u_key_intr_status_pwrb_h2l.wr_en_data_arb

SCORE	LINE
80.00	100.00

tb.dut.u_reg.u_key_intr_status_key0_in_h2l.wr_en_data_arb

SCORE	LINE
80.00	100.00

tb.dut.u_reg.u_key_intr_status_key1_in_h2l.wr_en_data_arb

SCORE	LINE
80.00	100.00

tb.dut.u_reg.u_key_intr_status_key2_in_h2l.wr_en_data_arb

SCORE	LINE
80.00	100.00

tb.dut.u_reg.u_key_intr_status_ac_present_h2l.wr_en_data_arb

SCORE	LINE
80.00	100.00

tb.dut.u_reg.u_key_intr_status_ec_rst_l_h2l.wr_en_data_arb

SCORE	LINE
80.00	100.00

tb.dut.u_reg.u_key_intr_status_flash_wp_l_h2l.wr_en_data_arb

SCORE	LINE
80.00	100.00

tb.dut.u_reg.u_key_intr_status_pwrb_l2h.wr_en_data_arb

SCORE	LINE
80.00	100.00

tb.dut.u_reg.u_key_intr_status_key0_in_l2h.wr_en_data_arb

SCORE	LINE
80.00	100.00

tb.dut.u_reg.u_key_intr_status_key1_in_l2h.wr_en_data_arb

SCORE	LINE
80.00	100.00

tb.dut.u_reg.u_key_intr_status_key2_in_l2h.wr_en_data_arb

SCORE	LINE
80.00	100.00

tb.dut.u_reg.u_key_intr_status_ac_present_l2h.wr_en_data_arb

SCORE	LINE
80.00	100.00

tb.dut.u_reg.u_key_intr_status_ec_rst_l_l2h.wr_en_data_arb

SCORE	LINE
80.00	100.00

tb.dut.u_reg.u_key_intr_status_flash_wp_l_l2h.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	110	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
88	1	1
110	1	1

---

Cond Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=3,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
80.00	60.00

tb.dut.u_reg.u_ulp_status.wr_en_data_arb

SCORE	COND
80.00	60.00

tb.dut.u_reg.u_wkup_status.wr_en_data_arb

SCORE	COND
80.00	60.00

tb.dut.u_reg.u_combo_intr_status_combo0_h2l.wr_en_data_arb

SCORE	COND
80.00	60.00

tb.dut.u_reg.u_combo_intr_status_combo1_h2l.wr_en_data_arb

SCORE	COND
80.00	60.00

tb.dut.u_reg.u_combo_intr_status_combo2_h2l.wr_en_data_arb

SCORE	COND
80.00	60.00

tb.dut.u_reg.u_combo_intr_status_combo3_h2l.wr_en_data_arb

SCORE	COND
80.00	60.00

tb.dut.u_reg.u_key_intr_status_pwrb_h2l.wr_en_data_arb

SCORE	COND
80.00	60.00

tb.dut.u_reg.u_key_intr_status_key0_in_h2l.wr_en_data_arb

SCORE	COND
80.00	60.00

tb.dut.u_reg.u_key_intr_status_key1_in_h2l.wr_en_data_arb

SCORE	COND
80.00	60.00

tb.dut.u_reg.u_key_intr_status_key2_in_h2l.wr_en_data_arb

SCORE	COND
80.00	60.00

tb.dut.u_reg.u_key_intr_status_ac_present_h2l.wr_en_data_arb

SCORE	COND
80.00	60.00

tb.dut.u_reg.u_key_intr_status_ec_rst_l_h2l.wr_en_data_arb

SCORE	COND
80.00	60.00

tb.dut.u_reg.u_key_intr_status_flash_wp_l_h2l.wr_en_data_arb

SCORE	COND
80.00	60.00

tb.dut.u_reg.u_key_intr_status_pwrb_l2h.wr_en_data_arb

SCORE	COND
80.00	60.00

tb.dut.u_reg.u_key_intr_status_key0_in_l2h.wr_en_data_arb

SCORE	COND
80.00	60.00

tb.dut.u_reg.u_key_intr_status_key1_in_l2h.wr_en_data_arb

SCORE	COND
80.00	60.00

tb.dut.u_reg.u_key_intr_status_key2_in_l2h.wr_en_data_arb

SCORE	COND
80.00	60.00

tb.dut.u_reg.u_key_intr_status_ac_present_l2h.wr_en_data_arb

SCORE	COND
80.00	60.00

tb.dut.u_reg.u_key_intr_status_ec_rst_l_l2h.wr_en_data_arb

SCORE	COND
80.00	60.00

tb.dut.u_reg.u_key_intr_status_flash_wp_l_l2h.wr_en_data_arb

	Total	Covered	Percent
Conditions	10	6	60.00
Logical	10	6	60.00
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       110
 EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
             ------1-----   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       110
 SUB-EXPRESSION (de ? d : q)
                 -1

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       110
 SUB-EXPRESSION (we ? ((~wd)) : '1)
                 -1

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_subreg_arb ( parameter DW=16,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_ec_rst_ctl.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_ulp_ac_debounce_ctl.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_ulp_lid_debounce_ctl.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_ulp_pwrb_debounce_ctl.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_intr_debounce_ctl.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_auto_block_debounce_ctl_debounce_timer.wr_en_data_arb

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_intr_enable.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_ulp_ctl.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_invert_ctl_key0_in.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_invert_ctl_key0_out.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_invert_ctl_key1_in.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_invert_ctl_key1_out.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_invert_ctl_key2_in.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_invert_ctl_key2_out.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_invert_ctl_pwrb_in.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_invert_ctl_pwrb_out.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_invert_ctl_ac_present.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_invert_ctl_bat_disable.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_invert_ctl_lid_open.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_invert_ctl_z3_wakeup.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_pin_allowed_ctl_bat_disable_0.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_pin_allowed_ctl_ec_rst_l_0.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_pin_allowed_ctl_pwrb_out_0.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_pin_allowed_ctl_key0_out_0.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_pin_allowed_ctl_key1_out_0.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_pin_allowed_ctl_key2_out_0.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_pin_allowed_ctl_z3_wakeup_0.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_pin_allowed_ctl_flash_wp_l_0.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_pin_allowed_ctl_bat_disable_1.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_pin_allowed_ctl_ec_rst_l_1.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_pin_allowed_ctl_pwrb_out_1.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_pin_allowed_ctl_key0_out_1.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_pin_allowed_ctl_key1_out_1.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_pin_allowed_ctl_key2_out_1.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_pin_allowed_ctl_z3_wakeup_1.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_pin_allowed_ctl_flash_wp_l_1.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_pin_out_ctl_bat_disable.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_pin_out_ctl_ec_rst_l.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_pin_out_ctl_pwrb_out.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_pin_out_ctl_key0_out.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_pin_out_ctl_key1_out.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_pin_out_ctl_key2_out.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_pin_out_ctl_z3_wakeup.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_pin_out_ctl_flash_wp_l.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_pin_out_value_bat_disable.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_pin_out_value_ec_rst_l.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_pin_out_value_pwrb_out.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_pin_out_value_key0_out.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_pin_out_value_key1_out.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_pin_out_value_key2_out.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_pin_out_value_z3_wakeup.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_pin_out_value_flash_wp_l.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_intr_ctl_pwrb_in_h2l.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_intr_ctl_key0_in_h2l.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_intr_ctl_key1_in_h2l.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_intr_ctl_key2_in_h2l.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_intr_ctl_ac_present_h2l.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_intr_ctl_ec_rst_l_h2l.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_intr_ctl_flash_wp_l_h2l.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_intr_ctl_pwrb_in_l2h.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_intr_ctl_key0_in_l2h.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_intr_ctl_key1_in_l2h.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_intr_ctl_key2_in_l2h.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_intr_ctl_ac_present_l2h.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_intr_ctl_ec_rst_l_l2h.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_intr_ctl_flash_wp_l_l2h.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_auto_block_debounce_ctl_auto_block_enable.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_auto_block_out_ctl_key0_out_sel.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_auto_block_out_ctl_key1_out_sel.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_auto_block_out_ctl_key2_out_sel.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_auto_block_out_ctl_key0_out_value.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_auto_block_out_ctl_key1_out_value.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_auto_block_out_ctl_key2_out_value.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_0_key0_in_sel_0.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_0_key1_in_sel_0.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_0_key2_in_sel_0.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_0_pwrb_in_sel_0.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_0_ac_present_sel_0.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_1_key0_in_sel_1.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_1_key1_in_sel_1.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_1_key2_in_sel_1.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_1_pwrb_in_sel_1.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_1_ac_present_sel_1.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_2_key0_in_sel_2.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_2_key1_in_sel_2.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_2_key2_in_sel_2.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_2_pwrb_in_sel_2.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_2_ac_present_sel_2.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_3_key0_in_sel_3.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_3_key1_in_sel_3.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_3_key2_in_sel_3.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_3_pwrb_in_sel_3.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_3_ac_present_sel_3.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_0_key0_in_sel_0.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_0_key1_in_sel_0.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_0_key2_in_sel_0.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_0_pwrb_in_sel_0.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_0_ac_present_sel_0.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_1_key0_in_sel_1.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_1_key1_in_sel_1.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_1_key2_in_sel_1.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_1_pwrb_in_sel_1.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_1_ac_present_sel_1.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_2_key0_in_sel_2.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_2_key1_in_sel_2.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_2_key2_in_sel_2.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_2_pwrb_in_sel_2.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_2_ac_present_sel_2.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_3_key0_in_sel_3.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_3_key1_in_sel_3.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_3_key2_in_sel_3.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_3_pwrb_in_sel_3.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_3_ac_present_sel_3.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_out_ctl_0_bat_disable_0.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_out_ctl_0_interrupt_0.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_out_ctl_0_ec_rst_0.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_out_ctl_0_rst_req_0.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_out_ctl_1_bat_disable_1.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_out_ctl_1_interrupt_1.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_out_ctl_1_ec_rst_1.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_out_ctl_1_rst_req_1.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_out_ctl_2_bat_disable_2.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_out_ctl_2_interrupt_2.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_out_ctl_2_ec_rst_2.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_out_ctl_2_rst_req_2.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_out_ctl_3_bat_disable_3.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_out_ctl_3_interrupt_3.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_out_ctl_3_ec_rst_3.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_out_ctl_3_rst_req_3.wr_en_data_arb

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=5,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_regwen.wr_en_data_arb

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       113
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       135
 EXPRESSION ((de ? d : q) & (we ? wd : '1))
             ------1-----   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       135
 SUB-EXPRESSION (de ? d : q)
                 -1

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Unreachable

 LINE       135
 SUB-EXPRESSION (we ? wd : '1)
                 -1

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_subreg_arb ( parameter DW=32,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_pre_det_ctl_0.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_pre_det_ctl_1.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_pre_det_ctl_2.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_pre_det_ctl_3.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_det_ctl_0.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_det_ctl_1.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_det_ctl_2.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_det_ctl_3.wr_en_data_arb

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_subreg_arb

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	34	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	34	((we == 1'b1)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3