Line Coverage for Module :
sysrst_ctrl_comboact
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 24 | 0 | 0.00 |
| CONT_ASSIGN | 34 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 35 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 36 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 37 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 41 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 48 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 49 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 52 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 53 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 62 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 63 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 70 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 71 | 1 | 0 | 0.00 |
| ALWAYS | 79 | 11 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_comboact.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_comboact.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 34 |
0 |
1 |
| 35 |
0 |
1 |
| 36 |
0 |
1 |
| 37 |
0 |
1 |
| 41 |
0 |
1 |
| 48 |
0 |
1 |
| 49 |
0 |
1 |
| 52 |
0 |
1 |
| 53 |
0 |
1 |
| 62 |
0 |
1 |
| 63 |
0 |
1 |
| 70 |
0 |
1 |
| 71 |
0 |
1 |
| 79 |
0 |
1 |
| 80 |
0 |
1 |
| 81 |
0 |
1 |
| 82 |
0 |
1 |
| 83 |
0 |
1 |
| 84 |
0 |
1 |
| 86 |
0 |
1 |
| 87 |
0 |
1 |
| 88 |
0 |
1 |
| 89 |
0 |
1 |
| 90 |
0 |
1 |
Cond Coverage for Module :
sysrst_ctrl_comboact
| Total | Covered | Percent |
|---|
| Conditions | 41 | 0 | 0.00 |
| Logical | 41 | 0 | 0.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 34
EXPRESSION (cfg_bat_disable_en_i & combo_det_pulse_i)
----------1--------- --------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
LINE 35
EXPRESSION (cfg_ec_rst_en_i & combo_det_pulse_i)
-------1------- --------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
LINE 36
EXPRESSION (cfg_rst_req_en_i & combo_det_pulse_i)
--------1------- --------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
LINE 37
EXPRESSION (cfg_intr_en_i & combo_det_pulse_i)
------1------ --------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
LINE 41
EXPRESSION (((~ec_rst_l_i)) & ec_rst_l_det_q)
-------1------- -------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
LINE 48
EXPRESSION (bat_disable_q | combo_bat_disable_pulse)
------1------ -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Not Covered | |
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
LINE 52
EXPRESSION (rst_req_q | combo_ot_pulse)
----1---- -------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Not Covered | |
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
LINE 63
EXPRESSION ((combo_ec_rst_pulse || ec_rst_l_det_pulse) ? 1'b0 : (timer_expired ? 1'b1 : ec_rst_l_q))
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Not Covered | |
LINE 63
SUB-EXPRESSION (combo_ec_rst_pulse || ec_rst_l_det_pulse)
---------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Not Covered | |
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
LINE 63
SUB-EXPRESSION (timer_expired ? 1'b1 : ec_rst_l_q)
------1------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Not Covered | |
LINE 70
EXPRESSION ((ec_rst_l_q == 1'b0) && (timer_cnt_q == ec_rst_ctl_i.q))
----------1--------- ---------------2---------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
LINE 70
SUB-EXPRESSION (ec_rst_l_q == 1'b0)
----------1---------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Not Covered | |
LINE 70
SUB-EXPRESSION (timer_cnt_q == ec_rst_ctl_i.q)
---------------1---------------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Not Covered | |
LINE 71
EXPRESSION (timer_expired ? '0 : ((ec_rst_l_q == 1'b0) ? ((timer_cnt_q + 1'b1)) : timer_cnt_q))
------1------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Not Covered | |
LINE 71
SUB-EXPRESSION ((ec_rst_l_q == 1'b0) ? ((timer_cnt_q + 1'b1)) : timer_cnt_q)
----------1---------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Not Covered | |
LINE 71
SUB-EXPRESSION (ec_rst_l_q == 1'b0)
----------1---------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Not Covered | |
Branch Coverage for Module :
sysrst_ctrl_comboact
| Line No. | Total | Covered | Percent |
| Branches |
|
8 |
0 |
0.00 |
| TERNARY |
63 |
3 |
0 |
0.00 |
| TERNARY |
71 |
3 |
0 |
0.00 |
| IF |
79 |
2 |
0 |
0.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_comboact.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_comboact.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 63 ((combo_ec_rst_pulse || ec_rst_l_det_pulse)) ?
-2-: 63 (timer_expired) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Not Covered |
|
| 0 |
1 |
Not Covered |
|
| 0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 71 (timer_expired) ?
-2-: 71 ((ec_rst_l_q == 1'b0)) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Not Covered |
|
| 0 |
1 |
Not Covered |
|
| 0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 79 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Not Covered |
|
| 0 |
Not Covered |
|
Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_combo_act
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 24 | 0 | 0.00 |
| CONT_ASSIGN | 34 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 35 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 36 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 37 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 41 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 48 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 49 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 52 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 53 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 62 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 63 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 70 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 71 | 1 | 0 | 0.00 |
| ALWAYS | 79 | 11 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_comboact.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_comboact.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 34 |
0 |
1 |
| 35 |
0 |
1 |
| 36 |
0 |
1 |
| 37 |
0 |
1 |
| 41 |
0 |
1 |
| 48 |
0 |
1 |
| 49 |
0 |
1 |
| 52 |
0 |
1 |
| 53 |
0 |
1 |
| 62 |
0 |
1 |
| 63 |
0 |
1 |
| 70 |
0 |
1 |
| 71 |
0 |
1 |
| 79 |
0 |
1 |
| 80 |
0 |
1 |
| 81 |
0 |
1 |
| 82 |
0 |
1 |
| 83 |
0 |
1 |
| 84 |
0 |
1 |
| 86 |
0 |
1 |
| 87 |
0 |
1 |
| 88 |
0 |
1 |
| 89 |
0 |
1 |
| 90 |
0 |
1 |
Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_combo_act
| Total | Covered | Percent |
|---|
| Conditions | 41 | 0 | 0.00 |
| Logical | 41 | 0 | 0.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 34
EXPRESSION (cfg_bat_disable_en_i & combo_det_pulse_i)
----------1--------- --------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
LINE 35
EXPRESSION (cfg_ec_rst_en_i & combo_det_pulse_i)
-------1------- --------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
LINE 36
EXPRESSION (cfg_rst_req_en_i & combo_det_pulse_i)
--------1------- --------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
LINE 37
EXPRESSION (cfg_intr_en_i & combo_det_pulse_i)
------1------ --------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
LINE 41
EXPRESSION (((~ec_rst_l_i)) & ec_rst_l_det_q)
-------1------- -------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
LINE 48
EXPRESSION (bat_disable_q | combo_bat_disable_pulse)
------1------ -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Not Covered | |
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
LINE 52
EXPRESSION (rst_req_q | combo_ot_pulse)
----1---- -------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Not Covered | |
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
LINE 63
EXPRESSION ((combo_ec_rst_pulse || ec_rst_l_det_pulse) ? 1'b0 : (timer_expired ? 1'b1 : ec_rst_l_q))
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Not Covered | |
LINE 63
SUB-EXPRESSION (combo_ec_rst_pulse || ec_rst_l_det_pulse)
---------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Not Covered | |
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
LINE 63
SUB-EXPRESSION (timer_expired ? 1'b1 : ec_rst_l_q)
------1------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Not Covered | |
LINE 70
EXPRESSION ((ec_rst_l_q == 1'b0) && (timer_cnt_q == ec_rst_ctl_i.q))
----------1--------- ---------------2---------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
LINE 70
SUB-EXPRESSION (ec_rst_l_q == 1'b0)
----------1---------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Not Covered | |
LINE 70
SUB-EXPRESSION (timer_cnt_q == ec_rst_ctl_i.q)
---------------1---------------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Not Covered | |
LINE 71
EXPRESSION (timer_expired ? '0 : ((ec_rst_l_q == 1'b0) ? ((timer_cnt_q + 1'b1)) : timer_cnt_q))
------1------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Not Covered | |
LINE 71
SUB-EXPRESSION ((ec_rst_l_q == 1'b0) ? ((timer_cnt_q + 1'b1)) : timer_cnt_q)
----------1---------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Not Covered | |
LINE 71
SUB-EXPRESSION (ec_rst_l_q == 1'b0)
----------1---------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Not Covered | |
Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_combo_act
| Line No. | Total | Covered | Percent |
| Branches |
|
8 |
0 |
0.00 |
| TERNARY |
63 |
3 |
0 |
0.00 |
| TERNARY |
71 |
3 |
0 |
0.00 |
| IF |
79 |
2 |
0 |
0.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_comboact.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_comboact.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 63 ((combo_ec_rst_pulse || ec_rst_l_det_pulse)) ?
-2-: 63 (timer_expired) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Not Covered |
|
| 0 |
1 |
Not Covered |
|
| 0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 71 (timer_expired) ?
-2-: 71 ((ec_rst_l_q == 1'b0)) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Not Covered |
|
| 0 |
1 |
Not Covered |
|
| 0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 79 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Not Covered |
|
| 0 |
Not Covered |
|
Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_combo_act
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 24 | 0 | 0.00 |
| CONT_ASSIGN | 34 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 35 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 36 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 37 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 41 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 48 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 49 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 52 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 53 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 62 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 63 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 70 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 71 | 1 | 0 | 0.00 |
| ALWAYS | 79 | 11 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_comboact.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_comboact.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 34 |
0 |
1 |
| 35 |
0 |
1 |
| 36 |
0 |
1 |
| 37 |
0 |
1 |
| 41 |
0 |
1 |
| 48 |
0 |
1 |
| 49 |
0 |
1 |
| 52 |
0 |
1 |
| 53 |
0 |
1 |
| 62 |
0 |
1 |
| 63 |
0 |
1 |
| 70 |
0 |
1 |
| 71 |
0 |
1 |
| 79 |
0 |
1 |
| 80 |
0 |
1 |
| 81 |
0 |
1 |
| 82 |
0 |
1 |
| 83 |
0 |
1 |
| 84 |
0 |
1 |
| 86 |
0 |
1 |
| 87 |
0 |
1 |
| 88 |
0 |
1 |
| 89 |
0 |
1 |
| 90 |
0 |
1 |
Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_combo_act
| Total | Covered | Percent |
|---|
| Conditions | 41 | 0 | 0.00 |
| Logical | 41 | 0 | 0.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 34
EXPRESSION (cfg_bat_disable_en_i & combo_det_pulse_i)
----------1--------- --------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
LINE 35
EXPRESSION (cfg_ec_rst_en_i & combo_det_pulse_i)
-------1------- --------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
LINE 36
EXPRESSION (cfg_rst_req_en_i & combo_det_pulse_i)
--------1------- --------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
LINE 37
EXPRESSION (cfg_intr_en_i & combo_det_pulse_i)
------1------ --------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
LINE 41
EXPRESSION (((~ec_rst_l_i)) & ec_rst_l_det_q)
-------1------- -------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
LINE 48
EXPRESSION (bat_disable_q | combo_bat_disable_pulse)
------1------ -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Not Covered | |
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
LINE 52
EXPRESSION (rst_req_q | combo_ot_pulse)
----1---- -------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Not Covered | |
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
LINE 63
EXPRESSION ((combo_ec_rst_pulse || ec_rst_l_det_pulse) ? 1'b0 : (timer_expired ? 1'b1 : ec_rst_l_q))
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Not Covered | |
LINE 63
SUB-EXPRESSION (combo_ec_rst_pulse || ec_rst_l_det_pulse)
---------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Not Covered | |
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
LINE 63
SUB-EXPRESSION (timer_expired ? 1'b1 : ec_rst_l_q)
------1------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Not Covered | |
LINE 70
EXPRESSION ((ec_rst_l_q == 1'b0) && (timer_cnt_q == ec_rst_ctl_i.q))
----------1--------- ---------------2---------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
LINE 70
SUB-EXPRESSION (ec_rst_l_q == 1'b0)
----------1---------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Not Covered | |
LINE 70
SUB-EXPRESSION (timer_cnt_q == ec_rst_ctl_i.q)
---------------1---------------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Not Covered | |
LINE 71
EXPRESSION (timer_expired ? '0 : ((ec_rst_l_q == 1'b0) ? ((timer_cnt_q + 1'b1)) : timer_cnt_q))
------1------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Not Covered | |
LINE 71
SUB-EXPRESSION ((ec_rst_l_q == 1'b0) ? ((timer_cnt_q + 1'b1)) : timer_cnt_q)
----------1---------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Not Covered | |
LINE 71
SUB-EXPRESSION (ec_rst_l_q == 1'b0)
----------1---------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Not Covered | |
Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_combo_act
| Line No. | Total | Covered | Percent |
| Branches |
|
8 |
0 |
0.00 |
| TERNARY |
63 |
3 |
0 |
0.00 |
| TERNARY |
71 |
3 |
0 |
0.00 |
| IF |
79 |
2 |
0 |
0.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_comboact.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_comboact.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 63 ((combo_ec_rst_pulse || ec_rst_l_det_pulse)) ?
-2-: 63 (timer_expired) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Not Covered |
|
| 0 |
1 |
Not Covered |
|
| 0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 71 (timer_expired) ?
-2-: 71 ((ec_rst_l_q == 1'b0)) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Not Covered |
|
| 0 |
1 |
Not Covered |
|
| 0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 79 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Not Covered |
|
| 0 |
Not Covered |
|
Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_combo_act
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 24 | 0 | 0.00 |
| CONT_ASSIGN | 34 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 35 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 36 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 37 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 41 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 48 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 49 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 52 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 53 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 62 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 63 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 70 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 71 | 1 | 0 | 0.00 |
| ALWAYS | 79 | 11 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_comboact.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_comboact.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 34 |
0 |
1 |
| 35 |
0 |
1 |
| 36 |
0 |
1 |
| 37 |
0 |
1 |
| 41 |
0 |
1 |
| 48 |
0 |
1 |
| 49 |
0 |
1 |
| 52 |
0 |
1 |
| 53 |
0 |
1 |
| 62 |
0 |
1 |
| 63 |
0 |
1 |
| 70 |
0 |
1 |
| 71 |
0 |
1 |
| 79 |
0 |
1 |
| 80 |
0 |
1 |
| 81 |
0 |
1 |
| 82 |
0 |
1 |
| 83 |
0 |
1 |
| 84 |
0 |
1 |
| 86 |
0 |
1 |
| 87 |
0 |
1 |
| 88 |
0 |
1 |
| 89 |
0 |
1 |
| 90 |
0 |
1 |
Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_combo_act
| Total | Covered | Percent |
|---|
| Conditions | 41 | 0 | 0.00 |
| Logical | 41 | 0 | 0.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 34
EXPRESSION (cfg_bat_disable_en_i & combo_det_pulse_i)
----------1--------- --------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
LINE 35
EXPRESSION (cfg_ec_rst_en_i & combo_det_pulse_i)
-------1------- --------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
LINE 36
EXPRESSION (cfg_rst_req_en_i & combo_det_pulse_i)
--------1------- --------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
LINE 37
EXPRESSION (cfg_intr_en_i & combo_det_pulse_i)
------1------ --------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
LINE 41
EXPRESSION (((~ec_rst_l_i)) & ec_rst_l_det_q)
-------1------- -------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
LINE 48
EXPRESSION (bat_disable_q | combo_bat_disable_pulse)
------1------ -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Not Covered | |
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
LINE 52
EXPRESSION (rst_req_q | combo_ot_pulse)
----1---- -------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Not Covered | |
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
LINE 63
EXPRESSION ((combo_ec_rst_pulse || ec_rst_l_det_pulse) ? 1'b0 : (timer_expired ? 1'b1 : ec_rst_l_q))
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Not Covered | |
LINE 63
SUB-EXPRESSION (combo_ec_rst_pulse || ec_rst_l_det_pulse)
---------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Not Covered | |
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
LINE 63
SUB-EXPRESSION (timer_expired ? 1'b1 : ec_rst_l_q)
------1------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Not Covered | |
LINE 70
EXPRESSION ((ec_rst_l_q == 1'b0) && (timer_cnt_q == ec_rst_ctl_i.q))
----------1--------- ---------------2---------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
LINE 70
SUB-EXPRESSION (ec_rst_l_q == 1'b0)
----------1---------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Not Covered | |
LINE 70
SUB-EXPRESSION (timer_cnt_q == ec_rst_ctl_i.q)
---------------1---------------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Not Covered | |
LINE 71
EXPRESSION (timer_expired ? '0 : ((ec_rst_l_q == 1'b0) ? ((timer_cnt_q + 1'b1)) : timer_cnt_q))
------1------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Not Covered | |
LINE 71
SUB-EXPRESSION ((ec_rst_l_q == 1'b0) ? ((timer_cnt_q + 1'b1)) : timer_cnt_q)
----------1---------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Not Covered | |
LINE 71
SUB-EXPRESSION (ec_rst_l_q == 1'b0)
----------1---------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Not Covered | |
Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_combo_act
| Line No. | Total | Covered | Percent |
| Branches |
|
8 |
0 |
0.00 |
| TERNARY |
63 |
3 |
0 |
0.00 |
| TERNARY |
71 |
3 |
0 |
0.00 |
| IF |
79 |
2 |
0 |
0.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_comboact.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_comboact.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 63 ((combo_ec_rst_pulse || ec_rst_l_det_pulse)) ?
-2-: 63 (timer_expired) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Not Covered |
|
| 0 |
1 |
Not Covered |
|
| 0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 71 (timer_expired) ?
-2-: 71 ((ec_rst_l_q == 1'b0)) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Not Covered |
|
| 0 |
1 |
Not Covered |
|
| 0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 79 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Not Covered |
|
| 0 |
Not Covered |
|
Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_combo_act
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 24 | 0 | 0.00 |
| CONT_ASSIGN | 34 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 35 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 36 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 37 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 41 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 48 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 49 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 52 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 53 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 62 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 63 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 70 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 71 | 1 | 0 | 0.00 |
| ALWAYS | 79 | 11 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_comboact.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_comboact.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 34 |
0 |
1 |
| 35 |
0 |
1 |
| 36 |
0 |
1 |
| 37 |
0 |
1 |
| 41 |
0 |
1 |
| 48 |
0 |
1 |
| 49 |
0 |
1 |
| 52 |
0 |
1 |
| 53 |
0 |
1 |
| 62 |
0 |
1 |
| 63 |
0 |
1 |
| 70 |
0 |
1 |
| 71 |
0 |
1 |
| 79 |
0 |
1 |
| 80 |
0 |
1 |
| 81 |
0 |
1 |
| 82 |
0 |
1 |
| 83 |
0 |
1 |
| 84 |
0 |
1 |
| 86 |
0 |
1 |
| 87 |
0 |
1 |
| 88 |
0 |
1 |
| 89 |
0 |
1 |
| 90 |
0 |
1 |
Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_combo_act
| Total | Covered | Percent |
|---|
| Conditions | 41 | 0 | 0.00 |
| Logical | 41 | 0 | 0.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 34
EXPRESSION (cfg_bat_disable_en_i & combo_det_pulse_i)
----------1--------- --------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
LINE 35
EXPRESSION (cfg_ec_rst_en_i & combo_det_pulse_i)
-------1------- --------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
LINE 36
EXPRESSION (cfg_rst_req_en_i & combo_det_pulse_i)
--------1------- --------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
LINE 37
EXPRESSION (cfg_intr_en_i & combo_det_pulse_i)
------1------ --------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
LINE 41
EXPRESSION (((~ec_rst_l_i)) & ec_rst_l_det_q)
-------1------- -------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
LINE 48
EXPRESSION (bat_disable_q | combo_bat_disable_pulse)
------1------ -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Not Covered | |
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
LINE 52
EXPRESSION (rst_req_q | combo_ot_pulse)
----1---- -------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Not Covered | |
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
LINE 63
EXPRESSION ((combo_ec_rst_pulse || ec_rst_l_det_pulse) ? 1'b0 : (timer_expired ? 1'b1 : ec_rst_l_q))
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Not Covered | |
LINE 63
SUB-EXPRESSION (combo_ec_rst_pulse || ec_rst_l_det_pulse)
---------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Not Covered | |
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
LINE 63
SUB-EXPRESSION (timer_expired ? 1'b1 : ec_rst_l_q)
------1------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Not Covered | |
LINE 70
EXPRESSION ((ec_rst_l_q == 1'b0) && (timer_cnt_q == ec_rst_ctl_i.q))
----------1--------- ---------------2---------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
LINE 70
SUB-EXPRESSION (ec_rst_l_q == 1'b0)
----------1---------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Not Covered | |
LINE 70
SUB-EXPRESSION (timer_cnt_q == ec_rst_ctl_i.q)
---------------1---------------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Not Covered | |
LINE 71
EXPRESSION (timer_expired ? '0 : ((ec_rst_l_q == 1'b0) ? ((timer_cnt_q + 1'b1)) : timer_cnt_q))
------1------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Not Covered | |
LINE 71
SUB-EXPRESSION ((ec_rst_l_q == 1'b0) ? ((timer_cnt_q + 1'b1)) : timer_cnt_q)
----------1---------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Not Covered | |
LINE 71
SUB-EXPRESSION (ec_rst_l_q == 1'b0)
----------1---------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Not Covered | |
Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_combo_act
| Line No. | Total | Covered | Percent |
| Branches |
|
8 |
0 |
0.00 |
| TERNARY |
63 |
3 |
0 |
0.00 |
| TERNARY |
71 |
3 |
0 |
0.00 |
| IF |
79 |
2 |
0 |
0.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_comboact.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_comboact.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 63 ((combo_ec_rst_pulse || ec_rst_l_det_pulse)) ?
-2-: 63 (timer_expired) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Not Covered |
|
| 0 |
1 |
Not Covered |
|
| 0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 71 (timer_expired) ?
-2-: 71 ((ec_rst_l_q == 1'b0)) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Not Covered |
|
| 0 |
1 |
Not Covered |
|
| 0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 79 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Not Covered |
|
| 0 |
Not Covered |
|