Assertions
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Assertions by Category
ASSERTPROPERTIESSEQUENCES
Total1028010
Category 01028010

Assertions by Severity
ASSERTPROPERTIESSEQUENCES
Total1028010
Severity 01028010

Summary for Assertions
NUMBERPERCENT
Total Number1028100.00
Uncovered121.17
Success101698.83
Failure00.00
Incomplete10.10
Without Attempts00.00

Summary for Cover Sequences
NUMBERPERCENT
Total Number10100.00
Uncovered00.00
All Matches10100.00
First Matches10100.00
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ASSERTIONSCATEGORYSEVERITYATTEMPTSREAL SUCCESSESFAILURESINCOMPLETE
tb.dut.tlul_assert_device.gen_assert_final[3].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[40].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[41].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[42].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[43].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[44].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[45].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[46].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[47].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[48].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[49].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[4].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[50].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[51].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[52].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[53].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[54].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[55].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[56].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[57].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[58].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[59].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[5].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[60].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[61].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[62].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[63].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[64].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[65].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[66].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[67].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[68].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[69].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[6].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[70].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[71].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[72].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[73].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[74].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[75].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[76].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[77].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[78].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[79].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[7].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[80].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[81].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[82].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[83].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[84].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[85].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[86].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[87].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[88].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[89].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[8].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[90].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[91].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[92].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[93].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[94].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[95].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[96].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[97].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[98].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[99].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[9].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_device.aDataKnown_M 001278357903229685700
tb.dut.tlul_assert_device.gen_device.addrSizeAlignedErr_A 001278357336611600
tb.dut.tlul_assert_device.gen_device.contigMask_M 0012783579031287379600
tb.dut.tlul_assert_device.gen_device.dDataKnown_A 00127835790319223600
tb.dut.tlul_assert_device.gen_device.legalAOpcodeErr_A 001278357336643200
tb.dut.tlul_assert_device.gen_device.legalAParam_M 0012783579031428120200
tb.dut.tlul_assert_device.gen_device.legalDParam_A 00127835790355926500
tb.dut.tlul_assert_device.gen_device.pendingReqPerSrc_M 0012783579031428120200
tb.dut.tlul_assert_device.gen_device.respMustHaveReq_A 00127835790355926500
tb.dut.tlul_assert_device.gen_device.respOpcode_A 00127835790355926500
tb.dut.tlul_assert_device.gen_device.respSzEqReqSz_A 00127835790355926500
tb.dut.tlul_assert_device.gen_device.sizeGTEMaskErr_A 001278357336385100
tb.dut.tlul_assert_device.gen_device.sizeMatchesMaskErr_A 001278357336345100
tb.dut.tlul_assert_device.p_dbw.TlDbw_A 0091591500
tb.dut.u_reg.en2addrHit 00127835733625129200
tb.dut.u_reg.reAfterRv 00127835733625129200
tb.dut.u_reg.rePulse 00127835733613671000
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.BusySrcReqChk_A 001278357336108568500
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.DstReqKnown_A 007625041695629600
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.SrcAckBusyChk_A 001278357336117600
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.SrcBusyKnown_A 001278357336127792976300
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001278357336117600
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 007625041117600
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A 007625041113400
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M 001278357336118500
tb.dut.u_reg.u_auto_block_out_ctl_cdc.BusySrcReqChk_A 00127835733698943100
tb.dut.u_reg.u_auto_block_out_ctl_cdc.DstReqKnown_A 007625041695629600
tb.dut.u_reg.u_auto_block_out_ctl_cdc.SrcAckBusyChk_A 001278357336111000
tb.dut.u_reg.u_auto_block_out_ctl_cdc.SrcBusyKnown_A 001278357336127792976300
tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001278357336111000
tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 007625041111000
tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A 007625041106400
tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M 001278357336112100
tb.dut.u_reg.u_chk.PayLoadWidthCheck 0091591500
tb.dut.u_reg.u_com_det_ctl_0_cdc.BusySrcReqChk_A 001278357336162502300
tb.dut.u_reg.u_com_det_ctl_0_cdc.DstReqKnown_A 007625041695629600
tb.dut.u_reg.u_com_det_ctl_0_cdc.SrcAckBusyChk_A 001278357336174700
tb.dut.u_reg.u_com_det_ctl_0_cdc.SrcBusyKnown_A 001278357336127792976300
tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001278357336174700
tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 007625041174700
tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req.DstPulseCheck_A 007625041170000
tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req.SrcPulseCheck_M 001278357336175500
tb.dut.u_reg.u_com_det_ctl_1_cdc.BusySrcReqChk_A 001278357336160860500
tb.dut.u_reg.u_com_det_ctl_1_cdc.DstReqKnown_A 007625041695629600
tb.dut.u_reg.u_com_det_ctl_1_cdc.SrcAckBusyChk_A 001278357336178100
tb.dut.u_reg.u_com_det_ctl_1_cdc.SrcBusyKnown_A 001278357336127792976300
tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001278357336178100
tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 007625041178100
tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req.DstPulseCheck_A 007625041173700
tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req.SrcPulseCheck_M 001278357336179100
tb.dut.u_reg.u_com_det_ctl_2_cdc.BusySrcReqChk_A 001278357336156516300
tb.dut.u_reg.u_com_det_ctl_2_cdc.DstReqKnown_A 007625041695629600
tb.dut.u_reg.u_com_det_ctl_2_cdc.SrcAckBusyChk_A 001278357336175200
tb.dut.u_reg.u_com_det_ctl_2_cdc.SrcBusyKnown_A 001278357336127792976300
tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001278357336175200
tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 007625041175200
tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req.DstPulseCheck_A 007625041170900
tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req.SrcPulseCheck_M 001278357336176000
tb.dut.u_reg.u_com_det_ctl_3_cdc.BusySrcReqChk_A 001278357336158839500
tb.dut.u_reg.u_com_det_ctl_3_cdc.DstReqKnown_A 007625041695629600
tb.dut.u_reg.u_com_det_ctl_3_cdc.SrcAckBusyChk_A 001278357336178400
tb.dut.u_reg.u_com_det_ctl_3_cdc.SrcBusyKnown_A 001278357336127792976300
tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001278357336178400
tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 007625041178400
tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req.DstPulseCheck_A 007625041173800
tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req.SrcPulseCheck_M 001278357336179200
tb.dut.u_reg.u_com_out_ctl_0_cdc.BusySrcReqChk_A 001278357336162591000
tb.dut.u_reg.u_com_out_ctl_0_cdc.DstReqKnown_A 007625041695629600
tb.dut.u_reg.u_com_out_ctl_0_cdc.SrcAckBusyChk_A 001278357336177800
tb.dut.u_reg.u_com_out_ctl_0_cdc.SrcBusyKnown_A 001278357336127792976300
tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001278357336177800
tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 007625041177800
tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req.DstPulseCheck_A 007625041173500
tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req.SrcPulseCheck_M 001278357336178600
tb.dut.u_reg.u_com_out_ctl_1_cdc.BusySrcReqChk_A 001278357336160249400
tb.dut.u_reg.u_com_out_ctl_1_cdc.DstReqKnown_A 007625041695629600
tb.dut.u_reg.u_com_out_ctl_1_cdc.SrcAckBusyChk_A 001278357336175900
tb.dut.u_reg.u_com_out_ctl_1_cdc.SrcBusyKnown_A 001278357336127792976300
tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001278357336175900
tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 007625041175900
tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req.DstPulseCheck_A 007625041172200
tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req.SrcPulseCheck_M 001278357336176600
tb.dut.u_reg.u_com_out_ctl_2_cdc.BusySrcReqChk_A 001278357336158858500
tb.dut.u_reg.u_com_out_ctl_2_cdc.DstReqKnown_A 007625041695629600
tb.dut.u_reg.u_com_out_ctl_2_cdc.SrcAckBusyChk_A 001278357336177500
tb.dut.u_reg.u_com_out_ctl_2_cdc.SrcBusyKnown_A 001278357336127792976300
tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001278357336177500
tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 007625041177500
tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req.DstPulseCheck_A 007625041173200
tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req.SrcPulseCheck_M 001278357336178300
tb.dut.u_reg.u_com_out_ctl_3_cdc.BusySrcReqChk_A 001278357336155642700
tb.dut.u_reg.u_com_out_ctl_3_cdc.DstReqKnown_A 007625041695629600
tb.dut.u_reg.u_com_out_ctl_3_cdc.SrcAckBusyChk_A 001278357336175200
tb.dut.u_reg.u_com_out_ctl_3_cdc.SrcBusyKnown_A 001278357336127792976300
tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001278357336175200
tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 007625041175200
tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req.DstPulseCheck_A 007625041171000
tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req.SrcPulseCheck_M 001278357336176300
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.BusySrcReqChk_A 001278357336105009600
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.DstReqKnown_A 007625041695629600
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.SrcAckBusyChk_A 001278357336116400
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.SrcBusyKnown_A 001278357336127792976300
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001278357336116400
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 007625041116400
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req.DstPulseCheck_A 007625041111900
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req.SrcPulseCheck_M 001278357336117300
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.BusySrcReqChk_A 001278357336105843200
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.DstReqKnown_A 007625041695629600
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.SrcAckBusyChk_A 001278357336119000
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.SrcBusyKnown_A 001278357336127792976300
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001278357336119000
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 007625041119000
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req.DstPulseCheck_A 007625041114600
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req.SrcPulseCheck_M 001278357336120000
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.BusySrcReqChk_A 001278357336106186200
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.DstReqKnown_A 007625041695629600
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.SrcAckBusyChk_A 001278357336117700
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.SrcBusyKnown_A 001278357336127792976300
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001278357336117700
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 007625041117700
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req.DstPulseCheck_A 007625041113600
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req.SrcPulseCheck_M 001278357336118800
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.BusySrcReqChk_A 00127835733699382500
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.DstReqKnown_A 007625041695629600
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.SrcAckBusyChk_A 001278357336115700
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.SrcBusyKnown_A 001278357336127792976300
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001278357336115700
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 007625041115700
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req.DstPulseCheck_A 007625041111600
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req.SrcPulseCheck_M 001278357336116600
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.BusySrcReqChk_A 001278357336707982300
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.DstReqKnown_A 007625041695629600
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.SrcAckBusyChk_A 001278357336715500
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.SrcBusyKnown_A 001278357336127792976300
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001278357336715500
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 007625041715500
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req.DstPulseCheck_A 007625041711200
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req.SrcPulseCheck_M 001278357336716300
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.BusySrcReqChk_A 001278357336700005600
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.DstReqKnown_A 007625041695629600
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.SrcAckBusyChk_A 001278357336710900
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.SrcBusyKnown_A 001278357336127792976300
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001278357336710900
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 007625041710900
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req.DstPulseCheck_A 007625041706700
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req.SrcPulseCheck_M 001278357336711800
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.BusySrcReqChk_A 001278357336681129800
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.DstReqKnown_A 007625041695629600
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.SrcAckBusyChk_A 001278357336695200
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.SrcBusyKnown_A 001278357336127792976300
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001278357336695200
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 007625041695200
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req.DstPulseCheck_A 007625041690400
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req.SrcPulseCheck_M 001278357336696100
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.BusySrcReqChk_A 001278357336709507300
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.DstReqKnown_A 007625041695629600
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.SrcAckBusyChk_A 001278357336724800
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.SrcBusyKnown_A 001278357336127792976300
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001278357336724800
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 007625041724800
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req.DstPulseCheck_A 007625041720700
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req.SrcPulseCheck_M 001278357336725600
tb.dut.u_reg.u_com_sel_ctl_0_cdc.BusySrcReqChk_A 001278357336772026400
tb.dut.u_reg.u_com_sel_ctl_0_cdc.DstReqKnown_A 007625041695629600
tb.dut.u_reg.u_com_sel_ctl_0_cdc.SrcAckBusyChk_A 001278357336775800
tb.dut.u_reg.u_com_sel_ctl_0_cdc.SrcBusyKnown_A 001278357336127792976300
tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001278357336775800
tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 007625041775800
tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req.DstPulseCheck_A 007625041771500
tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req.SrcPulseCheck_M 001278357336776500
tb.dut.u_reg.u_com_sel_ctl_1_cdc.BusySrcReqChk_A 001278357336756543800
tb.dut.u_reg.u_com_sel_ctl_1_cdc.DstReqKnown_A 007625041695629600
tb.dut.u_reg.u_com_sel_ctl_1_cdc.SrcAckBusyChk_A 001278357336763600
tb.dut.u_reg.u_com_sel_ctl_1_cdc.SrcBusyKnown_A 001278357336127792976300
tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001278357336763600
tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 007625041763600
tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req.DstPulseCheck_A 007625041759200
tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req.SrcPulseCheck_M 001278357336764600
tb.dut.u_reg.u_com_sel_ctl_2_cdc.BusySrcReqChk_A 001278357336743697700
tb.dut.u_reg.u_com_sel_ctl_2_cdc.DstReqKnown_A 007625041695629600
tb.dut.u_reg.u_com_sel_ctl_2_cdc.SrcAckBusyChk_A 001278357336757200
tb.dut.u_reg.u_com_sel_ctl_2_cdc.SrcBusyKnown_A 001278357336127792976300
tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001278357336757200
tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 007625041757200
tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req.DstPulseCheck_A 007625041753000
tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req.SrcPulseCheck_M 001278357336758200
tb.dut.u_reg.u_com_sel_ctl_3_cdc.BusySrcReqChk_A 001278357336767597000
tb.dut.u_reg.u_com_sel_ctl_3_cdc.DstReqKnown_A 007625041695629600
tb.dut.u_reg.u_com_sel_ctl_3_cdc.SrcAckBusyChk_A 001278357336781200
tb.dut.u_reg.u_com_sel_ctl_3_cdc.SrcBusyKnown_A 001278357336127792976300
tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001278357336781200
tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 007625041781200
tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req.DstPulseCheck_A 007625041776700
tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req.SrcPulseCheck_M 001278357336782100
tb.dut.u_reg.u_ec_rst_ctl_cdc.BusySrcReqChk_A 001278357336164114700
tb.dut.u_reg.u_ec_rst_ctl_cdc.DstReqKnown_A 007625041695629600
tb.dut.u_reg.u_ec_rst_ctl_cdc.SrcAckBusyChk_A 001278357336180400
tb.dut.u_reg.u_ec_rst_ctl_cdc.SrcBusyKnown_A 001278357336127792976300
tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001278357336180400
tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 007625041180400
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