Module Definition
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Module : prim_pulse_sync
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00

Source File(s) :
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv

Module self-instances :
NAME   SCORE   LINE   COND   TOGGLE   FSM   BRANCH   ASSERT   
tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_ec_rst_ctl_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
83.33 100.00 66.67 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_ulp_ac_debounce_ctl_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
83.33 100.00 66.67 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_ulp_lid_debounce_ctl_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
83.33 100.00 66.67 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_ulp_pwrb_debounce_ctl_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
83.33 100.00 66.67 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.08 100.00 92.31 100.00 100.00 u_ulp_ctl_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.88 100.00 87.50 100.00 100.00 u_wkup_status_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_key_invert_ctl_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_pin_allowed_ctl_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_pin_out_ctl_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_pin_out_value_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_key_intr_ctl_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_key_intr_debounce_ctl_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
83.33 100.00 66.67 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_auto_block_debounce_ctl_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
83.33 100.00 66.67 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_auto_block_out_ctl_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_com_pre_sel_ctl_0_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_com_pre_sel_ctl_1_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_com_pre_sel_ctl_2_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_com_pre_sel_ctl_3_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_com_pre_det_ctl_0_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_com_pre_det_ctl_1_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_com_pre_det_ctl_2_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_com_pre_det_ctl_3_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_com_sel_ctl_0_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_com_sel_ctl_1_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_com_sel_ctl_2_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_com_sel_ctl_3_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_com_det_ctl_0_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_com_det_ctl_1_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_com_det_ctl_2_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_com_det_ctl_3_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_com_out_ctl_0_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_com_out_ctl_1_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_com_out_ctl_2_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_com_out_ctl_3_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00

Line Coverage for Module : prim_pulse_sync
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00

30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin 31 1/1 if (!rst_src_ni) begin Tests: T1 T2 T4  32 1/1 src_level <= 1'b0; Tests: T1 T2 T4  33 end else begin 34 1/1 src_level <= src_level ^ src_pulse_i; Tests: T1 T2 T4  35 end 36 end 37 38 39 // source active must come far enough such that the destination domain has time 40 // to create a valid pulse. 41 `ifdef INC_ASSERT 42 //VCS coverage off 43 // pragma coverage off 44 45 // source active flag tracks whether there is an ongoing "toggle" event. 46 // Until this toggle event is accepted by the destination domain (negative edge of 47 // of the pulse output), the source side cannot toggle again. 48 logic effective_rst_n; 49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o; 50 51 logic src_active_flag_d, src_active_flag_q; 52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q; 53 54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin 55 unreachable if (!effective_rst_n) begin 56 unreachable src_active_flag_q <= '0; 57 end else begin 58 unreachable src_active_flag_q <= src_active_flag_d; 59 end 60 end 61 62 //VCS coverage on 63 // pragma coverage on 64 65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni) 66 `endif 67 68 ////////////////////////////////////////////////////////// 69 // synchronize level signal to destination clock domain // 70 ////////////////////////////////////////////////////////// 71 logic dst_level; 72 73 prim_flop_2sync #(.Width(1)) prim_flop_2sync ( 74 // source clock domain 75 .d_i (src_level), 76 // destination clock domain 77 .clk_i (clk_dst_i), 78 .rst_ni (rst_dst_ni), 79 .q_o (dst_level) 80 ); 81 82 //////////////////////////////////////// 83 // convert level signal back to pulse // 84 //////////////////////////////////////// 85 logic dst_level_q; 86 87 // delay dst_level by 1 cycle 88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin 89 1/1 if (!rst_dst_ni) begin Tests: T1 T2 T4  90 1/1 dst_level_q <= 1'b0; Tests: T1 T2 T4  91 end else begin 92 1/1 dst_level_q <= dst_level; Tests: T1 T2 T4  93 end 94 end 95 96 // edge detection 97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level; Tests: T1 T2 T4 

Cond Coverage for Module : prim_pulse_sync
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT1,T2,T12
10CoveredT1,T2,T12
11CoveredT5,T39,T70

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT1,T2,T12
10CoveredT5,T39,T70
11CoveredT1,T2,T12

Branch Coverage for Module : prim_pulse_sync
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00


31 if (!rst_src_ni) begin -1- 32 src_level <= 1'b0; ==> 33 end else begin 34 src_level <= src_level ^ src_pulse_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


89 if (!rst_dst_ni) begin -1- 90 dst_level_q <= 1'b0; ==> 91 end else begin 92 dst_level_q <= dst_level; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


Assert Coverage for Module : prim_pulse_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
DstPulseCheck_A 2147483647 242344 0 0
SrcPulseCheck_M 2147483647 244679 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 242344 0 0
T1 64157 2 0 0
T2 58803 2 0 0
T3 648228 0 0 0
T4 131976 14 0 0
T6 568425 3 0 0
T7 0 2 0 0
T8 240611 0 0 0
T11 0 36 0 0
T12 59109 0 0 0
T13 386625 0 0 0
T14 588966 0 0 0
T15 305751 0 0 0
T16 392574 0 0 0
T17 154959 0 0 0
T21 0 15 0 0
T22 472798 0 0 0
T27 0 18 0 0
T28 0 14 0 0
T29 52546 2 0 0
T30 0 2 0 0
T31 122118 2 0 0
T32 0 7 0 0
T57 53142 2 0 0
T58 0 14 0 0
T59 0 2 0 0
T60 0 10 0 0
T61 0 14 0 0
T62 0 14 0 0
T63 0 16 0 0
T64 0 16 0 0
T65 251010 0 0 0
T66 48764 0 0 0
T67 53084 0 0 0
T68 393069 0 0 0
T69 21542 0 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 244679 0 0
T1 64157 2 0 0
T2 58803 2 0 0
T3 648228 0 0 0
T4 131976 14 0 0
T6 7579 3 0 0
T7 0 2 0 0
T8 627 0 0 0
T11 0 36 0 0
T12 59109 0 0 0
T13 386625 0 0 0
T14 588966 0 0 0
T15 305751 0 0 0
T16 392574 0 0 0
T17 154959 0 0 0
T21 0 15 0 0
T22 472798 0 0 0
T27 0 18 0 0
T28 0 14 0 0
T29 456 2 0 0
T30 0 2 0 0
T31 122118 2 0 0
T32 0 7 0 0
T57 443 2 0 0
T58 0 14 0 0
T59 0 2 0 0
T60 0 10 0 0
T61 0 14 0 0
T62 0 14 0 0
T63 0 16 0 0
T64 0 16 0 0
T65 522 0 0 0
T66 406 0 0 0
T67 424 0 0 0
T68 818 0 0 0
T69 615 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00

30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin 31 1/1 if (!rst_src_ni) begin Tests: T1 T2 T4  32 1/1 src_level <= 1'b0; Tests: T1 T2 T4  33 end else begin 34 1/1 src_level <= src_level ^ src_pulse_i; Tests: T1 T2 T4  35 end 36 end 37 38 39 // source active must come far enough such that the destination domain has time 40 // to create a valid pulse. 41 `ifdef INC_ASSERT 42 //VCS coverage off 43 // pragma coverage off 44 45 // source active flag tracks whether there is an ongoing "toggle" event. 46 // Until this toggle event is accepted by the destination domain (negative edge of 47 // of the pulse output), the source side cannot toggle again. 48 logic effective_rst_n; 49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o; 50 51 logic src_active_flag_d, src_active_flag_q; 52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q; 53 54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin 55 unreachable if (!effective_rst_n) begin 56 unreachable src_active_flag_q <= '0; 57 end else begin 58 unreachable src_active_flag_q <= src_active_flag_d; 59 end 60 end 61 62 //VCS coverage on 63 // pragma coverage on 64 65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni) 66 `endif 67 68 ////////////////////////////////////////////////////////// 69 // synchronize level signal to destination clock domain // 70 ////////////////////////////////////////////////////////// 71 logic dst_level; 72 73 prim_flop_2sync #(.Width(1)) prim_flop_2sync ( 74 // source clock domain 75 .d_i (src_level), 76 // destination clock domain 77 .clk_i (clk_dst_i), 78 .rst_ni (rst_dst_ni), 79 .q_o (dst_level) 80 ); 81 82 //////////////////////////////////////// 83 // convert level signal back to pulse // 84 //////////////////////////////////////// 85 logic dst_level_q; 86 87 // delay dst_level by 1 cycle 88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin 89 1/1 if (!rst_dst_ni) begin Tests: T1 T2 T4  90 1/1 dst_level_q <= 1'b0; Tests: T1 T2 T4  91 end else begin 92 1/1 dst_level_q <= dst_level; Tests: T1 T2 T4  93 end 94 end 95 96 // edge detection 97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level; Tests: T1 T2 T16 

Cond Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT1,T2,T16
10CoveredT1,T2,T16
11CoveredT34,T37,T18

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT1,T2,T16
10CoveredT34,T37,T18
11CoveredT1,T2,T16

Branch Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00


31 if (!rst_src_ni) begin -1- 32 src_level <= 1'b0; ==> 33 end else begin 34 src_level <= src_level ^ src_pulse_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


89 if (!rst_dst_ni) begin -1- 90 dst_level_q <= 1'b0; ==> 91 end else begin 92 dst_level_q <= dst_level; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


Assert Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
DstPulseCheck_A 7271325 2081 0 0
SrcPulseCheck_M 1332231489 2145 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7271325 2081 0 0
T1 509 1 0 0
T2 486 1 0 0
T3 481 0 0 0
T4 666 0 0 0
T6 0 1 0 0
T7 0 1 0 0
T12 747 0 0 0
T13 523 0 0 0
T14 412 0 0 0
T15 423 0 0 0
T16 1038 1 0 0
T17 426 0 0 0
T29 0 1 0 0
T31 0 1 0 0
T57 0 1 0 0
T68 0 1 0 0
T69 0 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 1332231489 2145 0 0
T1 63648 1 0 0
T2 58317 1 0 0
T3 215595 0 0 0
T4 43326 0 0 0
T6 0 1 0 0
T7 0 1 0 0
T12 18956 0 0 0
T13 128352 0 0 0
T14 195910 0 0 0
T15 101494 0 0 0
T16 129820 1 0 0
T17 51227 0 0 0
T29 0 1 0 0
T31 0 1 0 0
T57 0 1 0 0
T68 0 1 0 0
T69 0 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00

30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin 31 1/1 if (!rst_src_ni) begin Tests: T1 T2 T4  32 1/1 src_level <= 1'b0; Tests: T1 T2 T4  33 end else begin 34 1/1 src_level <= src_level ^ src_pulse_i; Tests: T1 T2 T4  35 end 36 end 37 38 39 // source active must come far enough such that the destination domain has time 40 // to create a valid pulse. 41 `ifdef INC_ASSERT 42 //VCS coverage off 43 // pragma coverage off 44 45 // source active flag tracks whether there is an ongoing "toggle" event. 46 // Until this toggle event is accepted by the destination domain (negative edge of 47 // of the pulse output), the source side cannot toggle again. 48 logic effective_rst_n; 49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o; 50 51 logic src_active_flag_d, src_active_flag_q; 52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q; 53 54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin 55 unreachable if (!effective_rst_n) begin 56 unreachable src_active_flag_q <= '0; 57 end else begin 58 unreachable src_active_flag_q <= src_active_flag_d; 59 end 60 end 61 62 //VCS coverage on 63 // pragma coverage on 64 65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni) 66 `endif 67 68 ////////////////////////////////////////////////////////// 69 // synchronize level signal to destination clock domain // 70 ////////////////////////////////////////////////////////// 71 logic dst_level; 72 73 prim_flop_2sync #(.Width(1)) prim_flop_2sync ( 74 // source clock domain 75 .d_i (src_level), 76 // destination clock domain 77 .clk_i (clk_dst_i), 78 .rst_ni (rst_dst_ni), 79 .q_o (dst_level) 80 ); 81 82 //////////////////////////////////////// 83 // convert level signal back to pulse // 84 //////////////////////////////////////// 85 logic dst_level_q; 86 87 // delay dst_level by 1 cycle 88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin 89 1/1 if (!rst_dst_ni) begin Tests: T1 T2 T4  90 1/1 dst_level_q <= 1'b0; Tests: T1 T2 T4  91 end else begin 92 1/1 dst_level_q <= dst_level; Tests: T1 T2 T4  93 end 94 end 95 96 // edge detection 97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level; Tests: T1 T2 T4 

Cond Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT1,T2,T16
10CoveredT1,T2,T16
11CoveredT34,T37,T18

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT1,T2,T16
10CoveredT34,T37,T18
11CoveredT1,T2,T16

Branch Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00


31 if (!rst_src_ni) begin -1- 32 src_level <= 1'b0; ==> 33 end else begin 34 src_level <= src_level ^ src_pulse_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


89 if (!rst_dst_ni) begin -1- 90 dst_level_q <= 1'b0; ==> 91 end else begin 92 dst_level_q <= dst_level; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


Assert Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
DstPulseCheck_A 1332231489 2139 0 0
SrcPulseCheck_M 7271325 2139 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1332231489 2139 0 0
T1 63648 1 0 0
T2 58317 1 0 0
T3 215595 0 0 0
T4 43326 0 0 0
T6 0 1 0 0
T7 0 1 0 0
T12 18956 0 0 0
T13 128352 0 0 0
T14 195910 0 0 0
T15 101494 0 0 0
T16 129820 1 0 0
T17 51227 0 0 0
T29 0 1 0 0
T31 0 1 0 0
T57 0 1 0 0
T68 0 1 0 0
T69 0 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 7271325 2139 0 0
T1 509 1 0 0
T2 486 1 0 0
T3 481 0 0 0
T4 666 0 0 0
T6 0 1 0 0
T7 0 1 0 0
T12 747 0 0 0
T13 523 0 0 0
T14 412 0 0 0
T15 423 0 0 0
T16 1038 1 0 0
T17 426 0 0 0
T29 0 1 0 0
T31 0 1 0 0
T57 0 1 0 0
T68 0 1 0 0
T69 0 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00

30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin 31 1/1 if (!rst_src_ni) begin Tests: T1 T2 T4  32 1/1 src_level <= 1'b0; Tests: T1 T2 T4  33 end else begin 34 1/1 src_level <= src_level ^ src_pulse_i; Tests: T1 T2 T4  35 end 36 end 37 38 39 // source active must come far enough such that the destination domain has time 40 // to create a valid pulse. 41 `ifdef INC_ASSERT 42 //VCS coverage off 43 // pragma coverage off 44 45 // source active flag tracks whether there is an ongoing "toggle" event. 46 // Until this toggle event is accepted by the destination domain (negative edge of 47 // of the pulse output), the source side cannot toggle again. 48 logic effective_rst_n; 49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o; 50 51 logic src_active_flag_d, src_active_flag_q; 52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q; 53 54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin 55 unreachable if (!effective_rst_n) begin 56 unreachable src_active_flag_q <= '0; 57 end else begin 58 unreachable src_active_flag_q <= src_active_flag_d; 59 end 60 end 61 62 //VCS coverage on 63 // pragma coverage on 64 65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni) 66 `endif 67 68 ////////////////////////////////////////////////////////// 69 // synchronize level signal to destination clock domain // 70 ////////////////////////////////////////////////////////// 71 logic dst_level; 72 73 prim_flop_2sync #(.Width(1)) prim_flop_2sync ( 74 // source clock domain 75 .d_i (src_level), 76 // destination clock domain 77 .clk_i (clk_dst_i), 78 .rst_ni (rst_dst_ni), 79 .q_o (dst_level) 80 ); 81 82 //////////////////////////////////////// 83 // convert level signal back to pulse // 84 //////////////////////////////////////// 85 logic dst_level_q; 86 87 // delay dst_level by 1 cycle 88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin 89 1/1 if (!rst_dst_ni) begin Tests: T1 T2 T4  90 1/1 dst_level_q <= 1'b0; Tests: T1 T2 T4  91 end else begin 92 1/1 dst_level_q <= dst_level; Tests: T1 T2 T4  93 end 94 end 95 96 // edge detection 97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level; Tests: T12 T5 T9 

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT12,T5,T9
10CoveredT12,T5,T9
11CoveredT39,T70,T96

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT12,T5,T9
10CoveredT39,T70,T96
11CoveredT12,T5,T9

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00


31 if (!rst_src_ni) begin -1- 32 src_level <= 1'b0; ==> 33 end else begin 34 src_level <= src_level ^ src_pulse_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


89 if (!rst_dst_ni) begin -1- 90 dst_level_q <= 1'b0; ==> 91 end else begin 92 dst_level_q <= dst_level; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
DstPulseCheck_A 7271325 1057 0 0
SrcPulseCheck_M 1332231489 1125 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7271325 1057 0 0
T3 481 0 0 0
T5 0 1 0 0
T9 0 1 0 0
T12 747 1 0 0
T13 523 0 0 0
T14 412 0 0 0
T15 423 0 0 0
T16 1038 0 0 0
T17 426 0 0 0
T21 0 1 0 0
T22 491 0 0 0
T31 448 0 0 0
T39 0 2 0 0
T56 0 1 0 0
T70 0 2 0 0
T71 0 1 0 0
T72 0 1 0 0
T73 0 1 0 0
T74 403 0 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 1332231489 1125 0 0
T3 215595 0 0 0
T5 0 1 0 0
T9 0 1 0 0
T12 18956 1 0 0
T13 128352 0 0 0
T14 195910 0 0 0
T15 101494 0 0 0
T16 129820 0 0 0
T17 51227 0 0 0
T21 0 1 0 0
T22 235908 0 0 0
T31 60611 0 0 0
T39 0 2 0 0
T56 0 1 0 0
T70 0 2 0 0
T71 0 1 0 0
T72 0 1 0 0
T73 0 1 0 0
T74 104693 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00

30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin 31 1/1 if (!rst_src_ni) begin Tests: T1 T2 T4  32 1/1 src_level <= 1'b0; Tests: T1 T2 T4  33 end else begin 34 1/1 src_level <= src_level ^ src_pulse_i; Tests: T1 T2 T4  35 end 36 end 37 38 39 // source active must come far enough such that the destination domain has time 40 // to create a valid pulse. 41 `ifdef INC_ASSERT 42 //VCS coverage off 43 // pragma coverage off 44 45 // source active flag tracks whether there is an ongoing "toggle" event. 46 // Until this toggle event is accepted by the destination domain (negative edge of 47 // of the pulse output), the source side cannot toggle again. 48 logic effective_rst_n; 49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o; 50 51 logic src_active_flag_d, src_active_flag_q; 52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q; 53 54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin 55 unreachable if (!effective_rst_n) begin 56 unreachable src_active_flag_q <= '0; 57 end else begin 58 unreachable src_active_flag_q <= src_active_flag_d; 59 end 60 end 61 62 //VCS coverage on 63 // pragma coverage on 64 65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni) 66 `endif 67 68 ////////////////////////////////////////////////////////// 69 // synchronize level signal to destination clock domain // 70 ////////////////////////////////////////////////////////// 71 logic dst_level; 72 73 prim_flop_2sync #(.Width(1)) prim_flop_2sync ( 74 // source clock domain 75 .d_i (src_level), 76 // destination clock domain 77 .clk_i (clk_dst_i), 78 .rst_ni (rst_dst_ni), 79 .q_o (dst_level) 80 ); 81 82 //////////////////////////////////////// 83 // convert level signal back to pulse // 84 //////////////////////////////////////// 85 logic dst_level_q; 86 87 // delay dst_level by 1 cycle 88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin 89 1/1 if (!rst_dst_ni) begin Tests: T1 T2 T4  90 1/1 dst_level_q <= 1'b0; Tests: T1 T2 T4  91 end else begin 92 1/1 dst_level_q <= dst_level; Tests: T1 T2 T4  93 end 94 end 95 96 // edge detection 97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level; Tests: T1 T2 T4 

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT12,T5,T9
10CoveredT12,T5,T9
11CoveredT39,T70,T96

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT12,T5,T9
10CoveredT39,T70,T96
11CoveredT12,T5,T9

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00


31 if (!rst_src_ni) begin -1- 32 src_level <= 1'b0; ==> 33 end else begin 34 src_level <= src_level ^ src_pulse_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


89 if (!rst_dst_ni) begin -1- 90 dst_level_q <= 1'b0; ==> 91 end else begin 92 dst_level_q <= dst_level; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
DstPulseCheck_A 1332231489 1120 0 0
SrcPulseCheck_M 7271325 1120 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1332231489 1120 0 0
T3 215595 0 0 0
T5 0 1 0 0
T9 0 1 0 0
T12 18956 1 0 0
T13 128352 0 0 0
T14 195910 0 0 0
T15 101494 0 0 0
T16 129820 0 0 0
T17 51227 0 0 0
T21 0 1 0 0
T22 235908 0 0 0
T31 60611 0 0 0
T39 0 2 0 0
T56 0 1 0 0
T70 0 2 0 0
T71 0 1 0 0
T72 0 1 0 0
T73 0 1 0 0
T74 104693 0 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 7271325 1120 0 0
T3 481 0 0 0
T5 0 1 0 0
T9 0 1 0 0
T12 747 1 0 0
T13 523 0 0 0
T14 412 0 0 0
T15 423 0 0 0
T16 1038 0 0 0
T17 426 0 0 0
T21 0 1 0 0
T22 491 0 0 0
T31 448 0 0 0
T39 0 2 0 0
T56 0 1 0 0
T70 0 2 0 0
T71 0 1 0 0
T72 0 1 0 0
T73 0 1 0 0
T74 403 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00

30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin 31 1/1 if (!rst_src_ni) begin Tests: T1 T2 T4  32 1/1 src_level <= 1'b0; Tests: T1 T2 T4  33 end else begin 34 1/1 src_level <= src_level ^ src_pulse_i; Tests: T1 T2 T4  35 end 36 end 37 38 39 // source active must come far enough such that the destination domain has time 40 // to create a valid pulse. 41 `ifdef INC_ASSERT 42 //VCS coverage off 43 // pragma coverage off 44 45 // source active flag tracks whether there is an ongoing "toggle" event. 46 // Until this toggle event is accepted by the destination domain (negative edge of 47 // of the pulse output), the source side cannot toggle again. 48 logic effective_rst_n; 49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o; 50 51 logic src_active_flag_d, src_active_flag_q; 52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q; 53 54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin 55 unreachable if (!effective_rst_n) begin 56 unreachable src_active_flag_q <= '0; 57 end else begin 58 unreachable src_active_flag_q <= src_active_flag_d; 59 end 60 end 61 62 //VCS coverage on 63 // pragma coverage on 64 65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni) 66 `endif 67 68 ////////////////////////////////////////////////////////// 69 // synchronize level signal to destination clock domain // 70 ////////////////////////////////////////////////////////// 71 logic dst_level; 72 73 prim_flop_2sync #(.Width(1)) prim_flop_2sync ( 74 // source clock domain 75 .d_i (src_level), 76 // destination clock domain 77 .clk_i (clk_dst_i), 78 .rst_ni (rst_dst_ni), 79 .q_o (dst_level) 80 ); 81 82 //////////////////////////////////////// 83 // convert level signal back to pulse // 84 //////////////////////////////////////// 85 logic dst_level_q; 86 87 // delay dst_level by 1 cycle 88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin 89 1/1 if (!rst_dst_ni) begin Tests: T1 T2 T4  90 1/1 dst_level_q <= 1'b0; Tests: T1 T2 T4  91 end else begin 92 1/1 dst_level_q <= dst_level; Tests: T1 T2 T4  93 end 94 end 95 96 // edge detection 97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level; Tests: T12 T5 T9 

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT12,T5,T9
10CoveredT12,T5,T9
11CoveredT39,T70,T96

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT12,T5,T9
10CoveredT39,T70,T96
11CoveredT12,T5,T9

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00


31 if (!rst_src_ni) begin -1- 32 src_level <= 1'b0; ==> 33 end else begin 34 src_level <= src_level ^ src_pulse_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


89 if (!rst_dst_ni) begin -1- 90 dst_level_q <= 1'b0; ==> 91 end else begin 92 dst_level_q <= dst_level; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


Assert Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
DstPulseCheck_A 7271325 1055 0 0
SrcPulseCheck_M 1332231489 1124 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7271325 1055 0 0
T3 481 0 0 0
T5 0 1 0 0
T9 0 1 0 0
T12 747 1 0 0
T13 523 0 0 0
T14 412 0 0 0
T15 423 0 0 0
T16 1038 0 0 0
T17 426 0 0 0
T21 0 1 0 0
T22 491 0 0 0
T31 448 0 0 0
T39 0 2 0 0
T56 0 1 0 0
T70 0 2 0 0
T71 0 1 0 0
T72 0 1 0 0
T73 0 1 0 0
T74 403 0 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 1332231489 1124 0 0
T3 215595 0 0 0
T5 0 1 0 0
T9 0 1 0 0
T12 18956 1 0 0
T13 128352 0 0 0
T14 195910 0 0 0
T15 101494 0 0 0
T16 129820 0 0 0
T17 51227 0 0 0
T21 0 1 0 0
T22 235908 0 0 0
T31 60611 0 0 0
T39 0 2 0 0
T56 0 1 0 0
T70 0 2 0 0
T71 0 1 0 0
T72 0 1 0 0
T73 0 1 0 0
T74 104693 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00

30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin 31 1/1 if (!rst_src_ni) begin Tests: T1 T2 T4  32 1/1 src_level <= 1'b0; Tests: T1 T2 T4  33 end else begin 34 1/1 src_level <= src_level ^ src_pulse_i; Tests: T1 T2 T4  35 end 36 end 37 38 39 // source active must come far enough such that the destination domain has time 40 // to create a valid pulse. 41 `ifdef INC_ASSERT 42 //VCS coverage off 43 // pragma coverage off 44 45 // source active flag tracks whether there is an ongoing "toggle" event. 46 // Until this toggle event is accepted by the destination domain (negative edge of 47 // of the pulse output), the source side cannot toggle again. 48 logic effective_rst_n; 49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o; 50 51 logic src_active_flag_d, src_active_flag_q; 52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q; 53 54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin 55 unreachable if (!effective_rst_n) begin 56 unreachable src_active_flag_q <= '0; 57 end else begin 58 unreachable src_active_flag_q <= src_active_flag_d; 59 end 60 end 61 62 //VCS coverage on 63 // pragma coverage on 64 65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni) 66 `endif 67 68 ////////////////////////////////////////////////////////// 69 // synchronize level signal to destination clock domain // 70 ////////////////////////////////////////////////////////// 71 logic dst_level; 72 73 prim_flop_2sync #(.Width(1)) prim_flop_2sync ( 74 // source clock domain 75 .d_i (src_level), 76 // destination clock domain 77 .clk_i (clk_dst_i), 78 .rst_ni (rst_dst_ni), 79 .q_o (dst_level) 80 ); 81 82 //////////////////////////////////////// 83 // convert level signal back to pulse // 84 //////////////////////////////////////// 85 logic dst_level_q; 86 87 // delay dst_level by 1 cycle 88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin 89 1/1 if (!rst_dst_ni) begin Tests: T1 T2 T4  90 1/1 dst_level_q <= 1'b0; Tests: T1 T2 T4  91 end else begin 92 1/1 dst_level_q <= dst_level; Tests: T1 T2 T4  93 end 94 end 95 96 // edge detection 97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level; Tests: T1 T2 T4 

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT12,T5,T9
10CoveredT12,T5,T9
11CoveredT39,T70,T96

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT12,T5,T9
10CoveredT39,T70,T96
11CoveredT12,T5,T9

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00


31 if (!rst_src_ni) begin -1- 32 src_level <= 1'b0; ==> 33 end else begin 34 src_level <= src_level ^ src_pulse_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


89 if (!rst_dst_ni) begin -1- 90 dst_level_q <= 1'b0; ==> 91 end else begin 92 dst_level_q <= dst_level; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


Assert Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
DstPulseCheck_A 1332231489 1117 0 0
SrcPulseCheck_M 7271325 1117 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1332231489 1117 0 0
T3 215595 0 0 0
T5 0 1 0 0
T9 0 1 0 0
T12 18956 1 0 0
T13 128352 0 0 0
T14 195910 0 0 0
T15 101494 0 0 0
T16 129820 0 0 0
T17 51227 0 0 0
T21 0 1 0 0
T22 235908 0 0 0
T31 60611 0 0 0
T39 0 2 0 0
T56 0 1 0 0
T70 0 2 0 0
T71 0 1 0 0
T72 0 1 0 0
T73 0 1 0 0
T74 104693 0 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 7271325 1117 0 0
T3 481 0 0 0
T5 0 1 0 0
T9 0 1 0 0
T12 747 1 0 0
T13 523 0 0 0
T14 412 0 0 0
T15 423 0 0 0
T16 1038 0 0 0
T17 426 0 0 0
T21 0 1 0 0
T22 491 0 0 0
T31 448 0 0 0
T39 0 2 0 0
T56 0 1 0 0
T70 0 2 0 0
T71 0 1 0 0
T72 0 1 0 0
T73 0 1 0 0
T74 403 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00

30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin 31 1/1 if (!rst_src_ni) begin Tests: T1 T2 T4  32 1/1 src_level <= 1'b0; Tests: T1 T2 T4  33 end else begin 34 1/1 src_level <= src_level ^ src_pulse_i; Tests: T1 T2 T4  35 end 36 end 37 38 39 // source active must come far enough such that the destination domain has time 40 // to create a valid pulse. 41 `ifdef INC_ASSERT 42 //VCS coverage off 43 // pragma coverage off 44 45 // source active flag tracks whether there is an ongoing "toggle" event. 46 // Until this toggle event is accepted by the destination domain (negative edge of 47 // of the pulse output), the source side cannot toggle again. 48 logic effective_rst_n; 49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o; 50 51 logic src_active_flag_d, src_active_flag_q; 52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q; 53 54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin 55 unreachable if (!effective_rst_n) begin 56 unreachable src_active_flag_q <= '0; 57 end else begin 58 unreachable src_active_flag_q <= src_active_flag_d; 59 end 60 end 61 62 //VCS coverage on 63 // pragma coverage on 64 65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni) 66 `endif 67 68 ////////////////////////////////////////////////////////// 69 // synchronize level signal to destination clock domain // 70 ////////////////////////////////////////////////////////// 71 logic dst_level; 72 73 prim_flop_2sync #(.Width(1)) prim_flop_2sync ( 74 // source clock domain 75 .d_i (src_level), 76 // destination clock domain 77 .clk_i (clk_dst_i), 78 .rst_ni (rst_dst_ni), 79 .q_o (dst_level) 80 ); 81 82 //////////////////////////////////////// 83 // convert level signal back to pulse // 84 //////////////////////////////////////// 85 logic dst_level_q; 86 87 // delay dst_level by 1 cycle 88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin 89 1/1 if (!rst_dst_ni) begin Tests: T1 T2 T4  90 1/1 dst_level_q <= 1'b0; Tests: T1 T2 T4  91 end else begin 92 1/1 dst_level_q <= dst_level; Tests: T1 T2 T4  93 end 94 end 95 96 // edge detection 97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level; Tests: T12 T5 T9 

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT12,T5,T9
10CoveredT12,T5,T9
11CoveredT39,T70,T96

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT12,T5,T9
10CoveredT39,T70,T96
11CoveredT12,T5,T9

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00


31 if (!rst_src_ni) begin -1- 32 src_level <= 1'b0; ==> 33 end else begin 34 src_level <= src_level ^ src_pulse_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


89 if (!rst_dst_ni) begin -1- 90 dst_level_q <= 1'b0; ==> 91 end else begin 92 dst_level_q <= dst_level; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


Assert Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
DstPulseCheck_A 7271325 1050 0 0
SrcPulseCheck_M 1332231489 1122 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7271325 1050 0 0
T3 481 0 0 0
T5 0 1 0 0
T9 0 1 0 0
T12 747 1 0 0
T13 523 0 0 0
T14 412 0 0 0
T15 423 0 0 0
T16 1038 0 0 0
T17 426 0 0 0
T21 0 1 0 0
T22 491 0 0 0
T31 448 0 0 0
T39 0 2 0 0
T56 0 1 0 0
T70 0 2 0 0
T71 0 1 0 0
T72 0 1 0 0
T73 0 1 0 0
T74 403 0 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 1332231489 1122 0 0
T3 215595 0 0 0
T5 0 1 0 0
T9 0 1 0 0
T12 18956 1 0 0
T13 128352 0 0 0
T14 195910 0 0 0
T15 101494 0 0 0
T16 129820 0 0 0
T17 51227 0 0 0
T21 0 1 0 0
T22 235908 0 0 0
T31 60611 0 0 0
T39 0 2 0 0
T56 0 1 0 0
T70 0 2 0 0
T71 0 1 0 0
T72 0 1 0 0
T73 0 1 0 0
T74 104693 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00

30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin 31 1/1 if (!rst_src_ni) begin Tests: T1 T2 T4  32 1/1 src_level <= 1'b0; Tests: T1 T2 T4  33 end else begin 34 1/1 src_level <= src_level ^ src_pulse_i; Tests: T1 T2 T4  35 end 36 end 37 38 39 // source active must come far enough such that the destination domain has time 40 // to create a valid pulse. 41 `ifdef INC_ASSERT 42 //VCS coverage off 43 // pragma coverage off 44 45 // source active flag tracks whether there is an ongoing "toggle" event. 46 // Until this toggle event is accepted by the destination domain (negative edge of 47 // of the pulse output), the source side cannot toggle again. 48 logic effective_rst_n; 49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o; 50 51 logic src_active_flag_d, src_active_flag_q; 52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q; 53 54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin 55 unreachable if (!effective_rst_n) begin 56 unreachable src_active_flag_q <= '0; 57 end else begin 58 unreachable src_active_flag_q <= src_active_flag_d; 59 end 60 end 61 62 //VCS coverage on 63 // pragma coverage on 64 65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni) 66 `endif 67 68 ////////////////////////////////////////////////////////// 69 // synchronize level signal to destination clock domain // 70 ////////////////////////////////////////////////////////// 71 logic dst_level; 72 73 prim_flop_2sync #(.Width(1)) prim_flop_2sync ( 74 // source clock domain 75 .d_i (src_level), 76 // destination clock domain 77 .clk_i (clk_dst_i), 78 .rst_ni (rst_dst_ni), 79 .q_o (dst_level) 80 ); 81 82 //////////////////////////////////////// 83 // convert level signal back to pulse // 84 //////////////////////////////////////// 85 logic dst_level_q; 86 87 // delay dst_level by 1 cycle 88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin 89 1/1 if (!rst_dst_ni) begin Tests: T1 T2 T4  90 1/1 dst_level_q <= 1'b0; Tests: T1 T2 T4  91 end else begin 92 1/1 dst_level_q <= dst_level; Tests: T1 T2 T4  93 end 94 end 95 96 // edge detection 97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level; Tests: T1 T2 T4 

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT12,T5,T9
10CoveredT12,T5,T9
11CoveredT39,T70,T96

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT12,T5,T9
10CoveredT39,T70,T96
11CoveredT12,T5,T9

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00


31 if (!rst_src_ni) begin -1- 32 src_level <= 1'b0; ==> 33 end else begin 34 src_level <= src_level ^ src_pulse_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


89 if (!rst_dst_ni) begin -1- 90 dst_level_q <= 1'b0; ==> 91 end else begin 92 dst_level_q <= dst_level; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


Assert Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
DstPulseCheck_A 1332231489 1116 0 0
SrcPulseCheck_M 7271325 1116 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1332231489 1116 0 0
T3 215595 0 0 0
T5 0 1 0 0
T9 0 1 0 0
T12 18956 1 0 0
T13 128352 0 0 0
T14 195910 0 0 0
T15 101494 0 0 0
T16 129820 0 0 0
T17 51227 0 0 0
T21 0 1 0 0
T22 235908 0 0 0
T31 60611 0 0 0
T39 0 2 0 0
T56 0 1 0 0
T70 0 2 0 0
T71 0 1 0 0
T72 0 1 0 0
T73 0 1 0 0
T74 104693 0 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 7271325 1116 0 0
T3 481 0 0 0
T5 0 1 0 0
T9 0 1 0 0
T12 747 1 0 0
T13 523 0 0 0
T14 412 0 0 0
T15 423 0 0 0
T16 1038 0 0 0
T17 426 0 0 0
T21 0 1 0 0
T22 491 0 0 0
T31 448 0 0 0
T39 0 2 0 0
T56 0 1 0 0
T70 0 2 0 0
T71 0 1 0 0
T72 0 1 0 0
T73 0 1 0 0
T74 403 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00

30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin 31 1/1 if (!rst_src_ni) begin Tests: T1 T2 T4  32 1/1 src_level <= 1'b0; Tests: T1 T2 T4  33 end else begin 34 1/1 src_level <= src_level ^ src_pulse_i; Tests: T1 T2 T4  35 end 36 end 37 38 39 // source active must come far enough such that the destination domain has time 40 // to create a valid pulse. 41 `ifdef INC_ASSERT 42 //VCS coverage off 43 // pragma coverage off 44 45 // source active flag tracks whether there is an ongoing "toggle" event. 46 // Until this toggle event is accepted by the destination domain (negative edge of 47 // of the pulse output), the source side cannot toggle again. 48 logic effective_rst_n; 49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o; 50 51 logic src_active_flag_d, src_active_flag_q; 52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q; 53 54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin 55 unreachable if (!effective_rst_n) begin 56 unreachable src_active_flag_q <= '0; 57 end else begin 58 unreachable src_active_flag_q <= src_active_flag_d; 59 end 60 end 61 62 //VCS coverage on 63 // pragma coverage on 64 65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni) 66 `endif 67 68 ////////////////////////////////////////////////////////// 69 // synchronize level signal to destination clock domain // 70 ////////////////////////////////////////////////////////// 71 logic dst_level; 72 73 prim_flop_2sync #(.Width(1)) prim_flop_2sync ( 74 // source clock domain 75 .d_i (src_level), 76 // destination clock domain 77 .clk_i (clk_dst_i), 78 .rst_ni (rst_dst_ni), 79 .q_o (dst_level) 80 ); 81 82 //////////////////////////////////////// 83 // convert level signal back to pulse // 84 //////////////////////////////////////// 85 logic dst_level_q; 86 87 // delay dst_level by 1 cycle 88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin 89 1/1 if (!rst_dst_ni) begin Tests: T1 T2 T4  90 1/1 dst_level_q <= 1'b0; Tests: T1 T2 T4  91 end else begin 92 1/1 dst_level_q <= dst_level; Tests: T1 T2 T4  93 end 94 end 95 96 // edge detection 97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level; Tests: T5 T9 T21 

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT5,T9,T21
10CoveredT5,T9,T21
11CoveredT5,T9,T21

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT5,T9,T21
10CoveredT5,T9,T21
11CoveredT5,T9,T21

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00


31 if (!rst_src_ni) begin -1- 32 src_level <= 1'b0; ==> 33 end else begin 34 src_level <= src_level ^ src_pulse_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


89 if (!rst_dst_ni) begin -1- 90 dst_level_q <= 1'b0; ==> 91 end else begin 92 dst_level_q <= dst_level; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
DstPulseCheck_A 7271325 1067 0 0
SrcPulseCheck_M 1332231489 1134 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7271325 1067 0 0
T5 689 2 0 0
T6 7579 0 0 0
T8 627 0 0 0
T9 0 2 0 0
T21 0 4 0 0
T26 501 0 0 0
T27 645 0 0 0
T29 456 0 0 0
T39 0 2 0 0
T54 0 4 0 0
T55 0 2 0 0
T56 0 4 0 0
T65 522 0 0 0
T66 406 0 0 0
T67 424 0 0 0
T68 818 0 0 0
T70 0 2 0 0
T96 0 2 0 0
T97 0 2 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 1332231489 1134 0 0
T5 54551 2 0 0
T6 568425 0 0 0
T8 240611 0 0 0
T9 0 2 0 0
T21 0 4 0 0
T26 250832 0 0 0
T27 309902 0 0 0
T29 52546 0 0 0
T39 0 2 0 0
T54 0 4 0 0
T55 0 2 0 0
T56 0 4 0 0
T65 251010 0 0 0
T66 48764 0 0 0
T67 53084 0 0 0
T68 393069 0 0 0
T70 0 2 0 0
T96 0 2 0 0
T97 0 2 0 0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00

30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin 31 1/1 if (!rst_src_ni) begin Tests: T1 T2 T4  32 1/1 src_level <= 1'b0; Tests: T1 T2 T4  33 end else begin 34 1/1 src_level <= src_level ^ src_pulse_i; Tests: T1 T2 T4  35 end 36 end 37 38 39 // source active must come far enough such that the destination domain has time 40 // to create a valid pulse. 41 `ifdef INC_ASSERT 42 //VCS coverage off 43 // pragma coverage off 44 45 // source active flag tracks whether there is an ongoing "toggle" event. 46 // Until this toggle event is accepted by the destination domain (negative edge of 47 // of the pulse output), the source side cannot toggle again. 48 logic effective_rst_n; 49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o; 50 51 logic src_active_flag_d, src_active_flag_q; 52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q; 53 54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin 55 unreachable if (!effective_rst_n) begin 56 unreachable src_active_flag_q <= '0; 57 end else begin 58 unreachable src_active_flag_q <= src_active_flag_d; 59 end 60 end 61 62 //VCS coverage on 63 // pragma coverage on 64 65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni) 66 `endif 67 68 ////////////////////////////////////////////////////////// 69 // synchronize level signal to destination clock domain // 70 ////////////////////////////////////////////////////////// 71 logic dst_level; 72 73 prim_flop_2sync #(.Width(1)) prim_flop_2sync ( 74 // source clock domain 75 .d_i (src_level), 76 // destination clock domain 77 .clk_i (clk_dst_i), 78 .rst_ni (rst_dst_ni), 79 .q_o (dst_level) 80 ); 81 82 //////////////////////////////////////// 83 // convert level signal back to pulse // 84 //////////////////////////////////////// 85 logic dst_level_q; 86 87 // delay dst_level by 1 cycle 88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin 89 1/1 if (!rst_dst_ni) begin Tests: T1 T2 T4  90 1/1 dst_level_q <= 1'b0; Tests: T1 T2 T4  91 end else begin 92 1/1 dst_level_q <= dst_level; Tests: T1 T2 T4  93 end 94 end 95 96 // edge detection 97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level; Tests: T1 T2 T4 

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT5,T9,T21
10CoveredT5,T9,T21
11CoveredT5,T9,T21

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT5,T9,T21
10CoveredT5,T9,T21
11CoveredT5,T9,T21

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00


31 if (!rst_src_ni) begin -1- 32 src_level <= 1'b0; ==> 33 end else begin 34 src_level <= src_level ^ src_pulse_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


89 if (!rst_dst_ni) begin -1- 90 dst_level_q <= 1'b0; ==> 91 end else begin 92 dst_level_q <= dst_level; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
DstPulseCheck_A 1332231489 1126 0 0
SrcPulseCheck_M 7271325 1126 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1332231489 1126 0 0
T5 54551 2 0 0
T6 568425 0 0 0
T8 240611 0 0 0
T9 0 2 0 0
T21 0 4 0 0
T26 250832 0 0 0
T27 309902 0 0 0
T29 52546 0 0 0
T39 0 2 0 0
T54 0 4 0 0
T55 0 2 0 0
T56 0 4 0 0
T65 251010 0 0 0
T66 48764 0 0 0
T67 53084 0 0 0
T68 393069 0 0 0
T70 0 2 0 0
T96 0 2 0 0
T97 0 2 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 7271325 1126 0 0
T5 689 2 0 0
T6 7579 0 0 0
T8 627 0 0 0
T9 0 2 0 0
T21 0 4 0 0
T26 501 0 0 0
T27 645 0 0 0
T29 456 0 0 0
T39 0 2 0 0
T54 0 4 0 0
T55 0 2 0 0
T56 0 4 0 0
T65 522 0 0 0
T66 406 0 0 0
T67 424 0 0 0
T68 818 0 0 0
T70 0 2 0 0
T96 0 2 0 0
T97 0 2 0 0

Line Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00

30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin 31 1/1 if (!rst_src_ni) begin Tests: T1 T2 T4  32 1/1 src_level <= 1'b0; Tests: T1 T2 T4  33 end else begin 34 1/1 src_level <= src_level ^ src_pulse_i; Tests: T1 T2 T4  35 end 36 end 37 38 39 // source active must come far enough such that the destination domain has time 40 // to create a valid pulse. 41 `ifdef INC_ASSERT 42 //VCS coverage off 43 // pragma coverage off 44 45 // source active flag tracks whether there is an ongoing "toggle" event. 46 // Until this toggle event is accepted by the destination domain (negative edge of 47 // of the pulse output), the source side cannot toggle again. 48 logic effective_rst_n; 49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o; 50 51 logic src_active_flag_d, src_active_flag_q; 52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q; 53 54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin 55 unreachable if (!effective_rst_n) begin 56 unreachable src_active_flag_q <= '0; 57 end else begin 58 unreachable src_active_flag_q <= src_active_flag_d; 59 end 60 end 61 62 //VCS coverage on 63 // pragma coverage on 64 65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni) 66 `endif 67 68 ////////////////////////////////////////////////////////// 69 // synchronize level signal to destination clock domain // 70 ////////////////////////////////////////////////////////// 71 logic dst_level; 72 73 prim_flop_2sync #(.Width(1)) prim_flop_2sync ( 74 // source clock domain 75 .d_i (src_level), 76 // destination clock domain 77 .clk_i (clk_dst_i), 78 .rst_ni (rst_dst_ni), 79 .q_o (dst_level) 80 ); 81 82 //////////////////////////////////////// 83 // convert level signal back to pulse // 84 //////////////////////////////////////// 85 logic dst_level_q; 86 87 // delay dst_level by 1 cycle 88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin 89 1/1 if (!rst_dst_ni) begin Tests: T1 T2 T4  90 1/1 dst_level_q <= 1'b0; Tests: T1 T2 T4  91 end else begin 92 1/1 dst_level_q <= dst_level; Tests: T1 T2 T4  93 end 94 end 95 96 // edge detection 97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level; Tests: T5 T6 T9 

Cond Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT5,T6,T9
10CoveredT5,T6,T9
11CoveredT6,T162,T165

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT5,T6,T9
10CoveredT6,T162,T165
11CoveredT5,T6,T9

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00


31 if (!rst_src_ni) begin -1- 32 src_level <= 1'b0; ==> 33 end else begin 34 src_level <= src_level ^ src_pulse_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


89 if (!rst_dst_ni) begin -1- 90 dst_level_q <= 1'b0; ==> 91 end else begin 92 dst_level_q <= dst_level; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


Assert Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
DstPulseCheck_A 7271325 1059 0 0
SrcPulseCheck_M 1332231489 1129 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7271325 1059 0 0
T5 689 1 0 0
T6 7579 8 0 0
T8 627 0 0 0
T9 0 1 0 0
T11 0 11 0 0
T26 501 0 0 0
T27 645 0 0 0
T29 456 0 0 0
T30 0 1 0 0
T32 0 4 0 0
T39 0 1 0 0
T40 0 8 0 0
T42 0 3 0 0
T65 522 0 0 0
T66 406 0 0 0
T67 424 0 0 0
T68 818 0 0 0
T70 0 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 1332231489 1129 0 0
T5 54551 1 0 0
T6 568425 8 0 0
T8 240611 0 0 0
T9 0 1 0 0
T11 0 11 0 0
T21 0 1 0 0
T26 250832 0 0 0
T27 309902 0 0 0
T29 52546 0 0 0
T30 0 1 0 0
T32 0 4 0 0
T39 0 1 0 0
T40 0 8 0 0
T65 251010 0 0 0
T66 48764 0 0 0
T67 53084 0 0 0
T68 393069 0 0 0
T70 0 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00

30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin 31 1/1 if (!rst_src_ni) begin Tests: T1 T2 T4  32 1/1 src_level <= 1'b0; Tests: T1 T2 T4  33 end else begin 34 1/1 src_level <= src_level ^ src_pulse_i; Tests: T1 T2 T4  35 end 36 end 37 38 39 // source active must come far enough such that the destination domain has time 40 // to create a valid pulse. 41 `ifdef INC_ASSERT 42 //VCS coverage off 43 // pragma coverage off 44 45 // source active flag tracks whether there is an ongoing "toggle" event. 46 // Until this toggle event is accepted by the destination domain (negative edge of 47 // of the pulse output), the source side cannot toggle again. 48 logic effective_rst_n; 49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o; 50 51 logic src_active_flag_d, src_active_flag_q; 52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q; 53 54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin 55 unreachable if (!effective_rst_n) begin 56 unreachable src_active_flag_q <= '0; 57 end else begin 58 unreachable src_active_flag_q <= src_active_flag_d; 59 end 60 end 61 62 //VCS coverage on 63 // pragma coverage on 64 65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni) 66 `endif 67 68 ////////////////////////////////////////////////////////// 69 // synchronize level signal to destination clock domain // 70 ////////////////////////////////////////////////////////// 71 logic dst_level; 72 73 prim_flop_2sync #(.Width(1)) prim_flop_2sync ( 74 // source clock domain 75 .d_i (src_level), 76 // destination clock domain 77 .clk_i (clk_dst_i), 78 .rst_ni (rst_dst_ni), 79 .q_o (dst_level) 80 ); 81 82 //////////////////////////////////////// 83 // convert level signal back to pulse // 84 //////////////////////////////////////// 85 logic dst_level_q; 86 87 // delay dst_level by 1 cycle 88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin 89 1/1 if (!rst_dst_ni) begin Tests: T1 T2 T4  90 1/1 dst_level_q <= 1'b0; Tests: T1 T2 T4  91 end else begin 92 1/1 dst_level_q <= dst_level; Tests: T1 T2 T4  93 end 94 end 95 96 // edge detection 97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level; Tests: T22 T23 T24 

Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT22,T23,T24
10CoveredT22,T23,T24
11CoveredT22,T23,T24

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT22,T23,T24
10CoveredT22,T23,T24
11CoveredT22,T23,T24

Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00


31 if (!rst_src_ni) begin -1- 32 src_level <= 1'b0; ==> 33 end else begin 34 src_level <= src_level ^ src_pulse_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


89 if (!rst_dst_ni) begin -1- 90 dst_level_q <= 1'b0; ==> 91 end else begin 92 dst_level_q <= dst_level; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


Assert Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
DstPulseCheck_A 7271325 3141 0 0
SrcPulseCheck_M 1332231489 3211 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7271325 3141 0 0
T5 689 0 0 0
T7 506 0 0 0
T22 491 20 0 0
T23 497 20 0 0
T24 0 20 0 0
T25 502 0 0 0
T26 501 0 0 0
T27 645 0 0 0
T31 448 0 0 0
T54 0 20 0 0
T74 403 0 0 0
T75 0 20 0 0
T76 0 20 0 0
T77 0 20 0 0
T78 0 20 0 0
T79 0 20 0 0
T80 0 20 0 0
T81 405 0 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 1332231489 3211 0 0
T5 54551 0 0 0
T7 60814 0 0 0
T22 235908 20 0 0
T23 67247 20 0 0
T24 0 20 0 0
T25 248822 0 0 0
T26 250832 0 0 0
T27 309902 0 0 0
T31 60611 0 0 0
T54 0 20 0 0
T74 104693 0 0 0
T75 0 20 0 0
T76 0 20 0 0
T77 0 20 0 0
T78 0 20 0 0
T79 0 20 0 0
T80 0 20 0 0
T81 101285 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00

30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin 31 1/1 if (!rst_src_ni) begin Tests: T1 T2 T4  32 1/1 src_level <= 1'b0; Tests: T1 T2 T4  33 end else begin 34 1/1 src_level <= src_level ^ src_pulse_i; Tests: T1 T2 T4  35 end 36 end 37 38 39 // source active must come far enough such that the destination domain has time 40 // to create a valid pulse. 41 `ifdef INC_ASSERT 42 //VCS coverage off 43 // pragma coverage off 44 45 // source active flag tracks whether there is an ongoing "toggle" event. 46 // Until this toggle event is accepted by the destination domain (negative edge of 47 // of the pulse output), the source side cannot toggle again. 48 logic effective_rst_n; 49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o; 50 51 logic src_active_flag_d, src_active_flag_q; 52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q; 53 54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin 55 unreachable if (!effective_rst_n) begin 56 unreachable src_active_flag_q <= '0; 57 end else begin 58 unreachable src_active_flag_q <= src_active_flag_d; 59 end 60 end 61 62 //VCS coverage on 63 // pragma coverage on 64 65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni) 66 `endif 67 68 ////////////////////////////////////////////////////////// 69 // synchronize level signal to destination clock domain // 70 ////////////////////////////////////////////////////////// 71 logic dst_level; 72 73 prim_flop_2sync #(.Width(1)) prim_flop_2sync ( 74 // source clock domain 75 .d_i (src_level), 76 // destination clock domain 77 .clk_i (clk_dst_i), 78 .rst_ni (rst_dst_ni), 79 .q_o (dst_level) 80 ); 81 82 //////////////////////////////////////// 83 // convert level signal back to pulse // 84 //////////////////////////////////////// 85 logic dst_level_q; 86 87 // delay dst_level by 1 cycle 88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin 89 1/1 if (!rst_dst_ni) begin Tests: T1 T2 T4  90 1/1 dst_level_q <= 1'b0; Tests: T1 T2 T4  91 end else begin 92 1/1 dst_level_q <= dst_level; Tests: T1 T2 T4  93 end 94 end 95 96 // edge detection 97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level; Tests: T1 T2 T4 

Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT22,T23,T24
10CoveredT22,T23,T24
11CoveredT22,T23,T24

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT22,T23,T24
10CoveredT22,T23,T24
11CoveredT22,T23,T24

Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00


31 if (!rst_src_ni) begin -1- 32 src_level <= 1'b0; ==> 33 end else begin 34 src_level <= src_level ^ src_pulse_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


89 if (!rst_dst_ni) begin -1- 90 dst_level_q <= 1'b0; ==> 91 end else begin 92 dst_level_q <= dst_level; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


Assert Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
DstPulseCheck_A 1332231489 3206 0 0
SrcPulseCheck_M 7271325 3206 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1332231489 3206 0 0
T5 54551 0 0 0
T7 60814 0 0 0
T22 235908 20 0 0
T23 67247 20 0 0
T24 0 20 0 0
T25 248822 0 0 0
T26 250832 0 0 0
T27 309902 0 0 0
T31 60611 0 0 0
T54 0 20 0 0
T74 104693 0 0 0
T75 0 20 0 0
T76 0 20 0 0
T77 0 20 0 0
T78 0 20 0 0
T79 0 20 0 0
T80 0 20 0 0
T81 101285 0 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 7271325 3206 0 0
T5 689 0 0 0
T7 506 0 0 0
T22 491 20 0 0
T23 497 20 0 0
T24 0 20 0 0
T25 502 0 0 0
T26 501 0 0 0
T27 645 0 0 0
T31 448 0 0 0
T54 0 20 0 0
T74 403 0 0 0
T75 0 20 0 0
T76 0 20 0 0
T77 0 20 0 0
T78 0 20 0 0
T79 0 20 0 0
T80 0 20 0 0
T81 405 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00

30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin 31 1/1 if (!rst_src_ni) begin Tests: T1 T2 T4  32 1/1 src_level <= 1'b0; Tests: T1 T2 T4  33 end else begin 34 1/1 src_level <= src_level ^ src_pulse_i; Tests: T1 T2 T4  35 end 36 end 37 38 39 // source active must come far enough such that the destination domain has time 40 // to create a valid pulse. 41 `ifdef INC_ASSERT 42 //VCS coverage off 43 // pragma coverage off 44 45 // source active flag tracks whether there is an ongoing "toggle" event. 46 // Until this toggle event is accepted by the destination domain (negative edge of 47 // of the pulse output), the source side cannot toggle again. 48 logic effective_rst_n; 49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o; 50 51 logic src_active_flag_d, src_active_flag_q; 52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q; 53 54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin 55 unreachable if (!effective_rst_n) begin 56 unreachable src_active_flag_q <= '0; 57 end else begin 58 unreachable src_active_flag_q <= src_active_flag_d; 59 end 60 end 61 62 //VCS coverage on 63 // pragma coverage on 64 65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni) 66 `endif 67 68 ////////////////////////////////////////////////////////// 69 // synchronize level signal to destination clock domain // 70 ////////////////////////////////////////////////////////// 71 logic dst_level; 72 73 prim_flop_2sync #(.Width(1)) prim_flop_2sync ( 74 // source clock domain 75 .d_i (src_level), 76 // destination clock domain 77 .clk_i (clk_dst_i), 78 .rst_ni (rst_dst_ni), 79 .q_o (dst_level) 80 ); 81 82 //////////////////////////////////////// 83 // convert level signal back to pulse // 84 //////////////////////////////////////// 85 logic dst_level_q; 86 87 // delay dst_level by 1 cycle 88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin 89 1/1 if (!rst_dst_ni) begin Tests: T1 T2 T4  90 1/1 dst_level_q <= 1'b0; Tests: T1 T2 T4  91 end else begin 92 1/1 dst_level_q <= dst_level; Tests: T1 T2 T4  93 end 94 end 95 96 // edge detection 97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level; Tests: T13 T22 T23 

Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT13,T22,T23
10CoveredT13,T22,T23
11CoveredT13,T25,T26

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT13,T22,T23
10CoveredT13,T25,T26
11CoveredT13,T22,T23

Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00


31 if (!rst_src_ni) begin -1- 32 src_level <= 1'b0; ==> 33 end else begin 34 src_level <= src_level ^ src_pulse_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


89 if (!rst_dst_ni) begin -1- 90 dst_level_q <= 1'b0; ==> 91 end else begin 92 dst_level_q <= dst_level; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


Assert Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
DstPulseCheck_A 7271325 6155 0 0
SrcPulseCheck_M 1332231489 6225 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7271325 6155 0 0
T3 481 0 0 0
T13 523 20 0 0
T14 412 0 0 0
T15 423 0 0 0
T16 1038 0 0 0
T17 426 0 0 0
T22 491 1 0 0
T23 497 1 0 0
T24 0 1 0 0
T25 0 20 0 0
T26 0 20 0 0
T31 448 0 0 0
T51 0 20 0 0
T65 0 20 0 0
T74 403 0 0 0
T82 0 20 0 0
T83 0 20 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 1332231489 6225 0 0
T3 215595 0 0 0
T13 128352 20 0 0
T14 195910 0 0 0
T15 101494 0 0 0
T16 129820 0 0 0
T17 51227 0 0 0
T22 235908 1 0 0
T23 67247 1 0 0
T24 0 1 0 0
T25 0 20 0 0
T26 0 20 0 0
T31 60611 0 0 0
T51 0 20 0 0
T65 0 20 0 0
T74 104693 0 0 0
T82 0 20 0 0
T83 0 20 0 0

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00

30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin 31 1/1 if (!rst_src_ni) begin Tests: T1 T2 T4  32 1/1 src_level <= 1'b0; Tests: T1 T2 T4  33 end else begin 34 1/1 src_level <= src_level ^ src_pulse_i; Tests: T1 T2 T4  35 end 36 end 37 38 39 // source active must come far enough such that the destination domain has time 40 // to create a valid pulse. 41 `ifdef INC_ASSERT 42 //VCS coverage off 43 // pragma coverage off 44 45 // source active flag tracks whether there is an ongoing "toggle" event. 46 // Until this toggle event is accepted by the destination domain (negative edge of 47 // of the pulse output), the source side cannot toggle again. 48 logic effective_rst_n; 49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o; 50 51 logic src_active_flag_d, src_active_flag_q; 52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q; 53 54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin 55 unreachable if (!effective_rst_n) begin 56 unreachable src_active_flag_q <= '0; 57 end else begin 58 unreachable src_active_flag_q <= src_active_flag_d; 59 end 60 end 61 62 //VCS coverage on 63 // pragma coverage on 64 65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni) 66 `endif 67 68 ////////////////////////////////////////////////////////// 69 // synchronize level signal to destination clock domain // 70 ////////////////////////////////////////////////////////// 71 logic dst_level; 72 73 prim_flop_2sync #(.Width(1)) prim_flop_2sync ( 74 // source clock domain 75 .d_i (src_level), 76 // destination clock domain 77 .clk_i (clk_dst_i), 78 .rst_ni (rst_dst_ni), 79 .q_o (dst_level) 80 ); 81 82 //////////////////////////////////////// 83 // convert level signal back to pulse // 84 //////////////////////////////////////// 85 logic dst_level_q; 86 87 // delay dst_level by 1 cycle 88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin 89 1/1 if (!rst_dst_ni) begin Tests: T1 T2 T4  90 1/1 dst_level_q <= 1'b0; Tests: T1 T2 T4  91 end else begin 92 1/1 dst_level_q <= dst_level; Tests: T1 T2 T4  93 end 94 end 95 96 // edge detection 97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level; Tests: T1 T2 T4 

Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT13,T22,T23
10CoveredT13,T22,T23
11CoveredT13,T25,T26

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT13,T22,T23
10CoveredT13,T25,T26
11CoveredT13,T22,T23

Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00


31 if (!rst_src_ni) begin -1- 32 src_level <= 1'b0; ==> 33 end else begin 34 src_level <= src_level ^ src_pulse_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


89 if (!rst_dst_ni) begin -1- 90 dst_level_q <= 1'b0; ==> 91 end else begin 92 dst_level_q <= dst_level; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


Assert Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
DstPulseCheck_A 1332231489 6218 0 0
SrcPulseCheck_M 7271325 6218 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1332231489 6218 0 0
T3 215595 0 0 0
T13 128352 20 0 0
T14 195910 0 0 0
T15 101494 0 0 0
T16 129820 0 0 0
T17 51227 0 0 0
T22 235908 1 0 0
T23 67247 1 0 0
T24 0 1 0 0
T25 0 20 0 0
T26 0 20 0 0
T31 60611 0 0 0
T51 0 20 0 0
T65 0 20 0 0
T74 104693 0 0 0
T82 0 20 0 0
T83 0 20 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 7271325 6218 0 0
T3 481 0 0 0
T13 523 20 0 0
T14 412 0 0 0
T15 423 0 0 0
T16 1038 0 0 0
T17 426 0 0 0
T22 491 1 0 0
T23 497 1 0 0
T24 0 1 0 0
T25 0 20 0 0
T26 0 20 0 0
T31 448 0 0 0
T51 0 20 0 0
T65 0 20 0 0
T74 403 0 0 0
T82 0 20 0 0
T83 0 20 0 0

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00

30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin 31 1/1 if (!rst_src_ni) begin Tests: T1 T2 T4  32 1/1 src_level <= 1'b0; Tests: T1 T2 T4  33 end else begin 34 1/1 src_level <= src_level ^ src_pulse_i; Tests: T1 T2 T4  35 end 36 end 37 38 39 // source active must come far enough such that the destination domain has time 40 // to create a valid pulse. 41 `ifdef INC_ASSERT 42 //VCS coverage off 43 // pragma coverage off 44 45 // source active flag tracks whether there is an ongoing "toggle" event. 46 // Until this toggle event is accepted by the destination domain (negative edge of 47 // of the pulse output), the source side cannot toggle again. 48 logic effective_rst_n; 49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o; 50 51 logic src_active_flag_d, src_active_flag_q; 52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q; 53 54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin 55 unreachable if (!effective_rst_n) begin 56 unreachable src_active_flag_q <= '0; 57 end else begin 58 unreachable src_active_flag_q <= src_active_flag_d; 59 end 60 end 61 62 //VCS coverage on 63 // pragma coverage on 64 65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni) 66 `endif 67 68 ////////////////////////////////////////////////////////// 69 // synchronize level signal to destination clock domain // 70 ////////////////////////////////////////////////////////// 71 logic dst_level; 72 73 prim_flop_2sync #(.Width(1)) prim_flop_2sync ( 74 // source clock domain 75 .d_i (src_level), 76 // destination clock domain 77 .clk_i (clk_dst_i), 78 .rst_ni (rst_dst_ni), 79 .q_o (dst_level) 80 ); 81 82 //////////////////////////////////////// 83 // convert level signal back to pulse // 84 //////////////////////////////////////// 85 logic dst_level_q; 86 87 // delay dst_level by 1 cycle 88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin 89 1/1 if (!rst_dst_ni) begin Tests: T1 T2 T4  90 1/1 dst_level_q <= 1'b0; Tests: T1 T2 T4  91 end else begin 92 1/1 dst_level_q <= dst_level; Tests: T1 T2 T4  93 end 94 end 95 96 // edge detection 97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level; Tests: T1 T2 T13 

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT1,T2,T13
10CoveredT1,T2,T13
11CoveredT13,T25,T26

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT1,T2,T13
10CoveredT13,T25,T26
11CoveredT1,T2,T13

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00


31 if (!rst_src_ni) begin -1- 32 src_level <= 1'b0; ==> 33 end else begin 34 src_level <= src_level ^ src_pulse_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


89 if (!rst_dst_ni) begin -1- 90 dst_level_q <= 1'b0; ==> 91 end else begin 92 dst_level_q <= dst_level; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
DstPulseCheck_A 7271325 7356 0 0
SrcPulseCheck_M 1332231489 7428 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7271325 7356 0 0
T1 509 1 0 0
T2 486 1 0 0
T3 481 0 0 0
T4 666 0 0 0
T7 0 1 0 0
T12 747 0 0 0
T13 523 20 0 0
T14 412 0 0 0
T15 423 0 0 0
T16 1038 1 0 0
T17 426 0 0 0
T22 0 1 0 0
T23 0 1 0 0
T25 0 20 0 0
T26 0 20 0 0
T31 0 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 1332231489 7428 0 0
T1 63648 1 0 0
T2 58317 1 0 0
T3 215595 0 0 0
T4 43326 0 0 0
T7 0 1 0 0
T12 18956 0 0 0
T13 128352 20 0 0
T14 195910 0 0 0
T15 101494 0 0 0
T16 129820 1 0 0
T17 51227 0 0 0
T22 0 1 0 0
T23 0 1 0 0
T25 0 20 0 0
T26 0 20 0 0
T31 0 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00

30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin 31 1/1 if (!rst_src_ni) begin Tests: T1 T2 T4  32 1/1 src_level <= 1'b0; Tests: T1 T2 T4  33 end else begin 34 1/1 src_level <= src_level ^ src_pulse_i; Tests: T1 T2 T4  35 end 36 end 37 38 39 // source active must come far enough such that the destination domain has time 40 // to create a valid pulse. 41 `ifdef INC_ASSERT 42 //VCS coverage off 43 // pragma coverage off 44 45 // source active flag tracks whether there is an ongoing "toggle" event. 46 // Until this toggle event is accepted by the destination domain (negative edge of 47 // of the pulse output), the source side cannot toggle again. 48 logic effective_rst_n; 49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o; 50 51 logic src_active_flag_d, src_active_flag_q; 52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q; 53 54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin 55 unreachable if (!effective_rst_n) begin 56 unreachable src_active_flag_q <= '0; 57 end else begin 58 unreachable src_active_flag_q <= src_active_flag_d; 59 end 60 end 61 62 //VCS coverage on 63 // pragma coverage on 64 65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni) 66 `endif 67 68 ////////////////////////////////////////////////////////// 69 // synchronize level signal to destination clock domain // 70 ////////////////////////////////////////////////////////// 71 logic dst_level; 72 73 prim_flop_2sync #(.Width(1)) prim_flop_2sync ( 74 // source clock domain 75 .d_i (src_level), 76 // destination clock domain 77 .clk_i (clk_dst_i), 78 .rst_ni (rst_dst_ni), 79 .q_o (dst_level) 80 ); 81 82 //////////////////////////////////////// 83 // convert level signal back to pulse // 84 //////////////////////////////////////// 85 logic dst_level_q; 86 87 // delay dst_level by 1 cycle 88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin 89 1/1 if (!rst_dst_ni) begin Tests: T1 T2 T4  90 1/1 dst_level_q <= 1'b0; Tests: T1 T2 T4  91 end else begin 92 1/1 dst_level_q <= dst_level; Tests: T1 T2 T4  93 end 94 end 95 96 // edge detection 97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level; Tests: T1 T2 T4 

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT1,T2,T13
10CoveredT1,T2,T13
11CoveredT13,T25,T26

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT1,T2,T13
10CoveredT13,T25,T26
11CoveredT1,T2,T13

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00


31 if (!rst_src_ni) begin -1- 32 src_level <= 1'b0; ==> 33 end else begin 34 src_level <= src_level ^ src_pulse_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


89 if (!rst_dst_ni) begin -1- 90 dst_level_q <= 1'b0; ==> 91 end else begin 92 dst_level_q <= dst_level; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
DstPulseCheck_A 1332231489 7419 0 0
SrcPulseCheck_M 7271325 7419 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1332231489 7419 0 0
T1 63648 1 0 0
T2 58317 1 0 0
T3 215595 0 0 0
T4 43326 0 0 0
T7 0 1 0 0
T12 18956 0 0 0
T13 128352 20 0 0
T14 195910 0 0 0
T15 101494 0 0 0
T16 129820 1 0 0
T17 51227 0 0 0
T22 0 1 0 0
T23 0 1 0 0
T25 0 20 0 0
T26 0 20 0 0
T31 0 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 7271325 7419 0 0
T1 509 1 0 0
T2 486 1 0 0
T3 481 0 0 0
T4 666 0 0 0
T7 0 1 0 0
T12 747 0 0 0
T13 523 20 0 0
T14 412 0 0 0
T15 423 0 0 0
T16 1038 1 0 0
T17 426 0 0 0
T22 0 1 0 0
T23 0 1 0 0
T25 0 20 0 0
T26 0 20 0 0
T31 0 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00

30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin 31 1/1 if (!rst_src_ni) begin Tests: T1 T2 T4  32 1/1 src_level <= 1'b0; Tests: T1 T2 T4  33 end else begin 34 1/1 src_level <= src_level ^ src_pulse_i; Tests: T1 T2 T4  35 end 36 end 37 38 39 // source active must come far enough such that the destination domain has time 40 // to create a valid pulse. 41 `ifdef INC_ASSERT 42 //VCS coverage off 43 // pragma coverage off 44 45 // source active flag tracks whether there is an ongoing "toggle" event. 46 // Until this toggle event is accepted by the destination domain (negative edge of 47 // of the pulse output), the source side cannot toggle again. 48 logic effective_rst_n; 49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o; 50 51 logic src_active_flag_d, src_active_flag_q; 52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q; 53 54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin 55 unreachable if (!effective_rst_n) begin 56 unreachable src_active_flag_q <= '0; 57 end else begin 58 unreachable src_active_flag_q <= src_active_flag_d; 59 end 60 end 61 62 //VCS coverage on 63 // pragma coverage on 64 65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni) 66 `endif 67 68 ////////////////////////////////////////////////////////// 69 // synchronize level signal to destination clock domain // 70 ////////////////////////////////////////////////////////// 71 logic dst_level; 72 73 prim_flop_2sync #(.Width(1)) prim_flop_2sync ( 74 // source clock domain 75 .d_i (src_level), 76 // destination clock domain 77 .clk_i (clk_dst_i), 78 .rst_ni (rst_dst_ni), 79 .q_o (dst_level) 80 ); 81 82 //////////////////////////////////////// 83 // convert level signal back to pulse // 84 //////////////////////////////////////// 85 logic dst_level_q; 86 87 // delay dst_level by 1 cycle 88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin 89 1/1 if (!rst_dst_ni) begin Tests: T1 T2 T4  90 1/1 dst_level_q <= 1'b0; Tests: T1 T2 T4  91 end else begin 92 1/1 dst_level_q <= dst_level; Tests: T1 T2 T4  93 end 94 end 95 96 // edge detection 97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level; Tests: T13 T25 T26 

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT13,T25,T26
10CoveredT13,T25,T26
11CoveredT13,T25,T26

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT13,T25,T26
10CoveredT13,T25,T26
11CoveredT13,T25,T26

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00


31 if (!rst_src_ni) begin -1- 32 src_level <= 1'b0; ==> 33 end else begin 34 src_level <= src_level ^ src_pulse_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


89 if (!rst_dst_ni) begin -1- 90 dst_level_q <= 1'b0; ==> 91 end else begin 92 dst_level_q <= dst_level; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
DstPulseCheck_A 7271325 6056 0 0
SrcPulseCheck_M 1332231489 6127 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7271325 6056 0 0
T3 481 0 0 0
T13 523 20 0 0
T14 412 0 0 0
T15 423 0 0 0
T16 1038 0 0 0
T17 426 0 0 0
T22 491 0 0 0
T23 497 0 0 0
T25 0 20 0 0
T26 0 20 0 0
T31 448 0 0 0
T51 0 20 0 0
T65 0 20 0 0
T74 403 0 0 0
T82 0 20 0 0
T83 0 20 0 0
T84 0 20 0 0
T85 0 20 0 0
T86 0 20 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 1332231489 6127 0 0
T3 215595 0 0 0
T13 128352 20 0 0
T14 195910 0 0 0
T15 101494 0 0 0
T16 129820 0 0 0
T17 51227 0 0 0
T22 235908 0 0 0
T23 67247 0 0 0
T25 0 20 0 0
T26 0 20 0 0
T31 60611 0 0 0
T51 0 20 0 0
T65 0 20 0 0
T74 104693 0 0 0
T82 0 20 0 0
T83 0 20 0 0
T84 0 20 0 0
T85 0 20 0 0
T86 0 20 0 0

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00

30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin 31 1/1 if (!rst_src_ni) begin Tests: T1 T2 T4  32 1/1 src_level <= 1'b0; Tests: T1 T2 T4  33 end else begin 34 1/1 src_level <= src_level ^ src_pulse_i; Tests: T1 T2 T4  35 end 36 end 37 38 39 // source active must come far enough such that the destination domain has time 40 // to create a valid pulse. 41 `ifdef INC_ASSERT 42 //VCS coverage off 43 // pragma coverage off 44 45 // source active flag tracks whether there is an ongoing "toggle" event. 46 // Until this toggle event is accepted by the destination domain (negative edge of 47 // of the pulse output), the source side cannot toggle again. 48 logic effective_rst_n; 49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o; 50 51 logic src_active_flag_d, src_active_flag_q; 52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q; 53 54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin 55 unreachable if (!effective_rst_n) begin 56 unreachable src_active_flag_q <= '0; 57 end else begin 58 unreachable src_active_flag_q <= src_active_flag_d; 59 end 60 end 61 62 //VCS coverage on 63 // pragma coverage on 64 65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni) 66 `endif 67 68 ////////////////////////////////////////////////////////// 69 // synchronize level signal to destination clock domain // 70 ////////////////////////////////////////////////////////// 71 logic dst_level; 72 73 prim_flop_2sync #(.Width(1)) prim_flop_2sync ( 74 // source clock domain 75 .d_i (src_level), 76 // destination clock domain 77 .clk_i (clk_dst_i), 78 .rst_ni (rst_dst_ni), 79 .q_o (dst_level) 80 ); 81 82 //////////////////////////////////////// 83 // convert level signal back to pulse // 84 //////////////////////////////////////// 85 logic dst_level_q; 86 87 // delay dst_level by 1 cycle 88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin 89 1/1 if (!rst_dst_ni) begin Tests: T1 T2 T4  90 1/1 dst_level_q <= 1'b0; Tests: T1 T2 T4  91 end else begin 92 1/1 dst_level_q <= dst_level; Tests: T1 T2 T4  93 end 94 end 95 96 // edge detection 97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level; Tests: T1 T2 T4 

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT13,T25,T26
10CoveredT13,T25,T26
11CoveredT13,T25,T26

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT13,T25,T26
10CoveredT13,T25,T26
11CoveredT13,T25,T26

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00


31 if (!rst_src_ni) begin -1- 32 src_level <= 1'b0; ==> 33 end else begin 34 src_level <= src_level ^ src_pulse_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


89 if (!rst_dst_ni) begin -1- 90 dst_level_q <= 1'b0; ==> 91 end else begin 92 dst_level_q <= dst_level; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
DstPulseCheck_A 1332231489 6120 0 0
SrcPulseCheck_M 7271325 6120 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1332231489 6120 0 0
T3 215595 0 0 0
T13 128352 20 0 0
T14 195910 0 0 0
T15 101494 0 0 0
T16 129820 0 0 0
T17 51227 0 0 0
T22 235908 0 0 0
T23 67247 0 0 0
T25 0 20 0 0
T26 0 20 0 0
T31 60611 0 0 0
T51 0 20 0 0
T65 0 20 0 0
T74 104693 0 0 0
T82 0 20 0 0
T83 0 20 0 0
T84 0 20 0 0
T85 0 20 0 0
T86 0 20 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 7271325 6120 0 0
T3 481 0 0 0
T13 523 20 0 0
T14 412 0 0 0
T15 423 0 0 0
T16 1038 0 0 0
T17 426 0 0 0
T22 491 0 0 0
T23 497 0 0 0
T25 0 20 0 0
T26 0 20 0 0
T31 448 0 0 0
T51 0 20 0 0
T65 0 20 0 0
T74 403 0 0 0
T82 0 20 0 0
T83 0 20 0 0
T84 0 20 0 0
T85 0 20 0 0
T86 0 20 0 0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00

30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin 31 1/1 if (!rst_src_ni) begin Tests: T1 T2 T4  32 1/1 src_level <= 1'b0; Tests: T1 T2 T4  33 end else begin 34 1/1 src_level <= src_level ^ src_pulse_i; Tests: T1 T2 T4  35 end 36 end 37 38 39 // source active must come far enough such that the destination domain has time 40 // to create a valid pulse. 41 `ifdef INC_ASSERT 42 //VCS coverage off 43 // pragma coverage off 44 45 // source active flag tracks whether there is an ongoing "toggle" event. 46 // Until this toggle event is accepted by the destination domain (negative edge of 47 // of the pulse output), the source side cannot toggle again. 48 logic effective_rst_n; 49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o; 50 51 logic src_active_flag_d, src_active_flag_q; 52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q; 53 54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin 55 unreachable if (!effective_rst_n) begin 56 unreachable src_active_flag_q <= '0; 57 end else begin 58 unreachable src_active_flag_q <= src_active_flag_d; 59 end 60 end 61 62 //VCS coverage on 63 // pragma coverage on 64 65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni) 66 `endif 67 68 ////////////////////////////////////////////////////////// 69 // synchronize level signal to destination clock domain // 70 ////////////////////////////////////////////////////////// 71 logic dst_level; 72 73 prim_flop_2sync #(.Width(1)) prim_flop_2sync ( 74 // source clock domain 75 .d_i (src_level), 76 // destination clock domain 77 .clk_i (clk_dst_i), 78 .rst_ni (rst_dst_ni), 79 .q_o (dst_level) 80 ); 81 82 //////////////////////////////////////// 83 // convert level signal back to pulse // 84 //////////////////////////////////////// 85 logic dst_level_q; 86 87 // delay dst_level by 1 cycle 88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin 89 1/1 if (!rst_dst_ni) begin Tests: T1 T2 T4  90 1/1 dst_level_q <= 1'b0; Tests: T1 T2 T4  91 end else begin 92 1/1 dst_level_q <= dst_level; Tests: T1 T2 T4  93 end 94 end 95 96 // edge detection 97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level; Tests: T3 T8 T10 

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT3,T8,T10
10CoveredT3,T8,T10
11CoveredT21,T56,T34

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT3,T8,T10
10CoveredT21,T56,T34
11CoveredT3,T8,T10

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00


31 if (!rst_src_ni) begin -1- 32 src_level <= 1'b0; ==> 33 end else begin 34 src_level <= src_level ^ src_pulse_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


89 if (!rst_dst_ni) begin -1- 90 dst_level_q <= 1'b0; ==> 91 end else begin 92 dst_level_q <= dst_level; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
DstPulseCheck_A 7271325 1131 0 0
SrcPulseCheck_M 1332231489 1195 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7271325 1131 0 0
T3 481 1 0 0
T5 689 0 0 0
T7 506 0 0 0
T8 0 1 0 0
T10 0 1 0 0
T21 0 28 0 0
T22 491 0 0 0
T23 497 0 0 0
T25 502 0 0 0
T26 501 0 0 0
T31 448 0 0 0
T45 0 1 0 0
T48 0 1 0 0
T49 0 1 0 0
T51 0 1 0 0
T52 0 1 0 0
T53 0 1 0 0
T74 403 0 0 0
T81 405 0 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 1332231489 1195 0 0
T3 215595 1 0 0
T5 54551 0 0 0
T7 60814 0 0 0
T8 0 1 0 0
T10 0 1 0 0
T21 0 28 0 0
T22 235908 0 0 0
T23 67247 0 0 0
T25 248822 0 0 0
T26 250832 0 0 0
T31 60611 0 0 0
T45 0 1 0 0
T48 0 1 0 0
T49 0 1 0 0
T51 0 1 0 0
T52 0 1 0 0
T53 0 1 0 0
T74 104693 0 0 0
T81 101285 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00

30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin 31 1/1 if (!rst_src_ni) begin Tests: T1 T2 T4  32 1/1 src_level <= 1'b0; Tests: T1 T2 T4  33 end else begin 34 1/1 src_level <= src_level ^ src_pulse_i; Tests: T1 T2 T4  35 end 36 end 37 38 39 // source active must come far enough such that the destination domain has time 40 // to create a valid pulse. 41 `ifdef INC_ASSERT 42 //VCS coverage off 43 // pragma coverage off 44 45 // source active flag tracks whether there is an ongoing "toggle" event. 46 // Until this toggle event is accepted by the destination domain (negative edge of 47 // of the pulse output), the source side cannot toggle again. 48 logic effective_rst_n; 49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o; 50 51 logic src_active_flag_d, src_active_flag_q; 52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q; 53 54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin 55 unreachable if (!effective_rst_n) begin 56 unreachable src_active_flag_q <= '0; 57 end else begin 58 unreachable src_active_flag_q <= src_active_flag_d; 59 end 60 end 61 62 //VCS coverage on 63 // pragma coverage on 64 65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni) 66 `endif 67 68 ////////////////////////////////////////////////////////// 69 // synchronize level signal to destination clock domain // 70 ////////////////////////////////////////////////////////// 71 logic dst_level; 72 73 prim_flop_2sync #(.Width(1)) prim_flop_2sync ( 74 // source clock domain 75 .d_i (src_level), 76 // destination clock domain 77 .clk_i (clk_dst_i), 78 .rst_ni (rst_dst_ni), 79 .q_o (dst_level) 80 ); 81 82 //////////////////////////////////////// 83 // convert level signal back to pulse // 84 //////////////////////////////////////// 85 logic dst_level_q; 86 87 // delay dst_level by 1 cycle 88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin 89 1/1 if (!rst_dst_ni) begin Tests: T1 T2 T4  90 1/1 dst_level_q <= 1'b0; Tests: T1 T2 T4  91 end else begin 92 1/1 dst_level_q <= dst_level; Tests: T1 T2 T4  93 end 94 end 95 96 // edge detection 97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level; Tests: T1 T2 T4 

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT3,T8,T10
10CoveredT3,T8,T10
11CoveredT21,T56,T34

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT3,T8,T10
10CoveredT21,T56,T34
11CoveredT3,T8,T10

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00


31 if (!rst_src_ni) begin -1- 32 src_level <= 1'b0; ==> 33 end else begin 34 src_level <= src_level ^ src_pulse_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


89 if (!rst_dst_ni) begin -1- 90 dst_level_q <= 1'b0; ==> 91 end else begin 92 dst_level_q <= dst_level; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
DstPulseCheck_A 1332231489 1193 0 0
SrcPulseCheck_M 7271325 1193 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1332231489 1193 0 0
T3 215595 1 0 0
T5 54551 0 0 0
T7 60814 0 0 0
T8 0 1 0 0
T10 0 1 0 0
T21 0 28 0 0
T22 235908 0 0 0
T23 67247 0 0 0
T25 248822 0 0 0
T26 250832 0 0 0
T31 60611 0 0 0
T45 0 1 0 0
T48 0 1 0 0
T49 0 1 0 0
T51 0 1 0 0
T52 0 1 0 0
T53 0 1 0 0
T74 104693 0 0 0
T81 101285 0 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 7271325 1193 0 0
T3 481 1 0 0
T5 689 0 0 0
T7 506 0 0 0
T8 0 1 0 0
T10 0 1 0 0
T21 0 28 0 0
T22 491 0 0 0
T23 497 0 0 0
T25 502 0 0 0
T26 501 0 0 0
T31 448 0 0 0
T45 0 1 0 0
T48 0 1 0 0
T49 0 1 0 0
T51 0 1 0 0
T52 0 1 0 0
T53 0 1 0 0
T74 403 0 0 0
T81 405 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00

30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin 31 1/1 if (!rst_src_ni) begin Tests: T1 T2 T4  32 1/1 src_level <= 1'b0; Tests: T1 T2 T4  33 end else begin 34 1/1 src_level <= src_level ^ src_pulse_i; Tests: T1 T2 T4  35 end 36 end 37 38 39 // source active must come far enough such that the destination domain has time 40 // to create a valid pulse. 41 `ifdef INC_ASSERT 42 //VCS coverage off 43 // pragma coverage off 44 45 // source active flag tracks whether there is an ongoing "toggle" event. 46 // Until this toggle event is accepted by the destination domain (negative edge of 47 // of the pulse output), the source side cannot toggle again. 48 logic effective_rst_n; 49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o; 50 51 logic src_active_flag_d, src_active_flag_q; 52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q; 53 54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin 55 unreachable if (!effective_rst_n) begin 56 unreachable src_active_flag_q <= '0; 57 end else begin 58 unreachable src_active_flag_q <= src_active_flag_d; 59 end 60 end 61 62 //VCS coverage on 63 // pragma coverage on 64 65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni) 66 `endif 67 68 ////////////////////////////////////////////////////////// 69 // synchronize level signal to destination clock domain // 70 ////////////////////////////////////////////////////////// 71 logic dst_level; 72 73 prim_flop_2sync #(.Width(1)) prim_flop_2sync ( 74 // source clock domain 75 .d_i (src_level), 76 // destination clock domain 77 .clk_i (clk_dst_i), 78 .rst_ni (rst_dst_ni), 79 .q_o (dst_level) 80 ); 81 82 //////////////////////////////////////// 83 // convert level signal back to pulse // 84 //////////////////////////////////////// 85 logic dst_level_q; 86 87 // delay dst_level by 1 cycle 88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin 89 1/1 if (!rst_dst_ni) begin Tests: T1 T2 T4  90 1/1 dst_level_q <= 1'b0; Tests: T1 T2 T4  91 end else begin 92 1/1 dst_level_q <= dst_level; Tests: T1 T2 T4  93 end 94 end 95 96 // edge detection 97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT21,T56,T34

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT1,T2,T3
10CoveredT21,T56,T34
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00


31 if (!rst_src_ni) begin -1- 32 src_level <= 1'b0; ==> 33 end else begin 34 src_level <= src_level ^ src_pulse_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


89 if (!rst_dst_ni) begin -1- 90 dst_level_q <= 1'b0; ==> 91 end else begin 92 dst_level_q <= dst_level; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
DstPulseCheck_A 7271325 2106 0 0
SrcPulseCheck_M 1332231489 2174 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7271325 2106 0 0
T1 509 1 0 0
T2 486 1 0 0
T3 481 1 0 0
T4 666 0 0 0
T6 0 1 0 0
T7 0 1 0 0
T8 0 1 0 0
T12 747 0 0 0
T13 523 0 0 0
T14 412 0 0 0
T15 423 0 0 0
T16 1038 0 0 0
T17 426 0 0 0
T28 0 1 0 0
T29 0 1 0 0
T31 0 1 0 0
T57 0 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 1332231489 2174 0 0
T1 63648 1 0 0
T2 58317 1 0 0
T3 215595 1 0 0
T4 43326 0 0 0
T6 0 1 0 0
T7 0 1 0 0
T8 0 1 0 0
T12 18956 0 0 0
T13 128352 0 0 0
T14 195910 0 0 0
T15 101494 0 0 0
T16 129820 0 0 0
T17 51227 0 0 0
T28 0 1 0 0
T29 0 1 0 0
T31 0 1 0 0
T57 0 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00

30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin 31 1/1 if (!rst_src_ni) begin Tests: T1 T2 T4  32 1/1 src_level <= 1'b0; Tests: T1 T2 T4  33 end else begin 34 1/1 src_level <= src_level ^ src_pulse_i; Tests: T1 T2 T4  35 end 36 end 37 38 39 // source active must come far enough such that the destination domain has time 40 // to create a valid pulse. 41 `ifdef INC_ASSERT 42 //VCS coverage off 43 // pragma coverage off 44 45 // source active flag tracks whether there is an ongoing "toggle" event. 46 // Until this toggle event is accepted by the destination domain (negative edge of 47 // of the pulse output), the source side cannot toggle again. 48 logic effective_rst_n; 49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o; 50 51 logic src_active_flag_d, src_active_flag_q; 52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q; 53 54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin 55 unreachable if (!effective_rst_n) begin 56 unreachable src_active_flag_q <= '0; 57 end else begin 58 unreachable src_active_flag_q <= src_active_flag_d; 59 end 60 end 61 62 //VCS coverage on 63 // pragma coverage on 64 65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni) 66 `endif 67 68 ////////////////////////////////////////////////////////// 69 // synchronize level signal to destination clock domain // 70 ////////////////////////////////////////////////////////// 71 logic dst_level; 72 73 prim_flop_2sync #(.Width(1)) prim_flop_2sync ( 74 // source clock domain 75 .d_i (src_level), 76 // destination clock domain 77 .clk_i (clk_dst_i), 78 .rst_ni (rst_dst_ni), 79 .q_o (dst_level) 80 ); 81 82 //////////////////////////////////////// 83 // convert level signal back to pulse // 84 //////////////////////////////////////// 85 logic dst_level_q; 86 87 // delay dst_level by 1 cycle 88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin 89 1/1 if (!rst_dst_ni) begin Tests: T1 T2 T4  90 1/1 dst_level_q <= 1'b0; Tests: T1 T2 T4  91 end else begin 92 1/1 dst_level_q <= dst_level; Tests: T1 T2 T4  93 end 94 end 95 96 // edge detection 97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level; Tests: T1 T2 T4 

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT21,T56,T34

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT1,T2,T3
10CoveredT21,T56,T34
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00


31 if (!rst_src_ni) begin -1- 32 src_level <= 1'b0; ==> 33 end else begin 34 src_level <= src_level ^ src_pulse_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


89 if (!rst_dst_ni) begin -1- 90 dst_level_q <= 1'b0; ==> 91 end else begin 92 dst_level_q <= dst_level; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
DstPulseCheck_A 1332231489 2169 0 0
SrcPulseCheck_M 7271325 2169 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1332231489 2169 0 0
T1 63648 1 0 0
T2 58317 1 0 0
T3 215595 1 0 0
T4 43326 0 0 0
T6 0 1 0 0
T7 0 1 0 0
T8 0 1 0 0
T12 18956 0 0 0
T13 128352 0 0 0
T14 195910 0 0 0
T15 101494 0 0 0
T16 129820 0 0 0
T17 51227 0 0 0
T28 0 1 0 0
T29 0 1 0 0
T31 0 1 0 0
T57 0 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 7271325 2169 0 0
T1 509 1 0 0
T2 486 1 0 0
T3 481 1 0 0
T4 666 0 0 0
T6 0 1 0 0
T7 0 1 0 0
T8 0 1 0 0
T12 747 0 0 0
T13 523 0 0 0
T14 412 0 0 0
T15 423 0 0 0
T16 1038 0 0 0
T17 426 0 0 0
T28 0 1 0 0
T29 0 1 0 0
T31 0 1 0 0
T57 0 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00

30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin 31 1/1 if (!rst_src_ni) begin Tests: T1 T2 T4  32 1/1 src_level <= 1'b0; Tests: T1 T2 T4  33 end else begin 34 1/1 src_level <= src_level ^ src_pulse_i; Tests: T1 T2 T4  35 end 36 end 37 38 39 // source active must come far enough such that the destination domain has time 40 // to create a valid pulse. 41 `ifdef INC_ASSERT 42 //VCS coverage off 43 // pragma coverage off 44 45 // source active flag tracks whether there is an ongoing "toggle" event. 46 // Until this toggle event is accepted by the destination domain (negative edge of 47 // of the pulse output), the source side cannot toggle again. 48 logic effective_rst_n; 49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o; 50 51 logic src_active_flag_d, src_active_flag_q; 52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q; 53 54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin 55 unreachable if (!effective_rst_n) begin 56 unreachable src_active_flag_q <= '0; 57 end else begin 58 unreachable src_active_flag_q <= src_active_flag_d; 59 end 60 end 61 62 //VCS coverage on 63 // pragma coverage on 64 65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni) 66 `endif 67 68 ////////////////////////////////////////////////////////// 69 // synchronize level signal to destination clock domain // 70 ////////////////////////////////////////////////////////// 71 logic dst_level; 72 73 prim_flop_2sync #(.Width(1)) prim_flop_2sync ( 74 // source clock domain 75 .d_i (src_level), 76 // destination clock domain 77 .clk_i (clk_dst_i), 78 .rst_ni (rst_dst_ni), 79 .q_o (dst_level) 80 ); 81 82 //////////////////////////////////////// 83 // convert level signal back to pulse // 84 //////////////////////////////////////// 85 logic dst_level_q; 86 87 // delay dst_level by 1 cycle 88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin 89 1/1 if (!rst_dst_ni) begin Tests: T1 T2 T4  90 1/1 dst_level_q <= 1'b0; Tests: T1 T2 T4  91 end else begin 92 1/1 dst_level_q <= dst_level; Tests: T1 T2 T4  93 end 94 end 95 96 // edge detection 97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level; Tests: T4 T27 T28 

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT4,T27,T28
10CoveredT4,T27,T28
11CoveredT4,T27,T28

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT4,T27,T28
10CoveredT4,T27,T28
11CoveredT4,T27,T28

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00


31 if (!rst_src_ni) begin -1- 32 src_level <= 1'b0; ==> 33 end else begin 34 src_level <= src_level ^ src_pulse_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


89 if (!rst_dst_ni) begin -1- 90 dst_level_q <= 1'b0; ==> 91 end else begin 92 dst_level_q <= dst_level; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
DstPulseCheck_A 7271325 1443 0 0
SrcPulseCheck_M 1332231489 1518 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7271325 1443 0 0
T3 481 0 0 0
T4 666 5 0 0
T12 747 0 0 0
T13 523 0 0 0
T14 412 0 0 0
T15 423 0 0 0
T16 1038 0 0 0
T17 426 0 0 0
T21 0 2 0 0
T22 491 0 0 0
T27 0 6 0 0
T28 0 3 0 0
T31 448 0 0 0
T58 0 4 0 0
T60 0 3 0 0
T61 0 4 0 0
T62 0 4 0 0
T63 0 5 0 0
T64 0 5 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 1332231489 1518 0 0
T3 215595 0 0 0
T4 43326 5 0 0
T12 18956 0 0 0
T13 128352 0 0 0
T14 195910 0 0 0
T15 101494 0 0 0
T16 129820 0 0 0
T17 51227 0 0 0
T21 0 2 0 0
T22 235908 0 0 0
T27 0 6 0 0
T28 0 3 0 0
T31 60611 0 0 0
T58 0 4 0 0
T60 0 3 0 0
T61 0 4 0 0
T62 0 4 0 0
T63 0 5 0 0
T64 0 5 0 0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00

30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin 31 1/1 if (!rst_src_ni) begin Tests: T1 T2 T4  32 1/1 src_level <= 1'b0; Tests: T1 T2 T4  33 end else begin 34 1/1 src_level <= src_level ^ src_pulse_i; Tests: T1 T2 T4  35 end 36 end 37 38 39 // source active must come far enough such that the destination domain has time 40 // to create a valid pulse. 41 `ifdef INC_ASSERT 42 //VCS coverage off 43 // pragma coverage off 44 45 // source active flag tracks whether there is an ongoing "toggle" event. 46 // Until this toggle event is accepted by the destination domain (negative edge of 47 // of the pulse output), the source side cannot toggle again. 48 logic effective_rst_n; 49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o; 50 51 logic src_active_flag_d, src_active_flag_q; 52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q; 53 54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin 55 unreachable if (!effective_rst_n) begin 56 unreachable src_active_flag_q <= '0; 57 end else begin 58 unreachable src_active_flag_q <= src_active_flag_d; 59 end 60 end 61 62 //VCS coverage on 63 // pragma coverage on 64 65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni) 66 `endif 67 68 ////////////////////////////////////////////////////////// 69 // synchronize level signal to destination clock domain // 70 ////////////////////////////////////////////////////////// 71 logic dst_level; 72 73 prim_flop_2sync #(.Width(1)) prim_flop_2sync ( 74 // source clock domain 75 .d_i (src_level), 76 // destination clock domain 77 .clk_i (clk_dst_i), 78 .rst_ni (rst_dst_ni), 79 .q_o (dst_level) 80 ); 81 82 //////////////////////////////////////// 83 // convert level signal back to pulse // 84 //////////////////////////////////////// 85 logic dst_level_q; 86 87 // delay dst_level by 1 cycle 88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin 89 1/1 if (!rst_dst_ni) begin Tests: T1 T2 T4  90 1/1 dst_level_q <= 1'b0; Tests: T1 T2 T4  91 end else begin 92 1/1 dst_level_q <= dst_level; Tests: T1 T2 T4  93 end 94 end 95 96 // edge detection 97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level; Tests: T1 T2 T4 

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT4,T27,T28
10CoveredT4,T27,T28
11CoveredT4,T27,T28

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT4,T27,T28
10CoveredT4,T27,T28
11CoveredT4,T27,T28

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00


31 if (!rst_src_ni) begin -1- 32 src_level <= 1'b0; ==> 33 end else begin 34 src_level <= src_level ^ src_pulse_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


89 if (!rst_dst_ni) begin -1- 90 dst_level_q <= 1'b0; ==> 91 end else begin 92 dst_level_q <= dst_level; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
DstPulseCheck_A 1332231489 1511 0 0
SrcPulseCheck_M 7271325 1511 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1332231489 1511 0 0
T3 215595 0 0 0
T4 43326 5 0 0
T12 18956 0 0 0
T13 128352 0 0 0
T14 195910 0 0 0
T15 101494 0 0 0
T16 129820 0 0 0
T17 51227 0 0 0
T21 0 2 0 0
T22 235908 0 0 0
T27 0 6 0 0
T28 0 3 0 0
T31 60611 0 0 0
T58 0 4 0 0
T60 0 3 0 0
T61 0 4 0 0
T62 0 4 0 0
T63 0 5 0 0
T64 0 5 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 7271325 1511 0 0
T3 481 0 0 0
T4 666 5 0 0
T12 747 0 0 0
T13 523 0 0 0
T14 412 0 0 0
T15 423 0 0 0
T16 1038 0 0 0
T17 426 0 0 0
T21 0 2 0 0
T22 491 0 0 0
T27 0 6 0 0
T28 0 3 0 0
T31 448 0 0 0
T58 0 4 0 0
T60 0 3 0 0
T61 0 4 0 0
T62 0 4 0 0
T63 0 5 0 0
T64 0 5 0 0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00

30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin 31 1/1 if (!rst_src_ni) begin Tests: T1 T2 T4  32 1/1 src_level <= 1'b0; Tests: T1 T2 T4  33 end else begin 34 1/1 src_level <= src_level ^ src_pulse_i; Tests: T1 T2 T4  35 end 36 end 37 38 39 // source active must come far enough such that the destination domain has time 40 // to create a valid pulse. 41 `ifdef INC_ASSERT 42 //VCS coverage off 43 // pragma coverage off 44 45 // source active flag tracks whether there is an ongoing "toggle" event. 46 // Until this toggle event is accepted by the destination domain (negative edge of 47 // of the pulse output), the source side cannot toggle again. 48 logic effective_rst_n; 49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o; 50 51 logic src_active_flag_d, src_active_flag_q; 52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q; 53 54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin 55 unreachable if (!effective_rst_n) begin 56 unreachable src_active_flag_q <= '0; 57 end else begin 58 unreachable src_active_flag_q <= src_active_flag_d; 59 end 60 end 61 62 //VCS coverage on 63 // pragma coverage on 64 65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni) 66 `endif 67 68 ////////////////////////////////////////////////////////// 69 // synchronize level signal to destination clock domain // 70 ////////////////////////////////////////////////////////// 71 logic dst_level; 72 73 prim_flop_2sync #(.Width(1)) prim_flop_2sync ( 74 // source clock domain 75 .d_i (src_level), 76 // destination clock domain 77 .clk_i (clk_dst_i), 78 .rst_ni (rst_dst_ni), 79 .q_o (dst_level) 80 ); 81 82 //////////////////////////////////////// 83 // convert level signal back to pulse // 84 //////////////////////////////////////// 85 logic dst_level_q; 86 87 // delay dst_level by 1 cycle 88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin 89 1/1 if (!rst_dst_ni) begin Tests: T1 T2 T4  90 1/1 dst_level_q <= 1'b0; Tests: T1 T2 T4  91 end else begin 92 1/1 dst_level_q <= dst_level; Tests: T1 T2 T4  93 end 94 end 95 96 // edge detection 97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level; Tests: T4 T27 T28 

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT4,T27,T28
10CoveredT4,T27,T28
11CoveredT4,T27,T28

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT4,T27,T28
10CoveredT4,T27,T28
11CoveredT4,T27,T28

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00


31 if (!rst_src_ni) begin -1- 32 src_level <= 1'b0; ==> 33 end else begin 34 src_level <= src_level ^ src_pulse_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


89 if (!rst_dst_ni) begin -1- 90 dst_level_q <= 1'b0; ==> 91 end else begin 92 dst_level_q <= dst_level; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
DstPulseCheck_A 7271325 1245 0 0
SrcPulseCheck_M 1332231489 1310 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7271325 1245 0 0
T3 481 0 0 0
T4 666 2 0 0
T12 747 0 0 0
T13 523 0 0 0
T14 412 0 0 0
T15 423 0 0 0
T16 1038 0 0 0
T17 426 0 0 0
T21 0 1 0 0
T22 491 0 0 0
T27 0 3 0 0
T28 0 3 0 0
T31 448 0 0 0
T58 0 3 0 0
T60 0 2 0 0
T61 0 3 0 0
T62 0 3 0 0
T63 0 3 0 0
T64 0 3 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 1332231489 1310 0 0
T3 215595 0 0 0
T4 43326 2 0 0
T12 18956 0 0 0
T13 128352 0 0 0
T14 195910 0 0 0
T15 101494 0 0 0
T16 129820 0 0 0
T17 51227 0 0 0
T21 0 1 0 0
T22 235908 0 0 0
T27 0 3 0 0
T28 0 3 0 0
T31 60611 0 0 0
T58 0 3 0 0
T60 0 2 0 0
T61 0 3 0 0
T62 0 3 0 0
T63 0 3 0 0
T64 0 3 0 0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00

30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin 31 1/1 if (!rst_src_ni) begin Tests: T1 T2 T4  32 1/1 src_level <= 1'b0; Tests: T1 T2 T4  33 end else begin 34 1/1 src_level <= src_level ^ src_pulse_i; Tests: T1 T2 T4  35 end 36 end 37 38 39 // source active must come far enough such that the destination domain has time 40 // to create a valid pulse. 41 `ifdef INC_ASSERT 42 //VCS coverage off 43 // pragma coverage off 44 45 // source active flag tracks whether there is an ongoing "toggle" event. 46 // Until this toggle event is accepted by the destination domain (negative edge of 47 // of the pulse output), the source side cannot toggle again. 48 logic effective_rst_n; 49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o; 50 51 logic src_active_flag_d, src_active_flag_q; 52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q; 53 54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin 55 unreachable if (!effective_rst_n) begin 56 unreachable src_active_flag_q <= '0; 57 end else begin 58 unreachable src_active_flag_q <= src_active_flag_d; 59 end 60 end 61 62 //VCS coverage on 63 // pragma coverage on 64 65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni) 66 `endif 67 68 ////////////////////////////////////////////////////////// 69 // synchronize level signal to destination clock domain // 70 ////////////////////////////////////////////////////////// 71 logic dst_level; 72 73 prim_flop_2sync #(.Width(1)) prim_flop_2sync ( 74 // source clock domain 75 .d_i (src_level), 76 // destination clock domain 77 .clk_i (clk_dst_i), 78 .rst_ni (rst_dst_ni), 79 .q_o (dst_level) 80 ); 81 82 //////////////////////////////////////// 83 // convert level signal back to pulse // 84 //////////////////////////////////////// 85 logic dst_level_q; 86 87 // delay dst_level by 1 cycle 88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin 89 1/1 if (!rst_dst_ni) begin Tests: T1 T2 T4  90 1/1 dst_level_q <= 1'b0; Tests: T1 T2 T4  91 end else begin 92 1/1 dst_level_q <= dst_level; Tests: T1 T2 T4  93 end 94 end 95 96 // edge detection 97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level; Tests: T1 T2 T4 

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT4,T27,T28
10CoveredT4,T27,T28
11CoveredT4,T27,T28

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT4,T27,T28
10CoveredT4,T27,T28
11CoveredT4,T27,T28

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00


31 if (!rst_src_ni) begin -1- 32 src_level <= 1'b0; ==> 33 end else begin 34 src_level <= src_level ^ src_pulse_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


89 if (!rst_dst_ni) begin -1- 90 dst_level_q <= 1'b0; ==> 91 end else begin 92 dst_level_q <= dst_level; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
DstPulseCheck_A 1332231489 1303 0 0
SrcPulseCheck_M 7271325 1303 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1332231489 1303 0 0
T3 215595 0 0 0
T4 43326 2 0 0
T12 18956 0 0 0
T13 128352 0 0 0
T14 195910 0 0 0
T15 101494 0 0 0
T16 129820 0 0 0
T17 51227 0 0 0
T21 0 1 0 0
T22 235908 0 0 0
T27 0 3 0 0
T28 0 3 0 0
T31 60611 0 0 0
T58 0 3 0 0
T60 0 2 0 0
T61 0 3 0 0
T62 0 3 0 0
T63 0 3 0 0
T64 0 3 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 7271325 1303 0 0
T3 481 0 0 0
T4 666 2 0 0
T12 747 0 0 0
T13 523 0 0 0
T14 412 0 0 0
T15 423 0 0 0
T16 1038 0 0 0
T17 426 0 0 0
T21 0 1 0 0
T22 491 0 0 0
T27 0 3 0 0
T28 0 3 0 0
T31 448 0 0 0
T58 0 3 0 0
T60 0 2 0 0
T61 0 3 0 0
T62 0 3 0 0
T63 0 3 0 0
T64 0 3 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00

30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin 31 1/1 if (!rst_src_ni) begin Tests: T1 T2 T4  32 1/1 src_level <= 1'b0; Tests: T1 T2 T4  33 end else begin 34 1/1 src_level <= src_level ^ src_pulse_i; Tests: T1 T2 T4  35 end 36 end 37 38 39 // source active must come far enough such that the destination domain has time 40 // to create a valid pulse. 41 `ifdef INC_ASSERT 42 //VCS coverage off 43 // pragma coverage off 44 45 // source active flag tracks whether there is an ongoing "toggle" event. 46 // Until this toggle event is accepted by the destination domain (negative edge of 47 // of the pulse output), the source side cannot toggle again. 48 logic effective_rst_n; 49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o; 50 51 logic src_active_flag_d, src_active_flag_q; 52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q; 53 54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin 55 unreachable if (!effective_rst_n) begin 56 unreachable src_active_flag_q <= '0; 57 end else begin 58 unreachable src_active_flag_q <= src_active_flag_d; 59 end 60 end 61 62 //VCS coverage on 63 // pragma coverage on 64 65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni) 66 `endif 67 68 ////////////////////////////////////////////////////////// 69 // synchronize level signal to destination clock domain // 70 ////////////////////////////////////////////////////////// 71 logic dst_level; 72 73 prim_flop_2sync #(.Width(1)) prim_flop_2sync ( 74 // source clock domain 75 .d_i (src_level), 76 // destination clock domain 77 .clk_i (clk_dst_i), 78 .rst_ni (rst_dst_ni), 79 .q_o (dst_level) 80 ); 81 82 //////////////////////////////////////// 83 // convert level signal back to pulse // 84 //////////////////////////////////////// 85 logic dst_level_q; 86 87 // delay dst_level by 1 cycle 88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin 89 1/1 if (!rst_dst_ni) begin Tests: T1 T2 T4  90 1/1 dst_level_q <= 1'b0; Tests: T1 T2 T4  91 end else begin 92 1/1 dst_level_q <= dst_level; Tests: T1 T2 T4  93 end 94 end 95 96 // edge detection 97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level; Tests: T1 T7 T29 

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT1,T7,T29
10CoveredT1,T7,T29
11CoveredT11,T21,T30

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT1,T7,T29
10CoveredT11,T21,T30
11CoveredT1,T7,T29

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00


31 if (!rst_src_ni) begin -1- 32 src_level <= 1'b0; ==> 33 end else begin 34 src_level <= src_level ^ src_pulse_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


89 if (!rst_dst_ni) begin -1- 90 dst_level_q <= 1'b0; ==> 91 end else begin 92 dst_level_q <= dst_level; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
DstPulseCheck_A 7271325 7633 0 0
SrcPulseCheck_M 1332231489 7701 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7271325 7633 0 0
T1 509 1 0 0
T2 486 0 0 0
T3 481 0 0 0
T4 666 0 0 0
T7 0 1 0 0
T11 0 80 0 0
T12 747 0 0 0
T13 523 0 0 0
T14 412 0 0 0
T15 423 0 0 0
T16 1038 0 0 0
T17 426 0 0 0
T21 0 11 0 0
T29 0 1 0 0
T30 0 65 0 0
T40 0 77 0 0
T56 0 11 0 0
T59 0 1 0 0
T87 0 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 1332231489 7701 0 0
T1 63648 1 0 0
T2 58317 0 0 0
T3 215595 0 0 0
T4 43326 0 0 0
T7 0 1 0 0
T11 0 80 0 0
T12 18956 0 0 0
T13 128352 0 0 0
T14 195910 0 0 0
T15 101494 0 0 0
T16 129820 0 0 0
T17 51227 0 0 0
T21 0 11 0 0
T29 0 1 0 0
T30 0 65 0 0
T40 0 77 0 0
T56 0 11 0 0
T59 0 1 0 0
T87 0 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00

30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin 31 1/1 if (!rst_src_ni) begin Tests: T1 T2 T4  32 1/1 src_level <= 1'b0; Tests: T1 T2 T4  33 end else begin 34 1/1 src_level <= src_level ^ src_pulse_i; Tests: T1 T2 T4  35 end 36 end 37 38 39 // source active must come far enough such that the destination domain has time 40 // to create a valid pulse. 41 `ifdef INC_ASSERT 42 //VCS coverage off 43 // pragma coverage off 44 45 // source active flag tracks whether there is an ongoing "toggle" event. 46 // Until this toggle event is accepted by the destination domain (negative edge of 47 // of the pulse output), the source side cannot toggle again. 48 logic effective_rst_n; 49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o; 50 51 logic src_active_flag_d, src_active_flag_q; 52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q; 53 54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin 55 unreachable if (!effective_rst_n) begin 56 unreachable src_active_flag_q <= '0; 57 end else begin 58 unreachable src_active_flag_q <= src_active_flag_d; 59 end 60 end 61 62 //VCS coverage on 63 // pragma coverage on 64 65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni) 66 `endif 67 68 ////////////////////////////////////////////////////////// 69 // synchronize level signal to destination clock domain // 70 ////////////////////////////////////////////////////////// 71 logic dst_level; 72 73 prim_flop_2sync #(.Width(1)) prim_flop_2sync ( 74 // source clock domain 75 .d_i (src_level), 76 // destination clock domain 77 .clk_i (clk_dst_i), 78 .rst_ni (rst_dst_ni), 79 .q_o (dst_level) 80 ); 81 82 //////////////////////////////////////// 83 // convert level signal back to pulse // 84 //////////////////////////////////////// 85 logic dst_level_q; 86 87 // delay dst_level by 1 cycle 88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin 89 1/1 if (!rst_dst_ni) begin Tests: T1 T2 T4  90 1/1 dst_level_q <= 1'b0; Tests: T1 T2 T4  91 end else begin 92 1/1 dst_level_q <= dst_level; Tests: T1 T2 T4  93 end 94 end 95 96 // edge detection 97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level; Tests: T1 T2 T4 

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT1,T7,T29
10CoveredT1,T7,T29
11CoveredT11,T21,T30

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT1,T7,T29
10CoveredT11,T21,T30
11CoveredT1,T7,T29

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00


31 if (!rst_src_ni) begin -1- 32 src_level <= 1'b0; ==> 33 end else begin 34 src_level <= src_level ^ src_pulse_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


89 if (!rst_dst_ni) begin -1- 90 dst_level_q <= 1'b0; ==> 91 end else begin 92 dst_level_q <= dst_level; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
DstPulseCheck_A 1332231489 7698 0 0
SrcPulseCheck_M 7271325 7698 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1332231489 7698 0 0
T1 63648 1 0 0
T2 58317 0 0 0
T3 215595 0 0 0
T4 43326 0 0 0
T7 0 1 0 0
T11 0 80 0 0
T12 18956 0 0 0
T13 128352 0 0 0
T14 195910 0 0 0
T15 101494 0 0 0
T16 129820 0 0 0
T17 51227 0 0 0
T21 0 11 0 0
T29 0 1 0 0
T30 0 65 0 0
T40 0 77 0 0
T56 0 11 0 0
T59 0 1 0 0
T87 0 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 7271325 7698 0 0
T1 509 1 0 0
T2 486 0 0 0
T3 481 0 0 0
T4 666 0 0 0
T7 0 1 0 0
T11 0 80 0 0
T12 747 0 0 0
T13 523 0 0 0
T14 412 0 0 0
T15 423 0 0 0
T16 1038 0 0 0
T17 426 0 0 0
T21 0 11 0 0
T29 0 1 0 0
T30 0 65 0 0
T40 0 77 0 0
T56 0 11 0 0
T59 0 1 0 0
T87 0 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00

30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin 31 1/1 if (!rst_src_ni) begin Tests: T1 T2 T4  32 1/1 src_level <= 1'b0; Tests: T1 T2 T4  33 end else begin 34 1/1 src_level <= src_level ^ src_pulse_i; Tests: T1 T2 T4  35 end 36 end 37 38 39 // source active must come far enough such that the destination domain has time 40 // to create a valid pulse. 41 `ifdef INC_ASSERT 42 //VCS coverage off 43 // pragma coverage off 44 45 // source active flag tracks whether there is an ongoing "toggle" event. 46 // Until this toggle event is accepted by the destination domain (negative edge of 47 // of the pulse output), the source side cannot toggle again. 48 logic effective_rst_n; 49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o; 50 51 logic src_active_flag_d, src_active_flag_q; 52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q; 53 54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin 55 unreachable if (!effective_rst_n) begin 56 unreachable src_active_flag_q <= '0; 57 end else begin 58 unreachable src_active_flag_q <= src_active_flag_d; 59 end 60 end 61 62 //VCS coverage on 63 // pragma coverage on 64 65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni) 66 `endif 67 68 ////////////////////////////////////////////////////////// 69 // synchronize level signal to destination clock domain // 70 ////////////////////////////////////////////////////////// 71 logic dst_level; 72 73 prim_flop_2sync #(.Width(1)) prim_flop_2sync ( 74 // source clock domain 75 .d_i (src_level), 76 // destination clock domain 77 .clk_i (clk_dst_i), 78 .rst_ni (rst_dst_ni), 79 .q_o (dst_level) 80 ); 81 82 //////////////////////////////////////// 83 // convert level signal back to pulse // 84 //////////////////////////////////////// 85 logic dst_level_q; 86 87 // delay dst_level by 1 cycle 88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin 89 1/1 if (!rst_dst_ni) begin Tests: T1 T2 T4  90 1/1 dst_level_q <= 1'b0; Tests: T1 T2 T4  91 end else begin 92 1/1 dst_level_q <= dst_level; Tests: T1 T2 T4  93 end 94 end 95 96 // edge detection 97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level; Tests: T11 T21 T30 

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT11,T21,T30
10CoveredT11,T21,T30
11CoveredT11,T21,T30

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT11,T21,T30
10CoveredT11,T21,T30
11CoveredT11,T21,T30

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00


31 if (!rst_src_ni) begin -1- 32 src_level <= 1'b0; ==> 33 end else begin 34 src_level <= src_level ^ src_pulse_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


89 if (!rst_dst_ni) begin -1- 90 dst_level_q <= 1'b0; ==> 91 end else begin 92 dst_level_q <= dst_level; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
DstPulseCheck_A 7271325 7750 0 0
SrcPulseCheck_M 1332231489 7819 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7271325 7750 0 0
T11 30017 80 0 0
T21 0 11 0 0
T30 0 86 0 0
T40 0 80 0 0
T51 1595 0 0 0
T56 0 11 0 0
T58 692 0 0 0
T59 509 0 0 0
T60 773 0 0 0
T75 492 0 0 0
T84 507 0 0 0
T88 0 62 0 0
T89 0 51 0 0
T90 0 51 0 0
T91 0 65 0 0
T92 0 82 0 0
T93 425 0 0 0
T94 8443 0 0 0
T95 448 0 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 1332231489 7819 0 0
T11 750449 80 0 0
T21 0 11 0 0
T30 0 86 0 0
T40 0 80 0 0
T51 103734 0 0 0
T56 0 11 0 0
T58 342709 0 0 0
T59 68785 0 0 0
T60 46454 0 0 0
T75 243533 0 0 0
T84 63404 0 0 0
T88 0 62 0 0
T89 0 51 0 0
T90 0 51 0 0
T91 0 65 0 0
T92 0 82 0 0
T93 51059 0 0 0
T94 844352 0 0 0
T95 53819 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00

30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin 31 1/1 if (!rst_src_ni) begin Tests: T1 T2 T4  32 1/1 src_level <= 1'b0; Tests: T1 T2 T4  33 end else begin 34 1/1 src_level <= src_level ^ src_pulse_i; Tests: T1 T2 T4  35 end 36 end 37 38 39 // source active must come far enough such that the destination domain has time 40 // to create a valid pulse. 41 `ifdef INC_ASSERT 42 //VCS coverage off 43 // pragma coverage off 44 45 // source active flag tracks whether there is an ongoing "toggle" event. 46 // Until this toggle event is accepted by the destination domain (negative edge of 47 // of the pulse output), the source side cannot toggle again. 48 logic effective_rst_n; 49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o; 50 51 logic src_active_flag_d, src_active_flag_q; 52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q; 53 54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin 55 unreachable if (!effective_rst_n) begin 56 unreachable src_active_flag_q <= '0; 57 end else begin 58 unreachable src_active_flag_q <= src_active_flag_d; 59 end 60 end 61 62 //VCS coverage on 63 // pragma coverage on 64 65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni) 66 `endif 67 68 ////////////////////////////////////////////////////////// 69 // synchronize level signal to destination clock domain // 70 ////////////////////////////////////////////////////////// 71 logic dst_level; 72 73 prim_flop_2sync #(.Width(1)) prim_flop_2sync ( 74 // source clock domain 75 .d_i (src_level), 76 // destination clock domain 77 .clk_i (clk_dst_i), 78 .rst_ni (rst_dst_ni), 79 .q_o (dst_level) 80 ); 81 82 //////////////////////////////////////// 83 // convert level signal back to pulse // 84 //////////////////////////////////////// 85 logic dst_level_q; 86 87 // delay dst_level by 1 cycle 88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin 89 1/1 if (!rst_dst_ni) begin Tests: T1 T2 T4  90 1/1 dst_level_q <= 1'b0; Tests: T1 T2 T4  91 end else begin 92 1/1 dst_level_q <= dst_level; Tests: T1 T2 T4  93 end 94 end 95 96 // edge detection 97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level; Tests: T1 T2 T4 

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT11,T21,T30
10CoveredT11,T21,T30
11CoveredT11,T21,T30

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT11,T21,T30
10CoveredT11,T21,T30
11CoveredT11,T21,T30

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00


31 if (!rst_src_ni) begin -1- 32 src_level <= 1'b0; ==> 33 end else begin 34 src_level <= src_level ^ src_pulse_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


89 if (!rst_dst_ni) begin -1- 90 dst_level_q <= 1'b0; ==> 91 end else begin 92 dst_level_q <= dst_level; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
DstPulseCheck_A 1332231489 7816 0 0
SrcPulseCheck_M 7271325 7816 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1332231489 7816 0 0
T11 750449 80 0 0
T21 0 11 0 0
T30 0 86 0 0
T40 0 80 0 0
T51 103734 0 0 0
T56 0 11 0 0
T58 342709 0 0 0
T59 68785 0 0 0
T60 46454 0 0 0
T75 243533 0 0 0
T84 63404 0 0 0
T88 0 62 0 0
T89 0 51 0 0
T90 0 51 0 0
T91 0 65 0 0
T92 0 82 0 0
T93 51059 0 0 0
T94 844352 0 0 0
T95 53819 0 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 7271325 7816 0 0
T11 30017 80 0 0
T21 0 11 0 0
T30 0 86 0 0
T40 0 80 0 0
T51 1595 0 0 0
T56 0 11 0 0
T58 692 0 0 0
T59 509 0 0 0
T60 773 0 0 0
T75 492 0 0 0
T84 507 0 0 0
T88 0 62 0 0
T89 0 51 0 0
T90 0 51 0 0
T91 0 65 0 0
T92 0 82 0 0
T93 425 0 0 0
T94 8443 0 0 0
T95 448 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00

30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin 31 1/1 if (!rst_src_ni) begin Tests: T1 T2 T4  32 1/1 src_level <= 1'b0; Tests: T1 T2 T4  33 end else begin 34 1/1 src_level <= src_level ^ src_pulse_i; Tests: T1 T2 T4  35 end 36 end 37 38 39 // source active must come far enough such that the destination domain has time 40 // to create a valid pulse. 41 `ifdef INC_ASSERT 42 //VCS coverage off 43 // pragma coverage off 44 45 // source active flag tracks whether there is an ongoing "toggle" event. 46 // Until this toggle event is accepted by the destination domain (negative edge of 47 // of the pulse output), the source side cannot toggle again. 48 logic effective_rst_n; 49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o; 50 51 logic src_active_flag_d, src_active_flag_q; 52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q; 53 54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin 55 unreachable if (!effective_rst_n) begin 56 unreachable src_active_flag_q <= '0; 57 end else begin 58 unreachable src_active_flag_q <= src_active_flag_d; 59 end 60 end 61 62 //VCS coverage on 63 // pragma coverage on 64 65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni) 66 `endif 67 68 ////////////////////////////////////////////////////////// 69 // synchronize level signal to destination clock domain // 70 ////////////////////////////////////////////////////////// 71 logic dst_level; 72 73 prim_flop_2sync #(.Width(1)) prim_flop_2sync ( 74 // source clock domain 75 .d_i (src_level), 76 // destination clock domain 77 .clk_i (clk_dst_i), 78 .rst_ni (rst_dst_ni), 79 .q_o (dst_level) 80 ); 81 82 //////////////////////////////////////// 83 // convert level signal back to pulse // 84 //////////////////////////////////////// 85 logic dst_level_q; 86 87 // delay dst_level by 1 cycle 88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin 89 1/1 if (!rst_dst_ni) begin Tests: T1 T2 T4  90 1/1 dst_level_q <= 1'b0; Tests: T1 T2 T4  91 end else begin 92 1/1 dst_level_q <= dst_level; Tests: T1 T2 T4  93 end 94 end 95 96 // edge detection 97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level; Tests: T11 T21 T30 

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT11,T21,T30
10CoveredT11,T21,T30
11CoveredT11,T21,T30

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT11,T21,T30
10CoveredT11,T21,T30
11CoveredT11,T21,T30

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00


31 if (!rst_src_ni) begin -1- 32 src_level <= 1'b0; ==> 33 end else begin 34 src_level <= src_level ^ src_pulse_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


89 if (!rst_dst_ni) begin -1- 90 dst_level_q <= 1'b0; ==> 91 end else begin 92 dst_level_q <= dst_level; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
DstPulseCheck_A 7271325 7657 0 0
SrcPulseCheck_M 1332231489 7727 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7271325 7657 0 0
T11 30017 62 0 0
T21 0 11 0 0
T30 0 59 0 0
T40 0 77 0 0
T51 1595 0 0 0
T56 0 11 0 0
T58 692 0 0 0
T59 509 0 0 0
T60 773 0 0 0
T75 492 0 0 0
T84 507 0 0 0
T88 0 74 0 0
T89 0 51 0 0
T90 0 51 0 0
T91 0 73 0 0
T92 0 71 0 0
T93 425 0 0 0
T94 8443 0 0 0
T95 448 0 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 1332231489 7727 0 0
T11 750449 62 0 0
T21 0 11 0 0
T30 0 59 0 0
T40 0 77 0 0
T51 103734 0 0 0
T56 0 11 0 0
T58 342709 0 0 0
T59 68785 0 0 0
T60 46454 0 0 0
T75 243533 0 0 0
T84 63404 0 0 0
T88 0 74 0 0
T89 0 51 0 0
T90 0 51 0 0
T91 0 73 0 0
T92 0 71 0 0
T93 51059 0 0 0
T94 844352 0 0 0
T95 53819 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00

30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin 31 1/1 if (!rst_src_ni) begin Tests: T1 T2 T4  32 1/1 src_level <= 1'b0; Tests: T1 T2 T4  33 end else begin 34 1/1 src_level <= src_level ^ src_pulse_i; Tests: T1 T2 T4  35 end 36 end 37 38 39 // source active must come far enough such that the destination domain has time 40 // to create a valid pulse. 41 `ifdef INC_ASSERT 42 //VCS coverage off 43 // pragma coverage off 44 45 // source active flag tracks whether there is an ongoing "toggle" event. 46 // Until this toggle event is accepted by the destination domain (negative edge of 47 // of the pulse output), the source side cannot toggle again. 48 logic effective_rst_n; 49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o; 50 51 logic src_active_flag_d, src_active_flag_q; 52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q; 53 54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin 55 unreachable if (!effective_rst_n) begin 56 unreachable src_active_flag_q <= '0; 57 end else begin 58 unreachable src_active_flag_q <= src_active_flag_d; 59 end 60 end 61 62 //VCS coverage on 63 // pragma coverage on 64 65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni) 66 `endif 67 68 ////////////////////////////////////////////////////////// 69 // synchronize level signal to destination clock domain // 70 ////////////////////////////////////////////////////////// 71 logic dst_level; 72 73 prim_flop_2sync #(.Width(1)) prim_flop_2sync ( 74 // source clock domain 75 .d_i (src_level), 76 // destination clock domain 77 .clk_i (clk_dst_i), 78 .rst_ni (rst_dst_ni), 79 .q_o (dst_level) 80 ); 81 82 //////////////////////////////////////// 83 // convert level signal back to pulse // 84 //////////////////////////////////////// 85 logic dst_level_q; 86 87 // delay dst_level by 1 cycle 88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin 89 1/1 if (!rst_dst_ni) begin Tests: T1 T2 T4  90 1/1 dst_level_q <= 1'b0; Tests: T1 T2 T4  91 end else begin 92 1/1 dst_level_q <= dst_level; Tests: T1 T2 T4  93 end 94 end 95 96 // edge detection 97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level; Tests: T1 T2 T4 

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT11,T21,T30
10CoveredT11,T21,T30
11CoveredT11,T21,T30

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT11,T21,T30
10CoveredT11,T21,T30
11CoveredT11,T21,T30

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00


31 if (!rst_src_ni) begin -1- 32 src_level <= 1'b0; ==> 33 end else begin 34 src_level <= src_level ^ src_pulse_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


89 if (!rst_dst_ni) begin -1- 90 dst_level_q <= 1'b0; ==> 91 end else begin 92 dst_level_q <= dst_level; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
DstPulseCheck_A 1332231489 7723 0 0
SrcPulseCheck_M 7271325 7723 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1332231489 7723 0 0
T11 750449 62 0 0
T21 0 11 0 0
T30 0 59 0 0
T40 0 77 0 0
T51 103734 0 0 0
T56 0 11 0 0
T58 342709 0 0 0
T59 68785 0 0 0
T60 46454 0 0 0
T75 243533 0 0 0
T84 63404 0 0 0
T88 0 74 0 0
T89 0 51 0 0
T90 0 51 0 0
T91 0 73 0 0
T92 0 71 0 0
T93 51059 0 0 0
T94 844352 0 0 0
T95 53819 0 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 7271325 7723 0 0
T11 30017 62 0 0
T21 0 11 0 0
T30 0 59 0 0
T40 0 77 0 0
T51 1595 0 0 0
T56 0 11 0 0
T58 692 0 0 0
T59 509 0 0 0
T60 773 0 0 0
T75 492 0 0 0
T84 507 0 0 0
T88 0 74 0 0
T89 0 51 0 0
T90 0 51 0 0
T91 0 73 0 0
T92 0 71 0 0
T93 425 0 0 0
T94 8443 0 0 0
T95 448 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00

30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin 31 1/1 if (!rst_src_ni) begin Tests: T1 T2 T4  32 1/1 src_level <= 1'b0; Tests: T1 T2 T4  33 end else begin 34 1/1 src_level <= src_level ^ src_pulse_i; Tests: T1 T2 T4  35 end 36 end 37 38 39 // source active must come far enough such that the destination domain has time 40 // to create a valid pulse. 41 `ifdef INC_ASSERT 42 //VCS coverage off 43 // pragma coverage off 44 45 // source active flag tracks whether there is an ongoing "toggle" event. 46 // Until this toggle event is accepted by the destination domain (negative edge of 47 // of the pulse output), the source side cannot toggle again. 48 logic effective_rst_n; 49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o; 50 51 logic src_active_flag_d, src_active_flag_q; 52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q; 53 54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin 55 unreachable if (!effective_rst_n) begin 56 unreachable src_active_flag_q <= '0; 57 end else begin 58 unreachable src_active_flag_q <= src_active_flag_d; 59 end 60 end 61 62 //VCS coverage on 63 // pragma coverage on 64 65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni) 66 `endif 67 68 ////////////////////////////////////////////////////////// 69 // synchronize level signal to destination clock domain // 70 ////////////////////////////////////////////////////////// 71 logic dst_level; 72 73 prim_flop_2sync #(.Width(1)) prim_flop_2sync ( 74 // source clock domain 75 .d_i (src_level), 76 // destination clock domain 77 .clk_i (clk_dst_i), 78 .rst_ni (rst_dst_ni), 79 .q_o (dst_level) 80 ); 81 82 //////////////////////////////////////// 83 // convert level signal back to pulse // 84 //////////////////////////////////////// 85 logic dst_level_q; 86 87 // delay dst_level by 1 cycle 88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin 89 1/1 if (!rst_dst_ni) begin Tests: T1 T2 T4  90 1/1 dst_level_q <= 1'b0; Tests: T1 T2 T4  91 end else begin 92 1/1 dst_level_q <= dst_level; Tests: T1 T2 T4  93 end 94 end 95 96 // edge detection 97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level; Tests: T11 T21 T30 

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT11,T21,T30
10CoveredT11,T21,T30
11CoveredT11,T21,T30

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT11,T21,T30
10CoveredT11,T21,T30
11CoveredT11,T21,T30

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00


31 if (!rst_src_ni) begin -1- 32 src_level <= 1'b0; ==> 33 end else begin 34 src_level <= src_level ^ src_pulse_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


89 if (!rst_dst_ni) begin -1- 90 dst_level_q <= 1'b0; ==> 91 end else begin 92 dst_level_q <= dst_level; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
DstPulseCheck_A 7271325 7717 0 0
SrcPulseCheck_M 1332231489 7789 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7271325 7717 0 0
T11 30017 80 0 0
T21 0 11 0 0
T30 0 86 0 0
T40 0 95 0 0
T51 1595 0 0 0
T56 0 11 0 0
T58 692 0 0 0
T59 509 0 0 0
T60 773 0 0 0
T75 492 0 0 0
T84 507 0 0 0
T88 0 84 0 0
T89 0 51 0 0
T90 0 51 0 0
T91 0 73 0 0
T92 0 71 0 0
T93 425 0 0 0
T94 8443 0 0 0
T95 448 0 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 1332231489 7789 0 0
T11 750449 80 0 0
T21 0 11 0 0
T30 0 86 0 0
T40 0 95 0 0
T51 103734 0 0 0
T56 0 11 0 0
T58 342709 0 0 0
T59 68785 0 0 0
T60 46454 0 0 0
T75 243533 0 0 0
T84 63404 0 0 0
T88 0 84 0 0
T89 0 51 0 0
T90 0 51 0 0
T91 0 73 0 0
T92 0 71 0 0
T93 51059 0 0 0
T94 844352 0 0 0
T95 53819 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00

30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin 31 1/1 if (!rst_src_ni) begin Tests: T1 T2 T4  32 1/1 src_level <= 1'b0; Tests: T1 T2 T4  33 end else begin 34 1/1 src_level <= src_level ^ src_pulse_i; Tests: T1 T2 T4  35 end 36 end 37 38 39 // source active must come far enough such that the destination domain has time 40 // to create a valid pulse. 41 `ifdef INC_ASSERT 42 //VCS coverage off 43 // pragma coverage off 44 45 // source active flag tracks whether there is an ongoing "toggle" event. 46 // Until this toggle event is accepted by the destination domain (negative edge of 47 // of the pulse output), the source side cannot toggle again. 48 logic effective_rst_n; 49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o; 50 51 logic src_active_flag_d, src_active_flag_q; 52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q; 53 54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin 55 unreachable if (!effective_rst_n) begin 56 unreachable src_active_flag_q <= '0; 57 end else begin 58 unreachable src_active_flag_q <= src_active_flag_d; 59 end 60 end 61 62 //VCS coverage on 63 // pragma coverage on 64 65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni) 66 `endif 67 68 ////////////////////////////////////////////////////////// 69 // synchronize level signal to destination clock domain // 70 ////////////////////////////////////////////////////////// 71 logic dst_level; 72 73 prim_flop_2sync #(.Width(1)) prim_flop_2sync ( 74 // source clock domain 75 .d_i (src_level), 76 // destination clock domain 77 .clk_i (clk_dst_i), 78 .rst_ni (rst_dst_ni), 79 .q_o (dst_level) 80 ); 81 82 //////////////////////////////////////// 83 // convert level signal back to pulse // 84 //////////////////////////////////////// 85 logic dst_level_q; 86 87 // delay dst_level by 1 cycle 88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin 89 1/1 if (!rst_dst_ni) begin Tests: T1 T2 T4  90 1/1 dst_level_q <= 1'b0; Tests: T1 T2 T4  91 end else begin 92 1/1 dst_level_q <= dst_level; Tests: T1 T2 T4  93 end 94 end 95 96 // edge detection 97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level; Tests: T1 T2 T4 

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT11,T21,T30
10CoveredT11,T21,T30
11CoveredT11,T21,T30

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT11,T21,T30
10CoveredT11,T21,T30
11CoveredT11,T21,T30

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00


31 if (!rst_src_ni) begin -1- 32 src_level <= 1'b0; ==> 33 end else begin 34 src_level <= src_level ^ src_pulse_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


89 if (!rst_dst_ni) begin -1- 90 dst_level_q <= 1'b0; ==> 91 end else begin 92 dst_level_q <= dst_level; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
DstPulseCheck_A 1332231489 7784 0 0
SrcPulseCheck_M 7271325 7784 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1332231489 7784 0 0
T11 750449 80 0 0
T21 0 11 0 0
T30 0 86 0 0
T40 0 95 0 0
T51 103734 0 0 0
T56 0 11 0 0
T58 342709 0 0 0
T59 68785 0 0 0
T60 46454 0 0 0
T75 243533 0 0 0
T84 63404 0 0 0
T88 0 84 0 0
T89 0 51 0 0
T90 0 51 0 0
T91 0 73 0 0
T92 0 71 0 0
T93 51059 0 0 0
T94 844352 0 0 0
T95 53819 0 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 7271325 7784 0 0
T11 30017 80 0 0
T21 0 11 0 0
T30 0 86 0 0
T40 0 95 0 0
T51 1595 0 0 0
T56 0 11 0 0
T58 692 0 0 0
T59 509 0 0 0
T60 773 0 0 0
T75 492 0 0 0
T84 507 0 0 0
T88 0 84 0 0
T89 0 51 0 0
T90 0 51 0 0
T91 0 73 0 0
T92 0 71 0 0
T93 425 0 0 0
T94 8443 0 0 0
T95 448 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00

30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin 31 1/1 if (!rst_src_ni) begin Tests: T1 T2 T4  32 1/1 src_level <= 1'b0; Tests: T1 T2 T4  33 end else begin 34 1/1 src_level <= src_level ^ src_pulse_i; Tests: T1 T2 T4  35 end 36 end 37 38 39 // source active must come far enough such that the destination domain has time 40 // to create a valid pulse. 41 `ifdef INC_ASSERT 42 //VCS coverage off 43 // pragma coverage off 44 45 // source active flag tracks whether there is an ongoing "toggle" event. 46 // Until this toggle event is accepted by the destination domain (negative edge of 47 // of the pulse output), the source side cannot toggle again. 48 logic effective_rst_n; 49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o; 50 51 logic src_active_flag_d, src_active_flag_q; 52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q; 53 54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin 55 unreachable if (!effective_rst_n) begin 56 unreachable src_active_flag_q <= '0; 57 end else begin 58 unreachable src_active_flag_q <= src_active_flag_d; 59 end 60 end 61 62 //VCS coverage on 63 // pragma coverage on 64 65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni) 66 `endif 67 68 ////////////////////////////////////////////////////////// 69 // synchronize level signal to destination clock domain // 70 ////////////////////////////////////////////////////////// 71 logic dst_level; 72 73 prim_flop_2sync #(.Width(1)) prim_flop_2sync ( 74 // source clock domain 75 .d_i (src_level), 76 // destination clock domain 77 .clk_i (clk_dst_i), 78 .rst_ni (rst_dst_ni), 79 .q_o (dst_level) 80 ); 81 82 //////////////////////////////////////// 83 // convert level signal back to pulse // 84 //////////////////////////////////////// 85 logic dst_level_q; 86 87 // delay dst_level by 1 cycle 88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin 89 1/1 if (!rst_dst_ni) begin Tests: T1 T2 T4  90 1/1 dst_level_q <= 1'b0; Tests: T1 T2 T4  91 end else begin 92 1/1 dst_level_q <= dst_level; Tests: T1 T2 T4  93 end 94 end 95 96 // edge detection 97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level; Tests: T1 T7 T29 

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT1,T7,T29
10CoveredT1,T7,T29
11CoveredT21,T56,T34

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT1,T7,T29
10CoveredT21,T56,T34
11CoveredT1,T7,T29

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00


31 if (!rst_src_ni) begin -1- 32 src_level <= 1'b0; ==> 33 end else begin 34 src_level <= src_level ^ src_pulse_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


89 if (!rst_dst_ni) begin -1- 90 dst_level_q <= 1'b0; ==> 91 end else begin 92 dst_level_q <= dst_level; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
DstPulseCheck_A 7271325 1342 0 0
SrcPulseCheck_M 1332231489 1409 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7271325 1342 0 0
T1 509 1 0 0
T2 486 0 0 0
T3 481 0 0 0
T4 666 0 0 0
T7 0 1 0 0
T11 0 12 0 0
T12 747 0 0 0
T13 523 0 0 0
T14 412 0 0 0
T15 423 0 0 0
T16 1038 0 0 0
T17 426 0 0 0
T21 0 9 0 0
T29 0 1 0 0
T30 0 2 0 0
T40 0 10 0 0
T56 0 9 0 0
T59 0 1 0 0
T87 0 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 1332231489 1409 0 0
T1 63648 1 0 0
T2 58317 0 0 0
T3 215595 0 0 0
T4 43326 0 0 0
T7 0 1 0 0
T11 0 12 0 0
T12 18956 0 0 0
T13 128352 0 0 0
T14 195910 0 0 0
T15 101494 0 0 0
T16 129820 0 0 0
T17 51227 0 0 0
T21 0 9 0 0
T29 0 1 0 0
T30 0 2 0 0
T40 0 10 0 0
T56 0 9 0 0
T59 0 1 0 0
T87 0 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00

30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin 31 1/1 if (!rst_src_ni) begin Tests: T1 T2 T4  32 1/1 src_level <= 1'b0; Tests: T1 T2 T4  33 end else begin 34 1/1 src_level <= src_level ^ src_pulse_i; Tests: T1 T2 T4  35 end 36 end 37 38 39 // source active must come far enough such that the destination domain has time 40 // to create a valid pulse. 41 `ifdef INC_ASSERT 42 //VCS coverage off 43 // pragma coverage off 44 45 // source active flag tracks whether there is an ongoing "toggle" event. 46 // Until this toggle event is accepted by the destination domain (negative edge of 47 // of the pulse output), the source side cannot toggle again. 48 logic effective_rst_n; 49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o; 50 51 logic src_active_flag_d, src_active_flag_q; 52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q; 53 54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin 55 unreachable if (!effective_rst_n) begin 56 unreachable src_active_flag_q <= '0; 57 end else begin 58 unreachable src_active_flag_q <= src_active_flag_d; 59 end 60 end 61 62 //VCS coverage on 63 // pragma coverage on 64 65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni) 66 `endif 67 68 ////////////////////////////////////////////////////////// 69 // synchronize level signal to destination clock domain // 70 ////////////////////////////////////////////////////////// 71 logic dst_level; 72 73 prim_flop_2sync #(.Width(1)) prim_flop_2sync ( 74 // source clock domain 75 .d_i (src_level), 76 // destination clock domain 77 .clk_i (clk_dst_i), 78 .rst_ni (rst_dst_ni), 79 .q_o (dst_level) 80 ); 81 82 //////////////////////////////////////// 83 // convert level signal back to pulse // 84 //////////////////////////////////////// 85 logic dst_level_q; 86 87 // delay dst_level by 1 cycle 88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin 89 1/1 if (!rst_dst_ni) begin Tests: T1 T2 T4  90 1/1 dst_level_q <= 1'b0; Tests: T1 T2 T4  91 end else begin 92 1/1 dst_level_q <= dst_level; Tests: T1 T2 T4  93 end 94 end 95 96 // edge detection 97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level; Tests: T1 T2 T4 

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT1,T7,T29
10CoveredT1,T7,T29
11CoveredT21,T56,T34

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT1,T7,T29
10CoveredT21,T56,T34
11CoveredT1,T7,T29

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00


31 if (!rst_src_ni) begin -1- 32 src_level <= 1'b0; ==> 33 end else begin 34 src_level <= src_level ^ src_pulse_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


89 if (!rst_dst_ni) begin -1- 90 dst_level_q <= 1'b0; ==> 91 end else begin 92 dst_level_q <= dst_level; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
DstPulseCheck_A 1332231489 1405 0 0
SrcPulseCheck_M 7271325 1405 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1332231489 1405 0 0
T1 63648 1 0 0
T2 58317 0 0 0
T3 215595 0 0 0
T4 43326 0 0 0
T7 0 1 0 0
T11 0 12 0 0
T12 18956 0 0 0
T13 128352 0 0 0
T14 195910 0 0 0
T15 101494 0 0 0
T16 129820 0 0 0
T17 51227 0 0 0
T21 0 9 0 0
T29 0 1 0 0
T30 0 2 0 0
T40 0 10 0 0
T56 0 9 0 0
T59 0 1 0 0
T87 0 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 7271325 1405 0 0
T1 509 1 0 0
T2 486 0 0 0
T3 481 0 0 0
T4 666 0 0 0
T7 0 1 0 0
T11 0 12 0 0
T12 747 0 0 0
T13 523 0 0 0
T14 412 0 0 0
T15 423 0 0 0
T16 1038 0 0 0
T17 426 0 0 0
T21 0 9 0 0
T29 0 1 0 0
T30 0 2 0 0
T40 0 10 0 0
T56 0 9 0 0
T59 0 1 0 0
T87 0 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00

30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin 31 1/1 if (!rst_src_ni) begin Tests: T1 T2 T4  32 1/1 src_level <= 1'b0; Tests: T1 T2 T4  33 end else begin 34 1/1 src_level <= src_level ^ src_pulse_i; Tests: T1 T2 T4  35 end 36 end 37 38 39 // source active must come far enough such that the destination domain has time 40 // to create a valid pulse. 41 `ifdef INC_ASSERT 42 //VCS coverage off 43 // pragma coverage off 44 45 // source active flag tracks whether there is an ongoing "toggle" event. 46 // Until this toggle event is accepted by the destination domain (negative edge of 47 // of the pulse output), the source side cannot toggle again. 48 logic effective_rst_n; 49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o; 50 51 logic src_active_flag_d, src_active_flag_q; 52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q; 53 54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin 55 unreachable if (!effective_rst_n) begin 56 unreachable src_active_flag_q <= '0; 57 end else begin 58 unreachable src_active_flag_q <= src_active_flag_d; 59 end 60 end 61 62 //VCS coverage on 63 // pragma coverage on 64 65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni) 66 `endif 67 68 ////////////////////////////////////////////////////////// 69 // synchronize level signal to destination clock domain // 70 ////////////////////////////////////////////////////////// 71 logic dst_level; 72 73 prim_flop_2sync #(.Width(1)) prim_flop_2sync ( 74 // source clock domain 75 .d_i (src_level), 76 // destination clock domain 77 .clk_i (clk_dst_i), 78 .rst_ni (rst_dst_ni), 79 .q_o (dst_level) 80 ); 81 82 //////////////////////////////////////// 83 // convert level signal back to pulse // 84 //////////////////////////////////////// 85 logic dst_level_q; 86 87 // delay dst_level by 1 cycle 88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin 89 1/1 if (!rst_dst_ni) begin Tests: T1 T2 T4  90 1/1 dst_level_q <= 1'b0; Tests: T1 T2 T4  91 end else begin 92 1/1 dst_level_q <= dst_level; Tests: T1 T2 T4  93 end 94 end 95 96 // edge detection 97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level; Tests: T11 T21 T30 

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT11,T21,T30
10CoveredT11,T21,T30
11CoveredT21,T56,T34

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT11,T21,T30
10CoveredT21,T56,T34
11CoveredT11,T21,T30

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00


31 if (!rst_src_ni) begin -1- 32 src_level <= 1'b0; ==> 33 end else begin 34 src_level <= src_level ^ src_pulse_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


89 if (!rst_dst_ni) begin -1- 90 dst_level_q <= 1'b0; ==> 91 end else begin 92 dst_level_q <= dst_level; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
DstPulseCheck_A 7271325 1350 0 0
SrcPulseCheck_M 1332231489 1418 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7271325 1350 0 0
T11 30017 12 0 0
T21 0 9 0 0
T30 0 2 0 0
T40 0 10 0 0
T51 1595 0 0 0
T56 0 9 0 0
T58 692 0 0 0
T59 509 0 0 0
T60 773 0 0 0
T75 492 0 0 0
T84 507 0 0 0
T88 0 7 0 0
T89 0 1 0 0
T90 0 1 0 0
T91 0 6 0 0
T92 0 5 0 0
T93 425 0 0 0
T94 8443 0 0 0
T95 448 0 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 1332231489 1418 0 0
T11 750449 12 0 0
T21 0 9 0 0
T30 0 2 0 0
T40 0 10 0 0
T51 103734 0 0 0
T56 0 9 0 0
T58 342709 0 0 0
T59 68785 0 0 0
T60 46454 0 0 0
T75 243533 0 0 0
T84 63404 0 0 0
T88 0 7 0 0
T89 0 1 0 0
T90 0 1 0 0
T91 0 6 0 0
T92 0 5 0 0
T93 51059 0 0 0
T94 844352 0 0 0
T95 53819 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00

30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin 31 1/1 if (!rst_src_ni) begin Tests: T1 T2 T4  32 1/1 src_level <= 1'b0; Tests: T1 T2 T4  33 end else begin 34 1/1 src_level <= src_level ^ src_pulse_i; Tests: T1 T2 T4  35 end 36 end 37 38 39 // source active must come far enough such that the destination domain has time 40 // to create a valid pulse. 41 `ifdef INC_ASSERT 42 //VCS coverage off 43 // pragma coverage off 44 45 // source active flag tracks whether there is an ongoing "toggle" event. 46 // Until this toggle event is accepted by the destination domain (negative edge of 47 // of the pulse output), the source side cannot toggle again. 48 logic effective_rst_n; 49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o; 50 51 logic src_active_flag_d, src_active_flag_q; 52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q; 53 54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin 55 unreachable if (!effective_rst_n) begin 56 unreachable src_active_flag_q <= '0; 57 end else begin 58 unreachable src_active_flag_q <= src_active_flag_d; 59 end 60 end 61 62 //VCS coverage on 63 // pragma coverage on 64 65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni) 66 `endif 67 68 ////////////////////////////////////////////////////////// 69 // synchronize level signal to destination clock domain // 70 ////////////////////////////////////////////////////////// 71 logic dst_level; 72 73 prim_flop_2sync #(.Width(1)) prim_flop_2sync ( 74 // source clock domain 75 .d_i (src_level), 76 // destination clock domain 77 .clk_i (clk_dst_i), 78 .rst_ni (rst_dst_ni), 79 .q_o (dst_level) 80 ); 81 82 //////////////////////////////////////// 83 // convert level signal back to pulse // 84 //////////////////////////////////////// 85 logic dst_level_q; 86 87 // delay dst_level by 1 cycle 88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin 89 1/1 if (!rst_dst_ni) begin Tests: T1 T2 T4  90 1/1 dst_level_q <= 1'b0; Tests: T1 T2 T4  91 end else begin 92 1/1 dst_level_q <= dst_level; Tests: T1 T2 T4  93 end 94 end 95 96 // edge detection 97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level; Tests: T1 T2 T4 

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT11,T21,T30
10CoveredT11,T21,T30
11CoveredT21,T56,T34

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT11,T21,T30
10CoveredT21,T56,T34
11CoveredT11,T21,T30

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00


31 if (!rst_src_ni) begin -1- 32 src_level <= 1'b0; ==> 33 end else begin 34 src_level <= src_level ^ src_pulse_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


89 if (!rst_dst_ni) begin -1- 90 dst_level_q <= 1'b0; ==> 91 end else begin 92 dst_level_q <= dst_level; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
DstPulseCheck_A 1332231489 1414 0 0
SrcPulseCheck_M 7271325 1414 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1332231489 1414 0 0
T11 750449 12 0 0
T21 0 9 0 0
T30 0 2 0 0
T40 0 10 0 0
T51 103734 0 0 0
T56 0 9 0 0
T58 342709 0 0 0
T59 68785 0 0 0
T60 46454 0 0 0
T75 243533 0 0 0
T84 63404 0 0 0
T88 0 7 0 0
T89 0 1 0 0
T90 0 1 0 0
T91 0 6 0 0
T92 0 5 0 0
T93 51059 0 0 0
T94 844352 0 0 0
T95 53819 0 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 7271325 1414 0 0
T11 30017 12 0 0
T21 0 9 0 0
T30 0 2 0 0
T40 0 10 0 0
T51 1595 0 0 0
T56 0 9 0 0
T58 692 0 0 0
T59 509 0 0 0
T60 773 0 0 0
T75 492 0 0 0
T84 507 0 0 0
T88 0 7 0 0
T89 0 1 0 0
T90 0 1 0 0
T91 0 6 0 0
T92 0 5 0 0
T93 425 0 0 0
T94 8443 0 0 0
T95 448 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00

30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin 31 1/1 if (!rst_src_ni) begin Tests: T1 T2 T4  32 1/1 src_level <= 1'b0; Tests: T1 T2 T4  33 end else begin 34 1/1 src_level <= src_level ^ src_pulse_i; Tests: T1 T2 T4  35 end 36 end 37 38 39 // source active must come far enough such that the destination domain has time 40 // to create a valid pulse. 41 `ifdef INC_ASSERT 42 //VCS coverage off 43 // pragma coverage off 44 45 // source active flag tracks whether there is an ongoing "toggle" event. 46 // Until this toggle event is accepted by the destination domain (negative edge of 47 // of the pulse output), the source side cannot toggle again. 48 logic effective_rst_n; 49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o; 50 51 logic src_active_flag_d, src_active_flag_q; 52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q; 53 54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin 55 unreachable if (!effective_rst_n) begin 56 unreachable src_active_flag_q <= '0; 57 end else begin 58 unreachable src_active_flag_q <= src_active_flag_d; 59 end 60 end 61 62 //VCS coverage on 63 // pragma coverage on 64 65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni) 66 `endif 67 68 ////////////////////////////////////////////////////////// 69 // synchronize level signal to destination clock domain // 70 ////////////////////////////////////////////////////////// 71 logic dst_level; 72 73 prim_flop_2sync #(.Width(1)) prim_flop_2sync ( 74 // source clock domain 75 .d_i (src_level), 76 // destination clock domain 77 .clk_i (clk_dst_i), 78 .rst_ni (rst_dst_ni), 79 .q_o (dst_level) 80 ); 81 82 //////////////////////////////////////// 83 // convert level signal back to pulse // 84 //////////////////////////////////////// 85 logic dst_level_q; 86 87 // delay dst_level by 1 cycle 88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin 89 1/1 if (!rst_dst_ni) begin Tests: T1 T2 T4  90 1/1 dst_level_q <= 1'b0; Tests: T1 T2 T4  91 end else begin 92 1/1 dst_level_q <= dst_level; Tests: T1 T2 T4  93 end 94 end 95 96 // edge detection 97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level; Tests: T11 T21 T30 

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT11,T21,T30
10CoveredT11,T21,T30
11CoveredT21,T56,T34

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT11,T21,T30
10CoveredT21,T56,T34
11CoveredT11,T21,T30

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00


31 if (!rst_src_ni) begin -1- 32 src_level <= 1'b0; ==> 33 end else begin 34 src_level <= src_level ^ src_pulse_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


89 if (!rst_dst_ni) begin -1- 90 dst_level_q <= 1'b0; ==> 91 end else begin 92 dst_level_q <= dst_level; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
DstPulseCheck_A 7271325 1392 0 0
SrcPulseCheck_M 1332231489 1458 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7271325 1392 0 0
T11 30017 12 0 0
T21 0 9 0 0
T30 0 2 0 0
T40 0 10 0 0
T51 1595 0 0 0
T56 0 9 0 0
T58 692 0 0 0
T59 509 0 0 0
T60 773 0 0 0
T75 492 0 0 0
T84 507 0 0 0
T88 0 7 0 0
T89 0 1 0 0
T90 0 1 0 0
T91 0 6 0 0
T92 0 5 0 0
T93 425 0 0 0
T94 8443 0 0 0
T95 448 0 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 1332231489 1458 0 0
T11 750449 12 0 0
T21 0 9 0 0
T30 0 2 0 0
T40 0 10 0 0
T51 103734 0 0 0
T56 0 9 0 0
T58 342709 0 0 0
T59 68785 0 0 0
T60 46454 0 0 0
T75 243533 0 0 0
T84 63404 0 0 0
T88 0 7 0 0
T89 0 1 0 0
T90 0 1 0 0
T91 0 6 0 0
T92 0 5 0 0
T93 51059 0 0 0
T94 844352 0 0 0
T95 53819 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00

30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin 31 1/1 if (!rst_src_ni) begin Tests: T1 T2 T4  32 1/1 src_level <= 1'b0; Tests: T1 T2 T4  33 end else begin 34 1/1 src_level <= src_level ^ src_pulse_i; Tests: T1 T2 T4  35 end 36 end 37 38 39 // source active must come far enough such that the destination domain has time 40 // to create a valid pulse. 41 `ifdef INC_ASSERT 42 //VCS coverage off 43 // pragma coverage off 44 45 // source active flag tracks whether there is an ongoing "toggle" event. 46 // Until this toggle event is accepted by the destination domain (negative edge of 47 // of the pulse output), the source side cannot toggle again. 48 logic effective_rst_n; 49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o; 50 51 logic src_active_flag_d, src_active_flag_q; 52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q; 53 54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin 55 unreachable if (!effective_rst_n) begin 56 unreachable src_active_flag_q <= '0; 57 end else begin 58 unreachable src_active_flag_q <= src_active_flag_d; 59 end 60 end 61 62 //VCS coverage on 63 // pragma coverage on 64 65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni) 66 `endif 67 68 ////////////////////////////////////////////////////////// 69 // synchronize level signal to destination clock domain // 70 ////////////////////////////////////////////////////////// 71 logic dst_level; 72 73 prim_flop_2sync #(.Width(1)) prim_flop_2sync ( 74 // source clock domain 75 .d_i (src_level), 76 // destination clock domain 77 .clk_i (clk_dst_i), 78 .rst_ni (rst_dst_ni), 79 .q_o (dst_level) 80 ); 81 82 //////////////////////////////////////// 83 // convert level signal back to pulse // 84 //////////////////////////////////////// 85 logic dst_level_q; 86 87 // delay dst_level by 1 cycle 88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin 89 1/1 if (!rst_dst_ni) begin Tests: T1 T2 T4  90 1/1 dst_level_q <= 1'b0; Tests: T1 T2 T4  91 end else begin 92 1/1 dst_level_q <= dst_level; Tests: T1 T2 T4  93 end 94 end 95 96 // edge detection 97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level; Tests: T1 T2 T4 

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT11,T21,T30
10CoveredT11,T21,T30
11CoveredT21,T56,T34

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT11,T21,T30
10CoveredT21,T56,T34
11CoveredT11,T21,T30

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00


31 if (!rst_src_ni) begin -1- 32 src_level <= 1'b0; ==> 33 end else begin 34 src_level <= src_level ^ src_pulse_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


89 if (!rst_dst_ni) begin -1- 90 dst_level_q <= 1'b0; ==> 91 end else begin 92 dst_level_q <= dst_level; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
DstPulseCheck_A 1332231489 1453 0 0
SrcPulseCheck_M 7271325 1453 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1332231489 1453 0 0
T11 750449 12 0 0
T21 0 9 0 0
T30 0 2 0 0
T40 0 10 0 0
T51 103734 0 0 0
T56 0 9 0 0
T58 342709 0 0 0
T59 68785 0 0 0
T60 46454 0 0 0
T75 243533 0 0 0
T84 63404 0 0 0
T88 0 7 0 0
T89 0 1 0 0
T90 0 1 0 0
T91 0 6 0 0
T92 0 5 0 0
T93 51059 0 0 0
T94 844352 0 0 0
T95 53819 0 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 7271325 1453 0 0
T11 30017 12 0 0
T21 0 9 0 0
T30 0 2 0 0
T40 0 10 0 0
T51 1595 0 0 0
T56 0 9 0 0
T58 692 0 0 0
T59 509 0 0 0
T60 773 0 0 0
T75 492 0 0 0
T84 507 0 0 0
T88 0 7 0 0
T89 0 1 0 0
T90 0 1 0 0
T91 0 6 0 0
T92 0 5 0 0
T93 425 0 0 0
T94 8443 0 0 0
T95 448 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00

30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin 31 1/1 if (!rst_src_ni) begin Tests: T1 T2 T4  32 1/1 src_level <= 1'b0; Tests: T1 T2 T4  33 end else begin 34 1/1 src_level <= src_level ^ src_pulse_i; Tests: T1 T2 T4  35 end 36 end 37 38 39 // source active must come far enough such that the destination domain has time 40 // to create a valid pulse. 41 `ifdef INC_ASSERT 42 //VCS coverage off 43 // pragma coverage off 44 45 // source active flag tracks whether there is an ongoing "toggle" event. 46 // Until this toggle event is accepted by the destination domain (negative edge of 47 // of the pulse output), the source side cannot toggle again. 48 logic effective_rst_n; 49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o; 50 51 logic src_active_flag_d, src_active_flag_q; 52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q; 53 54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin 55 unreachable if (!effective_rst_n) begin 56 unreachable src_active_flag_q <= '0; 57 end else begin 58 unreachable src_active_flag_q <= src_active_flag_d; 59 end 60 end 61 62 //VCS coverage on 63 // pragma coverage on 64 65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni) 66 `endif 67 68 ////////////////////////////////////////////////////////// 69 // synchronize level signal to destination clock domain // 70 ////////////////////////////////////////////////////////// 71 logic dst_level; 72 73 prim_flop_2sync #(.Width(1)) prim_flop_2sync ( 74 // source clock domain 75 .d_i (src_level), 76 // destination clock domain 77 .clk_i (clk_dst_i), 78 .rst_ni (rst_dst_ni), 79 .q_o (dst_level) 80 ); 81 82 //////////////////////////////////////// 83 // convert level signal back to pulse // 84 //////////////////////////////////////// 85 logic dst_level_q; 86 87 // delay dst_level by 1 cycle 88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin 89 1/1 if (!rst_dst_ni) begin Tests: T1 T2 T4  90 1/1 dst_level_q <= 1'b0; Tests: T1 T2 T4  91 end else begin 92 1/1 dst_level_q <= dst_level; Tests: T1 T2 T4  93 end 94 end 95 96 // edge detection 97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level; Tests: T11 T21 T30 

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT11,T21,T30
10CoveredT11,T21,T30
11CoveredT21,T56,T34

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT11,T21,T30
10CoveredT21,T56,T34
11CoveredT11,T21,T30

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00


31 if (!rst_src_ni) begin -1- 32 src_level <= 1'b0; ==> 33 end else begin 34 src_level <= src_level ^ src_pulse_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


89 if (!rst_dst_ni) begin -1- 90 dst_level_q <= 1'b0; ==> 91 end else begin 92 dst_level_q <= dst_level; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
DstPulseCheck_A 7271325 1359 0 0
SrcPulseCheck_M 1332231489 1426 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7271325 1359 0 0
T11 30017 12 0 0
T21 0 9 0 0
T30 0 2 0 0
T40 0 10 0 0
T51 1595 0 0 0
T56 0 9 0 0
T58 692 0 0 0
T59 509 0 0 0
T60 773 0 0 0
T75 492 0 0 0
T84 507 0 0 0
T88 0 7 0 0
T89 0 1 0 0
T90 0 1 0 0
T91 0 6 0 0
T92 0 5 0 0
T93 425 0 0 0
T94 8443 0 0 0
T95 448 0 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 1332231489 1426 0 0
T11 750449 12 0 0
T21 0 9 0 0
T30 0 2 0 0
T40 0 10 0 0
T51 103734 0 0 0
T56 0 9 0 0
T58 342709 0 0 0
T59 68785 0 0 0
T60 46454 0 0 0
T75 243533 0 0 0
T84 63404 0 0 0
T88 0 7 0 0
T89 0 1 0 0
T90 0 1 0 0
T91 0 6 0 0
T92 0 5 0 0
T93 51059 0 0 0
T94 844352 0 0 0
T95 53819 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00

30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin 31 1/1 if (!rst_src_ni) begin Tests: T1 T2 T4  32 1/1 src_level <= 1'b0; Tests: T1 T2 T4  33 end else begin 34 1/1 src_level <= src_level ^ src_pulse_i; Tests: T1 T2 T4  35 end 36 end 37 38 39 // source active must come far enough such that the destination domain has time 40 // to create a valid pulse. 41 `ifdef INC_ASSERT 42 //VCS coverage off 43 // pragma coverage off 44 45 // source active flag tracks whether there is an ongoing "toggle" event. 46 // Until this toggle event is accepted by the destination domain (negative edge of 47 // of the pulse output), the source side cannot toggle again. 48 logic effective_rst_n; 49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o; 50 51 logic src_active_flag_d, src_active_flag_q; 52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q; 53 54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin 55 unreachable if (!effective_rst_n) begin 56 unreachable src_active_flag_q <= '0; 57 end else begin 58 unreachable src_active_flag_q <= src_active_flag_d; 59 end 60 end 61 62 //VCS coverage on 63 // pragma coverage on 64 65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni) 66 `endif 67 68 ////////////////////////////////////////////////////////// 69 // synchronize level signal to destination clock domain // 70 ////////////////////////////////////////////////////////// 71 logic dst_level; 72 73 prim_flop_2sync #(.Width(1)) prim_flop_2sync ( 74 // source clock domain 75 .d_i (src_level), 76 // destination clock domain 77 .clk_i (clk_dst_i), 78 .rst_ni (rst_dst_ni), 79 .q_o (dst_level) 80 ); 81 82 //////////////////////////////////////// 83 // convert level signal back to pulse // 84 //////////////////////////////////////// 85 logic dst_level_q; 86 87 // delay dst_level by 1 cycle 88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin 89 1/1 if (!rst_dst_ni) begin Tests: T1 T2 T4  90 1/1 dst_level_q <= 1'b0; Tests: T1 T2 T4  91 end else begin 92 1/1 dst_level_q <= dst_level; Tests: T1 T2 T4  93 end 94 end 95 96 // edge detection 97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level; Tests: T1 T2 T4 

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT11,T21,T30
10CoveredT11,T21,T30
11CoveredT21,T56,T34

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT11,T21,T30
10CoveredT21,T56,T34
11CoveredT11,T21,T30

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00


31 if (!rst_src_ni) begin -1- 32 src_level <= 1'b0; ==> 33 end else begin 34 src_level <= src_level ^ src_pulse_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


89 if (!rst_dst_ni) begin -1- 90 dst_level_q <= 1'b0; ==> 91 end else begin 92 dst_level_q <= dst_level; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
DstPulseCheck_A 1332231489 1421 0 0
SrcPulseCheck_M 7271325 1421 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1332231489 1421 0 0
T11 750449 12 0 0
T21 0 9 0 0
T30 0 2 0 0
T40 0 10 0 0
T51 103734 0 0 0
T56 0 9 0 0
T58 342709 0 0 0
T59 68785 0 0 0
T60 46454 0 0 0
T75 243533 0 0 0
T84 63404 0 0 0
T88 0 7 0 0
T89 0 1 0 0
T90 0 1 0 0
T91 0 6 0 0
T92 0 5 0 0
T93 51059 0 0 0
T94 844352 0 0 0
T95 53819 0 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 7271325 1421 0 0
T11 30017 12 0 0
T21 0 9 0 0
T30 0 2 0 0
T40 0 10 0 0
T51 1595 0 0 0
T56 0 9 0 0
T58 692 0 0 0
T59 509 0 0 0
T60 773 0 0 0
T75 492 0 0 0
T84 507 0 0 0
T88 0 7 0 0
T89 0 1 0 0
T90 0 1 0 0
T91 0 6 0 0
T92 0 5 0 0
T93 425 0 0 0
T94 8443 0 0 0
T95 448 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00

30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin 31 1/1 if (!rst_src_ni) begin Tests: T1 T2 T4  32 1/1 src_level <= 1'b0; Tests: T1 T2 T4  33 end else begin 34 1/1 src_level <= src_level ^ src_pulse_i; Tests: T1 T2 T4  35 end 36 end 37 38 39 // source active must come far enough such that the destination domain has time 40 // to create a valid pulse. 41 `ifdef INC_ASSERT 42 //VCS coverage off 43 // pragma coverage off 44 45 // source active flag tracks whether there is an ongoing "toggle" event. 46 // Until this toggle event is accepted by the destination domain (negative edge of 47 // of the pulse output), the source side cannot toggle again. 48 logic effective_rst_n; 49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o; 50 51 logic src_active_flag_d, src_active_flag_q; 52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q; 53 54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin 55 unreachable if (!effective_rst_n) begin 56 unreachable src_active_flag_q <= '0; 57 end else begin 58 unreachable src_active_flag_q <= src_active_flag_d; 59 end 60 end 61 62 //VCS coverage on 63 // pragma coverage on 64 65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni) 66 `endif 67 68 ////////////////////////////////////////////////////////// 69 // synchronize level signal to destination clock domain // 70 ////////////////////////////////////////////////////////// 71 logic dst_level; 72 73 prim_flop_2sync #(.Width(1)) prim_flop_2sync ( 74 // source clock domain 75 .d_i (src_level), 76 // destination clock domain 77 .clk_i (clk_dst_i), 78 .rst_ni (rst_dst_ni), 79 .q_o (dst_level) 80 ); 81 82 //////////////////////////////////////// 83 // convert level signal back to pulse // 84 //////////////////////////////////////// 85 logic dst_level_q; 86 87 // delay dst_level by 1 cycle 88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin 89 1/1 if (!rst_dst_ni) begin Tests: T1 T2 T4  90 1/1 dst_level_q <= 1'b0; Tests: T1 T2 T4  91 end else begin 92 1/1 dst_level_q <= dst_level; Tests: T1 T2 T4  93 end 94 end 95 96 // edge detection 97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level; Tests: T1 T2 T31 

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT1,T2,T31
10CoveredT1,T2,T31
11CoveredT11,T21,T30

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT1,T2,T31
10CoveredT11,T21,T30
11CoveredT1,T2,T31

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00


31 if (!rst_src_ni) begin -1- 32 src_level <= 1'b0; ==> 33 end else begin 34 src_level <= src_level ^ src_pulse_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


89 if (!rst_dst_ni) begin -1- 90 dst_level_q <= 1'b0; ==> 91 end else begin 92 dst_level_q <= dst_level; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
DstPulseCheck_A 7271325 8224 0 0
SrcPulseCheck_M 1332231489 8295 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7271325 8224 0 0
T1 509 1 0 0
T2 486 1 0 0
T3 481 0 0 0
T4 666 0 0 0
T6 0 1 0 0
T7 0 1 0 0
T11 0 80 0 0
T12 747 0 0 0
T13 523 0 0 0
T14 412 0 0 0
T15 423 0 0 0
T16 1038 0 0 0
T17 426 0 0 0
T28 0 1 0 0
T29 0 1 0 0
T31 0 1 0 0
T57 0 1 0 0
T59 0 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 1332231489 8295 0 0
T1 63648 1 0 0
T2 58317 1 0 0
T3 215595 0 0 0
T4 43326 0 0 0
T6 0 1 0 0
T7 0 1 0 0
T11 0 80 0 0
T12 18956 0 0 0
T13 128352 0 0 0
T14 195910 0 0 0
T15 101494 0 0 0
T16 129820 0 0 0
T17 51227 0 0 0
T28 0 1 0 0
T29 0 1 0 0
T31 0 1 0 0
T57 0 1 0 0
T59 0 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00

30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin 31 1/1 if (!rst_src_ni) begin Tests: T1 T2 T4  32 1/1 src_level <= 1'b0; Tests: T1 T2 T4  33 end else begin 34 1/1 src_level <= src_level ^ src_pulse_i; Tests: T1 T2 T4  35 end 36 end 37 38 39 // source active must come far enough such that the destination domain has time 40 // to create a valid pulse. 41 `ifdef INC_ASSERT 42 //VCS coverage off 43 // pragma coverage off 44 45 // source active flag tracks whether there is an ongoing "toggle" event. 46 // Until this toggle event is accepted by the destination domain (negative edge of 47 // of the pulse output), the source side cannot toggle again. 48 logic effective_rst_n; 49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o; 50 51 logic src_active_flag_d, src_active_flag_q; 52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q; 53 54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin 55 unreachable if (!effective_rst_n) begin 56 unreachable src_active_flag_q <= '0; 57 end else begin 58 unreachable src_active_flag_q <= src_active_flag_d; 59 end 60 end 61 62 //VCS coverage on 63 // pragma coverage on 64 65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni) 66 `endif 67 68 ////////////////////////////////////////////////////////// 69 // synchronize level signal to destination clock domain // 70 ////////////////////////////////////////////////////////// 71 logic dst_level; 72 73 prim_flop_2sync #(.Width(1)) prim_flop_2sync ( 74 // source clock domain 75 .d_i (src_level), 76 // destination clock domain 77 .clk_i (clk_dst_i), 78 .rst_ni (rst_dst_ni), 79 .q_o (dst_level) 80 ); 81 82 //////////////////////////////////////// 83 // convert level signal back to pulse // 84 //////////////////////////////////////// 85 logic dst_level_q; 86 87 // delay dst_level by 1 cycle 88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin 89 1/1 if (!rst_dst_ni) begin Tests: T1 T2 T4  90 1/1 dst_level_q <= 1'b0; Tests: T1 T2 T4  91 end else begin 92 1/1 dst_level_q <= dst_level; Tests: T1 T2 T4  93 end 94 end 95 96 // edge detection 97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level; Tests: T1 T2 T4 

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT1,T2,T31
10CoveredT1,T2,T31
11CoveredT11,T21,T30

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT1,T2,T31
10CoveredT11,T21,T30
11CoveredT1,T2,T31

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00


31 if (!rst_src_ni) begin -1- 32 src_level <= 1'b0; ==> 33 end else begin 34 src_level <= src_level ^ src_pulse_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


89 if (!rst_dst_ni) begin -1- 90 dst_level_q <= 1'b0; ==> 91 end else begin 92 dst_level_q <= dst_level; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
DstPulseCheck_A 1332231489 8291 0 0
SrcPulseCheck_M 7271325 8291 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1332231489 8291 0 0
T1 63648 1 0 0
T2 58317 1 0 0
T3 215595 0 0 0
T4 43326 0 0 0
T6 0 1 0 0
T7 0 1 0 0
T11 0 80 0 0
T12 18956 0 0 0
T13 128352 0 0 0
T14 195910 0 0 0
T15 101494 0 0 0
T16 129820 0 0 0
T17 51227 0 0 0
T28 0 1 0 0
T29 0 1 0 0
T31 0 1 0 0
T57 0 1 0 0
T59 0 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 7271325 8291 0 0
T1 509 1 0 0
T2 486 1 0 0
T3 481 0 0 0
T4 666 0 0 0
T6 0 1 0 0
T7 0 1 0 0
T11 0 80 0 0
T12 747 0 0 0
T13 523 0 0 0
T14 412 0 0 0
T15 423 0 0 0
T16 1038 0 0 0
T17 426 0 0 0
T28 0 1 0 0
T29 0 1 0 0
T31 0 1 0 0
T57 0 1 0 0
T59 0 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00

30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin 31 1/1 if (!rst_src_ni) begin Tests: T1 T2 T4  32 1/1 src_level <= 1'b0; Tests: T1 T2 T4  33 end else begin 34 1/1 src_level <= src_level ^ src_pulse_i; Tests: T1 T2 T4  35 end 36 end 37 38 39 // source active must come far enough such that the destination domain has time 40 // to create a valid pulse. 41 `ifdef INC_ASSERT 42 //VCS coverage off 43 // pragma coverage off 44 45 // source active flag tracks whether there is an ongoing "toggle" event. 46 // Until this toggle event is accepted by the destination domain (negative edge of 47 // of the pulse output), the source side cannot toggle again. 48 logic effective_rst_n; 49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o; 50 51 logic src_active_flag_d, src_active_flag_q; 52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q; 53 54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin 55 unreachable if (!effective_rst_n) begin 56 unreachable src_active_flag_q <= '0; 57 end else begin 58 unreachable src_active_flag_q <= src_active_flag_d; 59 end 60 end 61 62 //VCS coverage on 63 // pragma coverage on 64 65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni) 66 `endif 67 68 ////////////////////////////////////////////////////////// 69 // synchronize level signal to destination clock domain // 70 ////////////////////////////////////////////////////////// 71 logic dst_level; 72 73 prim_flop_2sync #(.Width(1)) prim_flop_2sync ( 74 // source clock domain 75 .d_i (src_level), 76 // destination clock domain 77 .clk_i (clk_dst_i), 78 .rst_ni (rst_dst_ni), 79 .q_o (dst_level) 80 ); 81 82 //////////////////////////////////////// 83 // convert level signal back to pulse // 84 //////////////////////////////////////// 85 logic dst_level_q; 86 87 // delay dst_level by 1 cycle 88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin 89 1/1 if (!rst_dst_ni) begin Tests: T1 T2 T4  90 1/1 dst_level_q <= 1'b0; Tests: T1 T2 T4  91 end else begin 92 1/1 dst_level_q <= dst_level; Tests: T1 T2 T4  93 end 94 end 95 96 // edge detection 97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level; Tests: T6 T11 T21 

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT6,T11,T21
10CoveredT6,T11,T21
11CoveredT11,T21,T30

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT6,T11,T21
10CoveredT11,T21,T30
11CoveredT6,T11,T21

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00


31 if (!rst_src_ni) begin -1- 32 src_level <= 1'b0; ==> 33 end else begin 34 src_level <= src_level ^ src_pulse_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


89 if (!rst_dst_ni) begin -1- 90 dst_level_q <= 1'b0; ==> 91 end else begin 92 dst_level_q <= dst_level; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
DstPulseCheck_A 7271325 8309 0 0
SrcPulseCheck_M 1332231489 8380 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7271325 8309 0 0
T6 7579 1 0 0
T8 627 0 0 0
T11 0 80 0 0
T21 0 11 0 0
T29 456 0 0 0
T30 0 86 0 0
T32 0 7 0 0
T40 0 80 0 0
T41 0 14 0 0
T42 0 4 0 0
T56 0 11 0 0
T57 443 0 0 0
T65 522 0 0 0
T66 406 0 0 0
T67 424 0 0 0
T68 818 0 0 0
T69 615 0 0 0
T82 527 0 0 0
T88 0 62 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 1332231489 8380 0 0
T6 568425 1 0 0
T8 240611 0 0 0
T11 0 80 0 0
T21 0 11 0 0
T29 52546 0 0 0
T30 0 86 0 0
T32 0 7 0 0
T40 0 80 0 0
T41 0 14 0 0
T42 0 4 0 0
T56 0 11 0 0
T57 53142 0 0 0
T65 251010 0 0 0
T66 48764 0 0 0
T67 53084 0 0 0
T68 393069 0 0 0
T69 21542 0 0 0
T82 63369 0 0 0
T88 0 62 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00

30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin 31 1/1 if (!rst_src_ni) begin Tests: T1 T2 T4  32 1/1 src_level <= 1'b0; Tests: T1 T2 T4  33 end else begin 34 1/1 src_level <= src_level ^ src_pulse_i; Tests: T1 T2 T4  35 end 36 end 37 38 39 // source active must come far enough such that the destination domain has time 40 // to create a valid pulse. 41 `ifdef INC_ASSERT 42 //VCS coverage off 43 // pragma coverage off 44 45 // source active flag tracks whether there is an ongoing "toggle" event. 46 // Until this toggle event is accepted by the destination domain (negative edge of 47 // of the pulse output), the source side cannot toggle again. 48 logic effective_rst_n; 49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o; 50 51 logic src_active_flag_d, src_active_flag_q; 52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q; 53 54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin 55 unreachable if (!effective_rst_n) begin 56 unreachable src_active_flag_q <= '0; 57 end else begin 58 unreachable src_active_flag_q <= src_active_flag_d; 59 end 60 end 61 62 //VCS coverage on 63 // pragma coverage on 64 65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni) 66 `endif 67 68 ////////////////////////////////////////////////////////// 69 // synchronize level signal to destination clock domain // 70 ////////////////////////////////////////////////////////// 71 logic dst_level; 72 73 prim_flop_2sync #(.Width(1)) prim_flop_2sync ( 74 // source clock domain 75 .d_i (src_level), 76 // destination clock domain 77 .clk_i (clk_dst_i), 78 .rst_ni (rst_dst_ni), 79 .q_o (dst_level) 80 ); 81 82 //////////////////////////////////////// 83 // convert level signal back to pulse // 84 //////////////////////////////////////// 85 logic dst_level_q; 86 87 // delay dst_level by 1 cycle 88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin 89 1/1 if (!rst_dst_ni) begin Tests: T1 T2 T4  90 1/1 dst_level_q <= 1'b0; Tests: T1 T2 T4  91 end else begin 92 1/1 dst_level_q <= dst_level; Tests: T1 T2 T4  93 end 94 end 95 96 // edge detection 97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level; Tests: T1 T2 T4 

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT6,T11,T21
10CoveredT6,T11,T21
11CoveredT11,T21,T30

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT6,T11,T21
10CoveredT11,T21,T30
11CoveredT6,T11,T21

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00


31 if (!rst_src_ni) begin -1- 32 src_level <= 1'b0; ==> 33 end else begin 34 src_level <= src_level ^ src_pulse_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


89 if (!rst_dst_ni) begin -1- 90 dst_level_q <= 1'b0; ==> 91 end else begin 92 dst_level_q <= dst_level; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
DstPulseCheck_A 1332231489 8375 0 0
SrcPulseCheck_M 7271325 8375 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1332231489 8375 0 0
T6 568425 1 0 0
T8 240611 0 0 0
T11 0 80 0 0
T21 0 11 0 0
T29 52546 0 0 0
T30 0 86 0 0
T32 0 7 0 0
T40 0 80 0 0
T41 0 14 0 0
T42 0 4 0 0
T56 0 11 0 0
T57 53142 0 0 0
T65 251010 0 0 0
T66 48764 0 0 0
T67 53084 0 0 0
T68 393069 0 0 0
T69 21542 0 0 0
T82 63369 0 0 0
T88 0 62 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 7271325 8375 0 0
T6 7579 1 0 0
T8 627 0 0 0
T11 0 80 0 0
T21 0 11 0 0
T29 456 0 0 0
T30 0 86 0 0
T32 0 7 0 0
T40 0 80 0 0
T41 0 14 0 0
T42 0 4 0 0
T56 0 11 0 0
T57 443 0 0 0
T65 522 0 0 0
T66 406 0 0 0
T67 424 0 0 0
T68 818 0 0 0
T69 615 0 0 0
T82 527 0 0 0
T88 0 62 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00

30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin 31 1/1 if (!rst_src_ni) begin Tests: T1 T2 T4  32 1/1 src_level <= 1'b0; Tests: T1 T2 T4  33 end else begin 34 1/1 src_level <= src_level ^ src_pulse_i; Tests: T1 T2 T4  35 end 36 end 37 38 39 // source active must come far enough such that the destination domain has time 40 // to create a valid pulse. 41 `ifdef INC_ASSERT 42 //VCS coverage off 43 // pragma coverage off 44 45 // source active flag tracks whether there is an ongoing "toggle" event. 46 // Until this toggle event is accepted by the destination domain (negative edge of 47 // of the pulse output), the source side cannot toggle again. 48 logic effective_rst_n; 49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o; 50 51 logic src_active_flag_d, src_active_flag_q; 52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q; 53 54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin 55 unreachable if (!effective_rst_n) begin 56 unreachable src_active_flag_q <= '0; 57 end else begin 58 unreachable src_active_flag_q <= src_active_flag_d; 59 end 60 end 61 62 //VCS coverage on 63 // pragma coverage on 64 65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni) 66 `endif 67 68 ////////////////////////////////////////////////////////// 69 // synchronize level signal to destination clock domain // 70 ////////////////////////////////////////////////////////// 71 logic dst_level; 72 73 prim_flop_2sync #(.Width(1)) prim_flop_2sync ( 74 // source clock domain 75 .d_i (src_level), 76 // destination clock domain 77 .clk_i (clk_dst_i), 78 .rst_ni (rst_dst_ni), 79 .q_o (dst_level) 80 ); 81 82 //////////////////////////////////////// 83 // convert level signal back to pulse // 84 //////////////////////////////////////// 85 logic dst_level_q; 86 87 // delay dst_level by 1 cycle 88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin 89 1/1 if (!rst_dst_ni) begin Tests: T1 T2 T4  90 1/1 dst_level_q <= 1'b0; Tests: T1 T2 T4  91 end else begin 92 1/1 dst_level_q <= dst_level; Tests: T1 T2 T4  93 end 94 end 95 96 // edge detection 97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level; Tests: T6 T11 T21 

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT6,T11,T21
10CoveredT6,T11,T21
11CoveredT11,T21,T30

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT6,T11,T21
10CoveredT11,T21,T30
11CoveredT6,T11,T21

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00


31 if (!rst_src_ni) begin -1- 32 src_level <= 1'b0; ==> 33 end else begin 34 src_level <= src_level ^ src_pulse_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


89 if (!rst_dst_ni) begin -1- 90 dst_level_q <= 1'b0; ==> 91 end else begin 92 dst_level_q <= dst_level; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
DstPulseCheck_A 7271325 8195 0 0
SrcPulseCheck_M 1332231489 8264 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7271325 8195 0 0
T6 7579 1 0 0
T8 627 0 0 0
T11 0 62 0 0
T21 0 11 0 0
T29 456 0 0 0
T30 0 59 0 0
T32 0 7 0 0
T40 0 77 0 0
T41 0 14 0 0
T42 0 4 0 0
T56 0 11 0 0
T57 443 0 0 0
T65 522 0 0 0
T66 406 0 0 0
T67 424 0 0 0
T68 818 0 0 0
T69 615 0 0 0
T82 527 0 0 0
T88 0 74 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 1332231489 8264 0 0
T6 568425 1 0 0
T8 240611 0 0 0
T11 0 62 0 0
T21 0 11 0 0
T29 52546 0 0 0
T30 0 59 0 0
T32 0 7 0 0
T40 0 77 0 0
T41 0 14 0 0
T42 0 4 0 0
T56 0 11 0 0
T57 53142 0 0 0
T65 251010 0 0 0
T66 48764 0 0 0
T67 53084 0 0 0
T68 393069 0 0 0
T69 21542 0 0 0
T82 63369 0 0 0
T88 0 74 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00

30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin 31 1/1 if (!rst_src_ni) begin Tests: T1 T2 T4  32 1/1 src_level <= 1'b0; Tests: T1 T2 T4  33 end else begin 34 1/1 src_level <= src_level ^ src_pulse_i; Tests: T1 T2 T4  35 end 36 end 37 38 39 // source active must come far enough such that the destination domain has time 40 // to create a valid pulse. 41 `ifdef INC_ASSERT 42 //VCS coverage off 43 // pragma coverage off 44 45 // source active flag tracks whether there is an ongoing "toggle" event. 46 // Until this toggle event is accepted by the destination domain (negative edge of 47 // of the pulse output), the source side cannot toggle again. 48 logic effective_rst_n; 49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o; 50 51 logic src_active_flag_d, src_active_flag_q; 52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q; 53 54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin 55 unreachable if (!effective_rst_n) begin 56 unreachable src_active_flag_q <= '0; 57 end else begin 58 unreachable src_active_flag_q <= src_active_flag_d; 59 end 60 end 61 62 //VCS coverage on 63 // pragma coverage on 64 65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni) 66 `endif 67 68 ////////////////////////////////////////////////////////// 69 // synchronize level signal to destination clock domain // 70 ////////////////////////////////////////////////////////// 71 logic dst_level; 72 73 prim_flop_2sync #(.Width(1)) prim_flop_2sync ( 74 // source clock domain 75 .d_i (src_level), 76 // destination clock domain 77 .clk_i (clk_dst_i), 78 .rst_ni (rst_dst_ni), 79 .q_o (dst_level) 80 ); 81 82 //////////////////////////////////////// 83 // convert level signal back to pulse // 84 //////////////////////////////////////// 85 logic dst_level_q; 86 87 // delay dst_level by 1 cycle 88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin 89 1/1 if (!rst_dst_ni) begin Tests: T1 T2 T4  90 1/1 dst_level_q <= 1'b0; Tests: T1 T2 T4  91 end else begin 92 1/1 dst_level_q <= dst_level; Tests: T1 T2 T4  93 end 94 end 95 96 // edge detection 97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level; Tests: T1 T2 T4 

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT6,T11,T21
10CoveredT6,T11,T21
11CoveredT11,T21,T30

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT6,T11,T21
10CoveredT11,T21,T30
11CoveredT6,T11,T21

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00


31 if (!rst_src_ni) begin -1- 32 src_level <= 1'b0; ==> 33 end else begin 34 src_level <= src_level ^ src_pulse_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


89 if (!rst_dst_ni) begin -1- 90 dst_level_q <= 1'b0; ==> 91 end else begin 92 dst_level_q <= dst_level; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
DstPulseCheck_A 1332231489 8259 0 0
SrcPulseCheck_M 7271325 8259 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1332231489 8259 0 0
T6 568425 1 0 0
T8 240611 0 0 0
T11 0 62 0 0
T21 0 11 0 0
T29 52546 0 0 0
T30 0 59 0 0
T32 0 7 0 0
T40 0 77 0 0
T41 0 14 0 0
T42 0 4 0 0
T56 0 11 0 0
T57 53142 0 0 0
T65 251010 0 0 0
T66 48764 0 0 0
T67 53084 0 0 0
T68 393069 0 0 0
T69 21542 0 0 0
T82 63369 0 0 0
T88 0 74 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 7271325 8259 0 0
T6 7579 1 0 0
T8 627 0 0 0
T11 0 62 0 0
T21 0 11 0 0
T29 456 0 0 0
T30 0 59 0 0
T32 0 7 0 0
T40 0 77 0 0
T41 0 14 0 0
T42 0 4 0 0
T56 0 11 0 0
T57 443 0 0 0
T65 522 0 0 0
T66 406 0 0 0
T67 424 0 0 0
T68 818 0 0 0
T69 615 0 0 0
T82 527 0 0 0
T88 0 74 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00

30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin 31 1/1 if (!rst_src_ni) begin Tests: T1 T2 T4  32 1/1 src_level <= 1'b0; Tests: T1 T2 T4  33 end else begin 34 1/1 src_level <= src_level ^ src_pulse_i; Tests: T1 T2 T4  35 end 36 end 37 38 39 // source active must come far enough such that the destination domain has time 40 // to create a valid pulse. 41 `ifdef INC_ASSERT 42 //VCS coverage off 43 // pragma coverage off 44 45 // source active flag tracks whether there is an ongoing "toggle" event. 46 // Until this toggle event is accepted by the destination domain (negative edge of 47 // of the pulse output), the source side cannot toggle again. 48 logic effective_rst_n; 49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o; 50 51 logic src_active_flag_d, src_active_flag_q; 52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q; 53 54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin 55 unreachable if (!effective_rst_n) begin 56 unreachable src_active_flag_q <= '0; 57 end else begin 58 unreachable src_active_flag_q <= src_active_flag_d; 59 end 60 end 61 62 //VCS coverage on 63 // pragma coverage on 64 65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni) 66 `endif 67 68 ////////////////////////////////////////////////////////// 69 // synchronize level signal to destination clock domain // 70 ////////////////////////////////////////////////////////// 71 logic dst_level; 72 73 prim_flop_2sync #(.Width(1)) prim_flop_2sync ( 74 // source clock domain 75 .d_i (src_level), 76 // destination clock domain 77 .clk_i (clk_dst_i), 78 .rst_ni (rst_dst_ni), 79 .q_o (dst_level) 80 ); 81 82 //////////////////////////////////////// 83 // convert level signal back to pulse // 84 //////////////////////////////////////// 85 logic dst_level_q; 86 87 // delay dst_level by 1 cycle 88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin 89 1/1 if (!rst_dst_ni) begin Tests: T1 T2 T4  90 1/1 dst_level_q <= 1'b0; Tests: T1 T2 T4  91 end else begin 92 1/1 dst_level_q <= dst_level; Tests: T1 T2 T4  93 end 94 end 95 96 // edge detection 97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level; Tests: T6 T11 T21 

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT6,T11,T21
10CoveredT6,T11,T21
11CoveredT11,T21,T30

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT6,T11,T21
10CoveredT11,T21,T30
11CoveredT6,T11,T21

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00


31 if (!rst_src_ni) begin -1- 32 src_level <= 1'b0; ==> 33 end else begin 34 src_level <= src_level ^ src_pulse_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


89 if (!rst_dst_ni) begin -1- 90 dst_level_q <= 1'b0; ==> 91 end else begin 92 dst_level_q <= dst_level; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
DstPulseCheck_A 7271325 8220 0 0
SrcPulseCheck_M 1332231489 8293 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7271325 8220 0 0
T6 7579 1 0 0
T8 627 0 0 0
T11 0 80 0 0
T21 0 11 0 0
T29 456 0 0 0
T30 0 86 0 0
T32 0 7 0 0
T40 0 95 0 0
T41 0 14 0 0
T42 0 4 0 0
T56 0 11 0 0
T57 443 0 0 0
T65 522 0 0 0
T66 406 0 0 0
T67 424 0 0 0
T68 818 0 0 0
T69 615 0 0 0
T82 527 0 0 0
T88 0 84 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 1332231489 8293 0 0
T6 568425 1 0 0
T8 240611 0 0 0
T11 0 80 0 0
T21 0 11 0 0
T29 52546 0 0 0
T30 0 86 0 0
T32 0 7 0 0
T40 0 95 0 0
T41 0 14 0 0
T42 0 4 0 0
T56 0 11 0 0
T57 53142 0 0 0
T65 251010 0 0 0
T66 48764 0 0 0
T67 53084 0 0 0
T68 393069 0 0 0
T69 21542 0 0 0
T82 63369 0 0 0
T88 0 84 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00

30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin 31 1/1 if (!rst_src_ni) begin Tests: T1 T2 T4  32 1/1 src_level <= 1'b0; Tests: T1 T2 T4  33 end else begin 34 1/1 src_level <= src_level ^ src_pulse_i; Tests: T1 T2 T4  35 end 36 end 37 38 39 // source active must come far enough such that the destination domain has time 40 // to create a valid pulse. 41 `ifdef INC_ASSERT 42 //VCS coverage off 43 // pragma coverage off 44 45 // source active flag tracks whether there is an ongoing "toggle" event. 46 // Until this toggle event is accepted by the destination domain (negative edge of 47 // of the pulse output), the source side cannot toggle again. 48 logic effective_rst_n; 49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o; 50 51 logic src_active_flag_d, src_active_flag_q; 52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q; 53 54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin 55 unreachable if (!effective_rst_n) begin 56 unreachable src_active_flag_q <= '0; 57 end else begin 58 unreachable src_active_flag_q <= src_active_flag_d; 59 end 60 end 61 62 //VCS coverage on 63 // pragma coverage on 64 65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni) 66 `endif 67 68 ////////////////////////////////////////////////////////// 69 // synchronize level signal to destination clock domain // 70 ////////////////////////////////////////////////////////// 71 logic dst_level; 72 73 prim_flop_2sync #(.Width(1)) prim_flop_2sync ( 74 // source clock domain 75 .d_i (src_level), 76 // destination clock domain 77 .clk_i (clk_dst_i), 78 .rst_ni (rst_dst_ni), 79 .q_o (dst_level) 80 ); 81 82 //////////////////////////////////////// 83 // convert level signal back to pulse // 84 //////////////////////////////////////// 85 logic dst_level_q; 86 87 // delay dst_level by 1 cycle 88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin 89 1/1 if (!rst_dst_ni) begin Tests: T1 T2 T4  90 1/1 dst_level_q <= 1'b0; Tests: T1 T2 T4  91 end else begin 92 1/1 dst_level_q <= dst_level; Tests: T1 T2 T4  93 end 94 end 95 96 // edge detection 97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level; Tests: T1 T2 T4 

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT6,T11,T21
10CoveredT6,T11,T21
11CoveredT11,T21,T30

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT6,T11,T21
10CoveredT11,T21,T30
11CoveredT6,T11,T21

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00


31 if (!rst_src_ni) begin -1- 32 src_level <= 1'b0; ==> 33 end else begin 34 src_level <= src_level ^ src_pulse_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


89 if (!rst_dst_ni) begin -1- 90 dst_level_q <= 1'b0; ==> 91 end else begin 92 dst_level_q <= dst_level; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
DstPulseCheck_A 1332231489 8288 0 0
SrcPulseCheck_M 7271325 8288 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1332231489 8288 0 0
T6 568425 1 0 0
T8 240611 0 0 0
T11 0 80 0 0
T21 0 11 0 0
T29 52546 0 0 0
T30 0 86 0 0
T32 0 7 0 0
T40 0 95 0 0
T41 0 14 0 0
T42 0 4 0 0
T56 0 11 0 0
T57 53142 0 0 0
T65 251010 0 0 0
T66 48764 0 0 0
T67 53084 0 0 0
T68 393069 0 0 0
T69 21542 0 0 0
T82 63369 0 0 0
T88 0 84 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 7271325 8288 0 0
T6 7579 1 0 0
T8 627 0 0 0
T11 0 80 0 0
T21 0 11 0 0
T29 456 0 0 0
T30 0 86 0 0
T32 0 7 0 0
T40 0 95 0 0
T41 0 14 0 0
T42 0 4 0 0
T56 0 11 0 0
T57 443 0 0 0
T65 522 0 0 0
T66 406 0 0 0
T67 424 0 0 0
T68 818 0 0 0
T69 615 0 0 0
T82 527 0 0 0
T88 0 84 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00

30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin 31 1/1 if (!rst_src_ni) begin Tests: T1 T2 T4  32 1/1 src_level <= 1'b0; Tests: T1 T2 T4  33 end else begin 34 1/1 src_level <= src_level ^ src_pulse_i; Tests: T1 T2 T4  35 end 36 end 37 38 39 // source active must come far enough such that the destination domain has time 40 // to create a valid pulse. 41 `ifdef INC_ASSERT 42 //VCS coverage off 43 // pragma coverage off 44 45 // source active flag tracks whether there is an ongoing "toggle" event. 46 // Until this toggle event is accepted by the destination domain (negative edge of 47 // of the pulse output), the source side cannot toggle again. 48 logic effective_rst_n; 49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o; 50 51 logic src_active_flag_d, src_active_flag_q; 52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q; 53 54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin 55 unreachable if (!effective_rst_n) begin 56 unreachable src_active_flag_q <= '0; 57 end else begin 58 unreachable src_active_flag_q <= src_active_flag_d; 59 end 60 end 61 62 //VCS coverage on 63 // pragma coverage on 64 65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni) 66 `endif 67 68 ////////////////////////////////////////////////////////// 69 // synchronize level signal to destination clock domain // 70 ////////////////////////////////////////////////////////// 71 logic dst_level; 72 73 prim_flop_2sync #(.Width(1)) prim_flop_2sync ( 74 // source clock domain 75 .d_i (src_level), 76 // destination clock domain 77 .clk_i (clk_dst_i), 78 .rst_ni (rst_dst_ni), 79 .q_o (dst_level) 80 ); 81 82 //////////////////////////////////////// 83 // convert level signal back to pulse // 84 //////////////////////////////////////// 85 logic dst_level_q; 86 87 // delay dst_level by 1 cycle 88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin 89 1/1 if (!rst_dst_ni) begin Tests: T1 T2 T4  90 1/1 dst_level_q <= 1'b0; Tests: T1 T2 T4  91 end else begin 92 1/1 dst_level_q <= dst_level; Tests: T1 T2 T4  93 end 94 end 95 96 // edge detection 97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level; Tests: T1 T2 T31 

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT1,T2,T31
10CoveredT1,T2,T31
11CoveredT21,T56,T34

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT1,T2,T31
10CoveredT21,T56,T34
11CoveredT1,T2,T31

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00


31 if (!rst_src_ni) begin -1- 32 src_level <= 1'b0; ==> 33 end else begin 34 src_level <= src_level ^ src_pulse_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


89 if (!rst_dst_ni) begin -1- 90 dst_level_q <= 1'b0; ==> 91 end else begin 92 dst_level_q <= dst_level; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
DstPulseCheck_A 7271325 2003 0 0
SrcPulseCheck_M 1332231489 2072 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7271325 2003 0 0
T1 509 1 0 0
T2 486 1 0 0
T3 481 0 0 0
T4 666 0 0 0
T6 0 1 0 0
T7 0 1 0 0
T11 0 12 0 0
T12 747 0 0 0
T13 523 0 0 0
T14 412 0 0 0
T15 423 0 0 0
T16 1038 0 0 0
T17 426 0 0 0
T28 0 1 0 0
T29 0 1 0 0
T31 0 1 0 0
T57 0 1 0 0
T59 0 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 1332231489 2072 0 0
T1 63648 1 0 0
T2 58317 1 0 0
T3 215595 0 0 0
T4 43326 0 0 0
T6 0 1 0 0
T7 0 1 0 0
T11 0 12 0 0
T12 18956 0 0 0
T13 128352 0 0 0
T14 195910 0 0 0
T15 101494 0 0 0
T16 129820 0 0 0
T17 51227 0 0 0
T28 0 1 0 0
T29 0 1 0 0
T31 0 1 0 0
T57 0 1 0 0
T59 0 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00

30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin 31 1/1 if (!rst_src_ni) begin Tests: T1 T2 T4  32 1/1 src_level <= 1'b0; Tests: T1 T2 T4  33 end else begin 34 1/1 src_level <= src_level ^ src_pulse_i; Tests: T1 T2 T4  35 end 36 end 37 38 39 // source active must come far enough such that the destination domain has time 40 // to create a valid pulse. 41 `ifdef INC_ASSERT 42 //VCS coverage off 43 // pragma coverage off 44 45 // source active flag tracks whether there is an ongoing "toggle" event. 46 // Until this toggle event is accepted by the destination domain (negative edge of 47 // of the pulse output), the source side cannot toggle again. 48 logic effective_rst_n; 49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o; 50 51 logic src_active_flag_d, src_active_flag_q; 52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q; 53 54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin 55 unreachable if (!effective_rst_n) begin 56 unreachable src_active_flag_q <= '0; 57 end else begin 58 unreachable src_active_flag_q <= src_active_flag_d; 59 end 60 end 61 62 //VCS coverage on 63 // pragma coverage on 64 65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni) 66 `endif 67 68 ////////////////////////////////////////////////////////// 69 // synchronize level signal to destination clock domain // 70 ////////////////////////////////////////////////////////// 71 logic dst_level; 72 73 prim_flop_2sync #(.Width(1)) prim_flop_2sync ( 74 // source clock domain 75 .d_i (src_level), 76 // destination clock domain 77 .clk_i (clk_dst_i), 78 .rst_ni (rst_dst_ni), 79 .q_o (dst_level) 80 ); 81 82 //////////////////////////////////////// 83 // convert level signal back to pulse // 84 //////////////////////////////////////// 85 logic dst_level_q; 86 87 // delay dst_level by 1 cycle 88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin 89 1/1 if (!rst_dst_ni) begin Tests: T1 T2 T4  90 1/1 dst_level_q <= 1'b0; Tests: T1 T2 T4  91 end else begin 92 1/1 dst_level_q <= dst_level; Tests: T1 T2 T4  93 end 94 end 95 96 // edge detection 97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level; Tests: T1 T2 T4 

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT1,T2,T31
10CoveredT1,T2,T31
11CoveredT21,T56,T34

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT1,T2,T31
10CoveredT21,T56,T34
11CoveredT1,T2,T31

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00


31 if (!rst_src_ni) begin -1- 32 src_level <= 1'b0; ==> 33 end else begin 34 src_level <= src_level ^ src_pulse_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


89 if (!rst_dst_ni) begin -1- 90 dst_level_q <= 1'b0; ==> 91 end else begin 92 dst_level_q <= dst_level; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
DstPulseCheck_A 1332231489 2067 0 0
SrcPulseCheck_M 7271325 2067 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1332231489 2067 0 0
T1 63648 1 0 0
T2 58317 1 0 0
T3 215595 0 0 0
T4 43326 0 0 0
T6 0 1 0 0
T7 0 1 0 0
T11 0 12 0 0
T12 18956 0 0 0
T13 128352 0 0 0
T14 195910 0 0 0
T15 101494 0 0 0
T16 129820 0 0 0
T17 51227 0 0 0
T28 0 1 0 0
T29 0 1 0 0
T31 0 1 0 0
T57 0 1 0 0
T59 0 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 7271325 2067 0 0
T1 509 1 0 0
T2 486 1 0 0
T3 481 0 0 0
T4 666 0 0 0
T6 0 1 0 0
T7 0 1 0 0
T11 0 12 0 0
T12 747 0 0 0
T13 523 0 0 0
T14 412 0 0 0
T15 423 0 0 0
T16 1038 0 0 0
T17 426 0 0 0
T28 0 1 0 0
T29 0 1 0 0
T31 0 1 0 0
T57 0 1 0 0
T59 0 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00

30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin 31 1/1 if (!rst_src_ni) begin Tests: T1 T2 T4  32 1/1 src_level <= 1'b0; Tests: T1 T2 T4  33 end else begin 34 1/1 src_level <= src_level ^ src_pulse_i; Tests: T1 T2 T4  35 end 36 end 37 38 39 // source active must come far enough such that the destination domain has time 40 // to create a valid pulse. 41 `ifdef INC_ASSERT 42 //VCS coverage off 43 // pragma coverage off 44 45 // source active flag tracks whether there is an ongoing "toggle" event. 46 // Until this toggle event is accepted by the destination domain (negative edge of 47 // of the pulse output), the source side cannot toggle again. 48 logic effective_rst_n; 49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o; 50 51 logic src_active_flag_d, src_active_flag_q; 52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q; 53 54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin 55 unreachable if (!effective_rst_n) begin 56 unreachable src_active_flag_q <= '0; 57 end else begin 58 unreachable src_active_flag_q <= src_active_flag_d; 59 end 60 end 61 62 //VCS coverage on 63 // pragma coverage on 64 65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni) 66 `endif 67 68 ////////////////////////////////////////////////////////// 69 // synchronize level signal to destination clock domain // 70 ////////////////////////////////////////////////////////// 71 logic dst_level; 72 73 prim_flop_2sync #(.Width(1)) prim_flop_2sync ( 74 // source clock domain 75 .d_i (src_level), 76 // destination clock domain 77 .clk_i (clk_dst_i), 78 .rst_ni (rst_dst_ni), 79 .q_o (dst_level) 80 ); 81 82 //////////////////////////////////////// 83 // convert level signal back to pulse // 84 //////////////////////////////////////// 85 logic dst_level_q; 86 87 // delay dst_level by 1 cycle 88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin 89 1/1 if (!rst_dst_ni) begin Tests: T1 T2 T4  90 1/1 dst_level_q <= 1'b0; Tests: T1 T2 T4  91 end else begin 92 1/1 dst_level_q <= dst_level; Tests: T1 T2 T4  93 end 94 end 95 96 // edge detection 97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level; Tests: T6 T11 T21 

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT6,T11,T21
10CoveredT6,T11,T21
11CoveredT21,T56,T34

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT6,T11,T21
10CoveredT21,T56,T34
11CoveredT6,T11,T21

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00


31 if (!rst_src_ni) begin -1- 32 src_level <= 1'b0; ==> 33 end else begin 34 src_level <= src_level ^ src_pulse_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


89 if (!rst_dst_ni) begin -1- 90 dst_level_q <= 1'b0; ==> 91 end else begin 92 dst_level_q <= dst_level; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
DstPulseCheck_A 7271325 1918 0 0
SrcPulseCheck_M 1332231489 1986 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7271325 1918 0 0
T6 7579 1 0 0
T8 627 0 0 0
T11 0 12 0 0
T21 0 9 0 0
T29 456 0 0 0
T30 0 2 0 0
T32 0 7 0 0
T40 0 10 0 0
T41 0 14 0 0
T42 0 4 0 0
T56 0 9 0 0
T57 443 0 0 0
T65 522 0 0 0
T66 406 0 0 0
T67 424 0 0 0
T68 818 0 0 0
T69 615 0 0 0
T82 527 0 0 0
T88 0 7 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 1332231489 1986 0 0
T6 568425 1 0 0
T8 240611 0 0 0
T11 0 12 0 0
T21 0 9 0 0
T29 52546 0 0 0
T30 0 2 0 0
T32 0 7 0 0
T40 0 10 0 0
T41 0 14 0 0
T42 0 4 0 0
T56 0 9 0 0
T57 53142 0 0 0
T65 251010 0 0 0
T66 48764 0 0 0
T67 53084 0 0 0
T68 393069 0 0 0
T69 21542 0 0 0
T82 63369 0 0 0
T88 0 7 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00

30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin 31 1/1 if (!rst_src_ni) begin Tests: T1 T2 T4  32 1/1 src_level <= 1'b0; Tests: T1 T2 T4  33 end else begin 34 1/1 src_level <= src_level ^ src_pulse_i; Tests: T1 T2 T4  35 end 36 end 37 38 39 // source active must come far enough such that the destination domain has time 40 // to create a valid pulse. 41 `ifdef INC_ASSERT 42 //VCS coverage off 43 // pragma coverage off 44 45 // source active flag tracks whether there is an ongoing "toggle" event. 46 // Until this toggle event is accepted by the destination domain (negative edge of 47 // of the pulse output), the source side cannot toggle again. 48 logic effective_rst_n; 49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o; 50 51 logic src_active_flag_d, src_active_flag_q; 52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q; 53 54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin 55 unreachable if (!effective_rst_n) begin 56 unreachable src_active_flag_q <= '0; 57 end else begin 58 unreachable src_active_flag_q <= src_active_flag_d; 59 end 60 end 61 62 //VCS coverage on 63 // pragma coverage on 64 65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni) 66 `endif 67 68 ////////////////////////////////////////////////////////// 69 // synchronize level signal to destination clock domain // 70 ////////////////////////////////////////////////////////// 71 logic dst_level; 72 73 prim_flop_2sync #(.Width(1)) prim_flop_2sync ( 74 // source clock domain 75 .d_i (src_level), 76 // destination clock domain 77 .clk_i (clk_dst_i), 78 .rst_ni (rst_dst_ni), 79 .q_o (dst_level) 80 ); 81 82 //////////////////////////////////////// 83 // convert level signal back to pulse // 84 //////////////////////////////////////// 85 logic dst_level_q; 86 87 // delay dst_level by 1 cycle 88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin 89 1/1 if (!rst_dst_ni) begin Tests: T1 T2 T4  90 1/1 dst_level_q <= 1'b0; Tests: T1 T2 T4  91 end else begin 92 1/1 dst_level_q <= dst_level; Tests: T1 T2 T4  93 end 94 end 95 96 // edge detection 97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level; Tests: T1 T2 T4 

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT6,T11,T21
10CoveredT6,T11,T21
11CoveredT21,T56,T34

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT6,T11,T21
10CoveredT21,T56,T34
11CoveredT6,T11,T21

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00


31 if (!rst_src_ni) begin -1- 32 src_level <= 1'b0; ==> 33 end else begin 34 src_level <= src_level ^ src_pulse_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


89 if (!rst_dst_ni) begin -1- 90 dst_level_q <= 1'b0; ==> 91 end else begin 92 dst_level_q <= dst_level; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
DstPulseCheck_A 1332231489 1982 0 0
SrcPulseCheck_M 7271325 1982 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1332231489 1982 0 0
T6 568425 1 0 0
T8 240611 0 0 0
T11 0 12 0 0
T21 0 9 0 0
T29 52546 0 0 0
T30 0 2 0 0
T32 0 7 0 0
T40 0 10 0 0
T41 0 14 0 0
T42 0 4 0 0
T56 0 9 0 0
T57 53142 0 0 0
T65 251010 0 0 0
T66 48764 0 0 0
T67 53084 0 0 0
T68 393069 0 0 0
T69 21542 0 0 0
T82 63369 0 0 0
T88 0 7 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 7271325 1982 0 0
T6 7579 1 0 0
T8 627 0 0 0
T11 0 12 0 0
T21 0 9 0 0
T29 456 0 0 0
T30 0 2 0 0
T32 0 7 0 0
T40 0 10 0 0
T41 0 14 0 0
T42 0 4 0 0
T56 0 9 0 0
T57 443 0 0 0
T65 522 0 0 0
T66 406 0 0 0
T67 424 0 0 0
T68 818 0 0 0
T69 615 0 0 0
T82 527 0 0 0
T88 0 7 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00

30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin 31 1/1 if (!rst_src_ni) begin Tests: T1 T2 T4  32 1/1 src_level <= 1'b0; Tests: T1 T2 T4  33 end else begin 34 1/1 src_level <= src_level ^ src_pulse_i; Tests: T1 T2 T4  35 end 36 end 37 38 39 // source active must come far enough such that the destination domain has time 40 // to create a valid pulse. 41 `ifdef INC_ASSERT 42 //VCS coverage off 43 // pragma coverage off 44 45 // source active flag tracks whether there is an ongoing "toggle" event. 46 // Until this toggle event is accepted by the destination domain (negative edge of 47 // of the pulse output), the source side cannot toggle again. 48 logic effective_rst_n; 49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o; 50 51 logic src_active_flag_d, src_active_flag_q; 52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q; 53 54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin 55 unreachable if (!effective_rst_n) begin 56 unreachable src_active_flag_q <= '0; 57 end else begin 58 unreachable src_active_flag_q <= src_active_flag_d; 59 end 60 end 61 62 //VCS coverage on 63 // pragma coverage on 64 65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni) 66 `endif 67 68 ////////////////////////////////////////////////////////// 69 // synchronize level signal to destination clock domain // 70 ////////////////////////////////////////////////////////// 71 logic dst_level; 72 73 prim_flop_2sync #(.Width(1)) prim_flop_2sync ( 74 // source clock domain 75 .d_i (src_level), 76 // destination clock domain 77 .clk_i (clk_dst_i), 78 .rst_ni (rst_dst_ni), 79 .q_o (dst_level) 80 ); 81 82 //////////////////////////////////////// 83 // convert level signal back to pulse // 84 //////////////////////////////////////// 85 logic dst_level_q; 86 87 // delay dst_level by 1 cycle 88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin 89 1/1 if (!rst_dst_ni) begin Tests: T1 T2 T4  90 1/1 dst_level_q <= 1'b0; Tests: T1 T2 T4  91 end else begin 92 1/1 dst_level_q <= dst_level; Tests: T1 T2 T4  93 end 94 end 95 96 // edge detection 97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level; Tests: T6 T11 T21 

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT6,T11,T21
10CoveredT6,T11,T21
11CoveredT21,T56,T34

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT6,T11,T21
10CoveredT21,T56,T34
11CoveredT6,T11,T21

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00


31 if (!rst_src_ni) begin -1- 32 src_level <= 1'b0; ==> 33 end else begin 34 src_level <= src_level ^ src_pulse_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


89 if (!rst_dst_ni) begin -1- 90 dst_level_q <= 1'b0; ==> 91 end else begin 92 dst_level_q <= dst_level; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
DstPulseCheck_A 7271325 1924 0 0
SrcPulseCheck_M 1332231489 1991 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7271325 1924 0 0
T6 7579 1 0 0
T8 627 0 0 0
T11 0 12 0 0
T21 0 9 0 0
T29 456 0 0 0
T30 0 2 0 0
T32 0 7 0 0
T40 0 10 0 0
T41 0 14 0 0
T42 0 4 0 0
T56 0 9 0 0
T57 443 0 0 0
T65 522 0 0 0
T66 406 0 0 0
T67 424 0 0 0
T68 818 0 0 0
T69 615 0 0 0
T82 527 0 0 0
T88 0 7 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 1332231489 1991 0 0
T6 568425 1 0 0
T8 240611 0 0 0
T11 0 12 0 0
T21 0 9 0 0
T29 52546 0 0 0
T30 0 2 0 0
T32 0 7 0 0
T40 0 10 0 0
T41 0 14 0 0
T42 0 4 0 0
T56 0 9 0 0
T57 53142 0 0 0
T65 251010 0 0 0
T66 48764 0 0 0
T67 53084 0 0 0
T68 393069 0 0 0
T69 21542 0 0 0
T82 63369 0 0 0
T88 0 7 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00

30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin 31 1/1 if (!rst_src_ni) begin Tests: T1 T2 T4  32 1/1 src_level <= 1'b0; Tests: T1 T2 T4  33 end else begin 34 1/1 src_level <= src_level ^ src_pulse_i; Tests: T1 T2 T4  35 end 36 end 37 38 39 // source active must come far enough such that the destination domain has time 40 // to create a valid pulse. 41 `ifdef INC_ASSERT 42 //VCS coverage off 43 // pragma coverage off 44 45 // source active flag tracks whether there is an ongoing "toggle" event. 46 // Until this toggle event is accepted by the destination domain (negative edge of 47 // of the pulse output), the source side cannot toggle again. 48 logic effective_rst_n; 49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o; 50 51 logic src_active_flag_d, src_active_flag_q; 52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q; 53 54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin 55 unreachable if (!effective_rst_n) begin 56 unreachable src_active_flag_q <= '0; 57 end else begin 58 unreachable src_active_flag_q <= src_active_flag_d; 59 end 60 end 61 62 //VCS coverage on 63 // pragma coverage on 64 65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni) 66 `endif 67 68 ////////////////////////////////////////////////////////// 69 // synchronize level signal to destination clock domain // 70 ////////////////////////////////////////////////////////// 71 logic dst_level; 72 73 prim_flop_2sync #(.Width(1)) prim_flop_2sync ( 74 // source clock domain 75 .d_i (src_level), 76 // destination clock domain 77 .clk_i (clk_dst_i), 78 .rst_ni (rst_dst_ni), 79 .q_o (dst_level) 80 ); 81 82 //////////////////////////////////////// 83 // convert level signal back to pulse // 84 //////////////////////////////////////// 85 logic dst_level_q; 86 87 // delay dst_level by 1 cycle 88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin 89 1/1 if (!rst_dst_ni) begin Tests: T1 T2 T4  90 1/1 dst_level_q <= 1'b0; Tests: T1 T2 T4  91 end else begin 92 1/1 dst_level_q <= dst_level; Tests: T1 T2 T4  93 end 94 end 95 96 // edge detection 97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level; Tests: T1 T2 T4 

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT6,T11,T21
10CoveredT6,T11,T21
11CoveredT21,T56,T34

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT6,T11,T21
10CoveredT21,T56,T34
11CoveredT6,T11,T21

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00


31 if (!rst_src_ni) begin -1- 32 src_level <= 1'b0; ==> 33 end else begin 34 src_level <= src_level ^ src_pulse_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


89 if (!rst_dst_ni) begin -1- 90 dst_level_q <= 1'b0; ==> 91 end else begin 92 dst_level_q <= dst_level; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
DstPulseCheck_A 1332231489 1984 0 0
SrcPulseCheck_M 7271325 1984 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1332231489 1984 0 0
T6 568425 1 0 0
T8 240611 0 0 0
T11 0 12 0 0
T21 0 9 0 0
T29 52546 0 0 0
T30 0 2 0 0
T32 0 7 0 0
T40 0 10 0 0
T41 0 14 0 0
T42 0 4 0 0
T56 0 9 0 0
T57 53142 0 0 0
T65 251010 0 0 0
T66 48764 0 0 0
T67 53084 0 0 0
T68 393069 0 0 0
T69 21542 0 0 0
T82 63369 0 0 0
T88 0 7 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 7271325 1984 0 0
T6 7579 1 0 0
T8 627 0 0 0
T11 0 12 0 0
T21 0 9 0 0
T29 456 0 0 0
T30 0 2 0 0
T32 0 7 0 0
T40 0 10 0 0
T41 0 14 0 0
T42 0 4 0 0
T56 0 9 0 0
T57 443 0 0 0
T65 522 0 0 0
T66 406 0 0 0
T67 424 0 0 0
T68 818 0 0 0
T69 615 0 0 0
T82 527 0 0 0
T88 0 7 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00

30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin 31 1/1 if (!rst_src_ni) begin Tests: T1 T2 T4  32 1/1 src_level <= 1'b0; Tests: T1 T2 T4  33 end else begin 34 1/1 src_level <= src_level ^ src_pulse_i; Tests: T1 T2 T4  35 end 36 end 37 38 39 // source active must come far enough such that the destination domain has time 40 // to create a valid pulse. 41 `ifdef INC_ASSERT 42 //VCS coverage off 43 // pragma coverage off 44 45 // source active flag tracks whether there is an ongoing "toggle" event. 46 // Until this toggle event is accepted by the destination domain (negative edge of 47 // of the pulse output), the source side cannot toggle again. 48 logic effective_rst_n; 49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o; 50 51 logic src_active_flag_d, src_active_flag_q; 52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q; 53 54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin 55 unreachable if (!effective_rst_n) begin 56 unreachable src_active_flag_q <= '0; 57 end else begin 58 unreachable src_active_flag_q <= src_active_flag_d; 59 end 60 end 61 62 //VCS coverage on 63 // pragma coverage on 64 65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni) 66 `endif 67 68 ////////////////////////////////////////////////////////// 69 // synchronize level signal to destination clock domain // 70 ////////////////////////////////////////////////////////// 71 logic dst_level; 72 73 prim_flop_2sync #(.Width(1)) prim_flop_2sync ( 74 // source clock domain 75 .d_i (src_level), 76 // destination clock domain 77 .clk_i (clk_dst_i), 78 .rst_ni (rst_dst_ni), 79 .q_o (dst_level) 80 ); 81 82 //////////////////////////////////////// 83 // convert level signal back to pulse // 84 //////////////////////////////////////// 85 logic dst_level_q; 86 87 // delay dst_level by 1 cycle 88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin 89 1/1 if (!rst_dst_ni) begin Tests: T1 T2 T4  90 1/1 dst_level_q <= 1'b0; Tests: T1 T2 T4  91 end else begin 92 1/1 dst_level_q <= dst_level; Tests: T1 T2 T4  93 end 94 end 95 96 // edge detection 97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level; Tests: T6 T11 T21 

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT6,T11,T21
10CoveredT6,T11,T21
11CoveredT21,T56,T34

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT6,T11,T21
10CoveredT21,T56,T34
11CoveredT6,T11,T21

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00


31 if (!rst_src_ni) begin -1- 32 src_level <= 1'b0; ==> 33 end else begin 34 src_level <= src_level ^ src_pulse_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


89 if (!rst_dst_ni) begin -1- 90 dst_level_q <= 1'b0; ==> 91 end else begin 92 dst_level_q <= dst_level; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
DstPulseCheck_A 7271325 1924 0 0
SrcPulseCheck_M 1332231489 1991 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7271325 1924 0 0
T6 7579 1 0 0
T8 627 0 0 0
T11 0 12 0 0
T21 0 9 0 0
T29 456 0 0 0
T30 0 2 0 0
T32 0 7 0 0
T40 0 10 0 0
T41 0 14 0 0
T42 0 4 0 0
T56 0 9 0 0
T57 443 0 0 0
T65 522 0 0 0
T66 406 0 0 0
T67 424 0 0 0
T68 818 0 0 0
T69 615 0 0 0
T82 527 0 0 0
T88 0 7 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 1332231489 1991 0 0
T6 568425 1 0 0
T8 240611 0 0 0
T11 0 12 0 0
T21 0 9 0 0
T29 52546 0 0 0
T30 0 2 0 0
T32 0 7 0 0
T40 0 10 0 0
T41 0 14 0 0
T42 0 4 0 0
T56 0 9 0 0
T57 53142 0 0 0
T65 251010 0 0 0
T66 48764 0 0 0
T67 53084 0 0 0
T68 393069 0 0 0
T69 21542 0 0 0
T82 63369 0 0 0
T88 0 7 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00

30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin 31 1/1 if (!rst_src_ni) begin Tests: T1 T2 T4  32 1/1 src_level <= 1'b0; Tests: T1 T2 T4  33 end else begin 34 1/1 src_level <= src_level ^ src_pulse_i; Tests: T1 T2 T4  35 end 36 end 37 38 39 // source active must come far enough such that the destination domain has time 40 // to create a valid pulse. 41 `ifdef INC_ASSERT 42 //VCS coverage off 43 // pragma coverage off 44 45 // source active flag tracks whether there is an ongoing "toggle" event. 46 // Until this toggle event is accepted by the destination domain (negative edge of 47 // of the pulse output), the source side cannot toggle again. 48 logic effective_rst_n; 49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o; 50 51 logic src_active_flag_d, src_active_flag_q; 52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q; 53 54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin 55 unreachable if (!effective_rst_n) begin 56 unreachable src_active_flag_q <= '0; 57 end else begin 58 unreachable src_active_flag_q <= src_active_flag_d; 59 end 60 end 61 62 //VCS coverage on 63 // pragma coverage on 64 65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni) 66 `endif 67 68 ////////////////////////////////////////////////////////// 69 // synchronize level signal to destination clock domain // 70 ////////////////////////////////////////////////////////// 71 logic dst_level; 72 73 prim_flop_2sync #(.Width(1)) prim_flop_2sync ( 74 // source clock domain 75 .d_i (src_level), 76 // destination clock domain 77 .clk_i (clk_dst_i), 78 .rst_ni (rst_dst_ni), 79 .q_o (dst_level) 80 ); 81 82 //////////////////////////////////////// 83 // convert level signal back to pulse // 84 //////////////////////////////////////// 85 logic dst_level_q; 86 87 // delay dst_level by 1 cycle 88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin 89 1/1 if (!rst_dst_ni) begin Tests: T1 T2 T4  90 1/1 dst_level_q <= 1'b0; Tests: T1 T2 T4  91 end else begin 92 1/1 dst_level_q <= dst_level; Tests: T1 T2 T4  93 end 94 end 95 96 // edge detection 97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level; Tests: T1 T2 T4 

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT6,T11,T21
10CoveredT6,T11,T21
11CoveredT21,T56,T34

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT6,T11,T21
10CoveredT21,T56,T34
11CoveredT6,T11,T21

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00


31 if (!rst_src_ni) begin -1- 32 src_level <= 1'b0; ==> 33 end else begin 34 src_level <= src_level ^ src_pulse_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


89 if (!rst_dst_ni) begin -1- 90 dst_level_q <= 1'b0; ==> 91 end else begin 92 dst_level_q <= dst_level; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
DstPulseCheck_A 1332231489 1984 0 0
SrcPulseCheck_M 7271325 1984 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1332231489 1984 0 0
T6 568425 1 0 0
T8 240611 0 0 0
T11 0 12 0 0
T21 0 9 0 0
T29 52546 0 0 0
T30 0 2 0 0
T32 0 7 0 0
T40 0 10 0 0
T41 0 14 0 0
T42 0 4 0 0
T56 0 9 0 0
T57 53142 0 0 0
T65 251010 0 0 0
T66 48764 0 0 0
T67 53084 0 0 0
T68 393069 0 0 0
T69 21542 0 0 0
T82 63369 0 0 0
T88 0 7 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 7271325 1984 0 0
T6 7579 1 0 0
T8 627 0 0 0
T11 0 12 0 0
T21 0 9 0 0
T29 456 0 0 0
T30 0 2 0 0
T32 0 7 0 0
T40 0 10 0 0
T41 0 14 0 0
T42 0 4 0 0
T56 0 9 0 0
T57 443 0 0 0
T65 522 0 0 0
T66 406 0 0 0
T67 424 0 0 0
T68 818 0 0 0
T69 615 0 0 0
T82 527 0 0 0
T88 0 7 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00

30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin 31 1/1 if (!rst_src_ni) begin Tests: T1 T2 T4  32 1/1 src_level <= 1'b0; Tests: T1 T2 T4  33 end else begin 34 1/1 src_level <= src_level ^ src_pulse_i; Tests: T1 T2 T4  35 end 36 end 37 38 39 // source active must come far enough such that the destination domain has time 40 // to create a valid pulse. 41 `ifdef INC_ASSERT 42 //VCS coverage off 43 // pragma coverage off 44 45 // source active flag tracks whether there is an ongoing "toggle" event. 46 // Until this toggle event is accepted by the destination domain (negative edge of 47 // of the pulse output), the source side cannot toggle again. 48 logic effective_rst_n; 49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o; 50 51 logic src_active_flag_d, src_active_flag_q; 52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q; 53 54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin 55 unreachable if (!effective_rst_n) begin 56 unreachable src_active_flag_q <= '0; 57 end else begin 58 unreachable src_active_flag_q <= src_active_flag_d; 59 end 60 end 61 62 //VCS coverage on 63 // pragma coverage on 64 65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni) 66 `endif 67 68 ////////////////////////////////////////////////////////// 69 // synchronize level signal to destination clock domain // 70 ////////////////////////////////////////////////////////// 71 logic dst_level; 72 73 prim_flop_2sync #(.Width(1)) prim_flop_2sync ( 74 // source clock domain 75 .d_i (src_level), 76 // destination clock domain 77 .clk_i (clk_dst_i), 78 .rst_ni (rst_dst_ni), 79 .q_o (dst_level) 80 ); 81 82 //////////////////////////////////////// 83 // convert level signal back to pulse // 84 //////////////////////////////////////// 85 logic dst_level_q; 86 87 // delay dst_level by 1 cycle 88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin 89 1/1 if (!rst_dst_ni) begin Tests: T1 T2 T4  90 1/1 dst_level_q <= 1'b0; Tests: T1 T2 T4  91 end else begin 92 1/1 dst_level_q <= dst_level; Tests: T1 T2 T4  93 end 94 end 95 96 // edge detection 97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level; Tests: T1 T2 T31 

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT1,T2,T31
10CoveredT1,T2,T31
11CoveredT21,T56,T34

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT1,T2,T31
10CoveredT21,T56,T34
11CoveredT1,T2,T31

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00


31 if (!rst_src_ni) begin -1- 32 src_level <= 1'b0; ==> 33 end else begin 34 src_level <= src_level ^ src_pulse_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


89 if (!rst_dst_ni) begin -1- 90 dst_level_q <= 1'b0; ==> 91 end else begin 92 dst_level_q <= dst_level; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
DstPulseCheck_A 7271325 2002 0 0
SrcPulseCheck_M 1332231489 2071 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7271325 2002 0 0
T1 509 1 0 0
T2 486 1 0 0
T3 481 0 0 0
T4 666 0 0 0
T6 0 1 0 0
T7 0 1 0 0
T11 0 12 0 0
T12 747 0 0 0
T13 523 0 0 0
T14 412 0 0 0
T15 423 0 0 0
T16 1038 0 0 0
T17 426 0 0 0
T28 0 1 0 0
T29 0 1 0 0
T31 0 1 0 0
T57 0 1 0 0
T59 0 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 1332231489 2071 0 0
T1 63648 1 0 0
T2 58317 1 0 0
T3 215595 0 0 0
T4 43326 0 0 0
T6 0 1 0 0
T7 0 1 0 0
T11 0 12 0 0
T12 18956 0 0 0
T13 128352 0 0 0
T14 195910 0 0 0
T15 101494 0 0 0
T16 129820 0 0 0
T17 51227 0 0 0
T28 0 1 0 0
T29 0 1 0 0
T31 0 1 0 0
T57 0 1 0 0
T59 0 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00

30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin 31 1/1 if (!rst_src_ni) begin Tests: T1 T2 T4  32 1/1 src_level <= 1'b0; Tests: T1 T2 T4  33 end else begin 34 1/1 src_level <= src_level ^ src_pulse_i; Tests: T1 T2 T4  35 end 36 end 37 38 39 // source active must come far enough such that the destination domain has time 40 // to create a valid pulse. 41 `ifdef INC_ASSERT 42 //VCS coverage off 43 // pragma coverage off 44 45 // source active flag tracks whether there is an ongoing "toggle" event. 46 // Until this toggle event is accepted by the destination domain (negative edge of 47 // of the pulse output), the source side cannot toggle again. 48 logic effective_rst_n; 49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o; 50 51 logic src_active_flag_d, src_active_flag_q; 52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q; 53 54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin 55 unreachable if (!effective_rst_n) begin 56 unreachable src_active_flag_q <= '0; 57 end else begin 58 unreachable src_active_flag_q <= src_active_flag_d; 59 end 60 end 61 62 //VCS coverage on 63 // pragma coverage on 64 65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni) 66 `endif 67 68 ////////////////////////////////////////////////////////// 69 // synchronize level signal to destination clock domain // 70 ////////////////////////////////////////////////////////// 71 logic dst_level; 72 73 prim_flop_2sync #(.Width(1)) prim_flop_2sync ( 74 // source clock domain 75 .d_i (src_level), 76 // destination clock domain 77 .clk_i (clk_dst_i), 78 .rst_ni (rst_dst_ni), 79 .q_o (dst_level) 80 ); 81 82 //////////////////////////////////////// 83 // convert level signal back to pulse // 84 //////////////////////////////////////// 85 logic dst_level_q; 86 87 // delay dst_level by 1 cycle 88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin 89 1/1 if (!rst_dst_ni) begin Tests: T1 T2 T4  90 1/1 dst_level_q <= 1'b0; Tests: T1 T2 T4  91 end else begin 92 1/1 dst_level_q <= dst_level; Tests: T1 T2 T4  93 end 94 end 95 96 // edge detection 97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level; Tests: T1 T2 T4 

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT1,T2,T31
10CoveredT1,T2,T31
11CoveredT21,T56,T34

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT1,T2,T31
10CoveredT21,T56,T34
11CoveredT1,T2,T31

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00


31 if (!rst_src_ni) begin -1- 32 src_level <= 1'b0; ==> 33 end else begin 34 src_level <= src_level ^ src_pulse_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


89 if (!rst_dst_ni) begin -1- 90 dst_level_q <= 1'b0; ==> 91 end else begin 92 dst_level_q <= dst_level; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
DstPulseCheck_A 1332231489 2064 0 0
SrcPulseCheck_M 7271325 2064 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1332231489 2064 0 0
T1 63648 1 0 0
T2 58317 1 0 0
T3 215595 0 0 0
T4 43326 0 0 0
T6 0 1 0 0
T7 0 1 0 0
T11 0 12 0 0
T12 18956 0 0 0
T13 128352 0 0 0
T14 195910 0 0 0
T15 101494 0 0 0
T16 129820 0 0 0
T17 51227 0 0 0
T28 0 1 0 0
T29 0 1 0 0
T31 0 1 0 0
T57 0 1 0 0
T59 0 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 7271325 2064 0 0
T1 509 1 0 0
T2 486 1 0 0
T3 481 0 0 0
T4 666 0 0 0
T6 0 1 0 0
T7 0 1 0 0
T11 0 12 0 0
T12 747 0 0 0
T13 523 0 0 0
T14 412 0 0 0
T15 423 0 0 0
T16 1038 0 0 0
T17 426 0 0 0
T28 0 1 0 0
T29 0 1 0 0
T31 0 1 0 0
T57 0 1 0 0
T59 0 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00

30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin 31 1/1 if (!rst_src_ni) begin Tests: T1 T2 T4  32 1/1 src_level <= 1'b0; Tests: T1 T2 T4  33 end else begin 34 1/1 src_level <= src_level ^ src_pulse_i; Tests: T1 T2 T4  35 end 36 end 37 38 39 // source active must come far enough such that the destination domain has time 40 // to create a valid pulse. 41 `ifdef INC_ASSERT 42 //VCS coverage off 43 // pragma coverage off 44 45 // source active flag tracks whether there is an ongoing "toggle" event. 46 // Until this toggle event is accepted by the destination domain (negative edge of 47 // of the pulse output), the source side cannot toggle again. 48 logic effective_rst_n; 49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o; 50 51 logic src_active_flag_d, src_active_flag_q; 52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q; 53 54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin 55 unreachable if (!effective_rst_n) begin 56 unreachable src_active_flag_q <= '0; 57 end else begin 58 unreachable src_active_flag_q <= src_active_flag_d; 59 end 60 end 61 62 //VCS coverage on 63 // pragma coverage on 64 65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni) 66 `endif 67 68 ////////////////////////////////////////////////////////// 69 // synchronize level signal to destination clock domain // 70 ////////////////////////////////////////////////////////// 71 logic dst_level; 72 73 prim_flop_2sync #(.Width(1)) prim_flop_2sync ( 74 // source clock domain 75 .d_i (src_level), 76 // destination clock domain 77 .clk_i (clk_dst_i), 78 .rst_ni (rst_dst_ni), 79 .q_o (dst_level) 80 ); 81 82 //////////////////////////////////////// 83 // convert level signal back to pulse // 84 //////////////////////////////////////// 85 logic dst_level_q; 86 87 // delay dst_level by 1 cycle 88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin 89 1/1 if (!rst_dst_ni) begin Tests: T1 T2 T4  90 1/1 dst_level_q <= 1'b0; Tests: T1 T2 T4  91 end else begin 92 1/1 dst_level_q <= dst_level; Tests: T1 T2 T4  93 end 94 end 95 96 // edge detection 97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level; Tests: T6 T11 T21 

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT6,T11,T21
10CoveredT6,T11,T21
11CoveredT21,T56,T34

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT6,T11,T21
10CoveredT21,T56,T34
11CoveredT6,T11,T21

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00


31 if (!rst_src_ni) begin -1- 32 src_level <= 1'b0; ==> 33 end else begin 34 src_level <= src_level ^ src_pulse_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


89 if (!rst_dst_ni) begin -1- 90 dst_level_q <= 1'b0; ==> 91 end else begin 92 dst_level_q <= dst_level; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
DstPulseCheck_A 7271325 1937 0 0
SrcPulseCheck_M 1332231489 2006 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7271325 1937 0 0
T6 7579 1 0 0
T8 627 0 0 0
T11 0 12 0 0
T21 0 9 0 0
T29 456 0 0 0
T30 0 2 0 0
T32 0 7 0 0
T40 0 10 0 0
T41 0 14 0 0
T42 0 4 0 0
T56 0 9 0 0
T57 443 0 0 0
T65 522 0 0 0
T66 406 0 0 0
T67 424 0 0 0
T68 818 0 0 0
T69 615 0 0 0
T82 527 0 0 0
T88 0 7 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 1332231489 2006 0 0
T6 568425 1 0 0
T8 240611 0 0 0
T11 0 12 0 0
T21 0 9 0 0
T29 52546 0 0 0
T30 0 2 0 0
T32 0 7 0 0
T40 0 10 0 0
T41 0 14 0 0
T42 0 4 0 0
T56 0 9 0 0
T57 53142 0 0 0
T65 251010 0 0 0
T66 48764 0 0 0
T67 53084 0 0 0
T68 393069 0 0 0
T69 21542 0 0 0
T82 63369 0 0 0
T88 0 7 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00

30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin 31 1/1 if (!rst_src_ni) begin Tests: T1 T2 T4  32 1/1 src_level <= 1'b0; Tests: T1 T2 T4  33 end else begin 34 1/1 src_level <= src_level ^ src_pulse_i; Tests: T1 T2 T4  35 end 36 end 37 38 39 // source active must come far enough such that the destination domain has time 40 // to create a valid pulse. 41 `ifdef INC_ASSERT 42 //VCS coverage off 43 // pragma coverage off 44 45 // source active flag tracks whether there is an ongoing "toggle" event. 46 // Until this toggle event is accepted by the destination domain (negative edge of 47 // of the pulse output), the source side cannot toggle again. 48 logic effective_rst_n; 49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o; 50 51 logic src_active_flag_d, src_active_flag_q; 52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q; 53 54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin 55 unreachable if (!effective_rst_n) begin 56 unreachable src_active_flag_q <= '0; 57 end else begin 58 unreachable src_active_flag_q <= src_active_flag_d; 59 end 60 end 61 62 //VCS coverage on 63 // pragma coverage on 64 65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni) 66 `endif 67 68 ////////////////////////////////////////////////////////// 69 // synchronize level signal to destination clock domain // 70 ////////////////////////////////////////////////////////// 71 logic dst_level; 72 73 prim_flop_2sync #(.Width(1)) prim_flop_2sync ( 74 // source clock domain 75 .d_i (src_level), 76 // destination clock domain 77 .clk_i (clk_dst_i), 78 .rst_ni (rst_dst_ni), 79 .q_o (dst_level) 80 ); 81 82 //////////////////////////////////////// 83 // convert level signal back to pulse // 84 //////////////////////////////////////// 85 logic dst_level_q; 86 87 // delay dst_level by 1 cycle 88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin 89 1/1 if (!rst_dst_ni) begin Tests: T1 T2 T4  90 1/1 dst_level_q <= 1'b0; Tests: T1 T2 T4  91 end else begin 92 1/1 dst_level_q <= dst_level; Tests: T1 T2 T4  93 end 94 end 95 96 // edge detection 97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level; Tests: T1 T2 T4 

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT6,T11,T21
10CoveredT6,T11,T21
11CoveredT21,T56,T34

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT6,T11,T21
10CoveredT21,T56,T34
11CoveredT6,T11,T21

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00


31 if (!rst_src_ni) begin -1- 32 src_level <= 1'b0; ==> 33 end else begin 34 src_level <= src_level ^ src_pulse_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


89 if (!rst_dst_ni) begin -1- 90 dst_level_q <= 1'b0; ==> 91 end else begin 92 dst_level_q <= dst_level; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
DstPulseCheck_A 1332231489 2000 0 0
SrcPulseCheck_M 7271325 2000 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1332231489 2000 0 0
T6 568425 1 0 0
T8 240611 0 0 0
T11 0 12 0 0
T21 0 9 0 0
T29 52546 0 0 0
T30 0 2 0 0
T32 0 7 0 0
T40 0 10 0 0
T41 0 14 0 0
T42 0 4 0 0
T56 0 9 0 0
T57 53142 0 0 0
T65 251010 0 0 0
T66 48764 0 0 0
T67 53084 0 0 0
T68 393069 0 0 0
T69 21542 0 0 0
T82 63369 0 0 0
T88 0 7 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 7271325 2000 0 0
T6 7579 1 0 0
T8 627 0 0 0
T11 0 12 0 0
T21 0 9 0 0
T29 456 0 0 0
T30 0 2 0 0
T32 0 7 0 0
T40 0 10 0 0
T41 0 14 0 0
T42 0 4 0 0
T56 0 9 0 0
T57 443 0 0 0
T65 522 0 0 0
T66 406 0 0 0
T67 424 0 0 0
T68 818 0 0 0
T69 615 0 0 0
T82 527 0 0 0
T88 0 7 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00

30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin 31 1/1 if (!rst_src_ni) begin Tests: T1 T2 T4  32 1/1 src_level <= 1'b0; Tests: T1 T2 T4  33 end else begin 34 1/1 src_level <= src_level ^ src_pulse_i; Tests: T1 T2 T4  35 end 36 end 37 38 39 // source active must come far enough such that the destination domain has time 40 // to create a valid pulse. 41 `ifdef INC_ASSERT 42 //VCS coverage off 43 // pragma coverage off 44 45 // source active flag tracks whether there is an ongoing "toggle" event. 46 // Until this toggle event is accepted by the destination domain (negative edge of 47 // of the pulse output), the source side cannot toggle again. 48 logic effective_rst_n; 49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o; 50 51 logic src_active_flag_d, src_active_flag_q; 52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q; 53 54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin 55 unreachable if (!effective_rst_n) begin 56 unreachable src_active_flag_q <= '0; 57 end else begin 58 unreachable src_active_flag_q <= src_active_flag_d; 59 end 60 end 61 62 //VCS coverage on 63 // pragma coverage on 64 65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni) 66 `endif 67 68 ////////////////////////////////////////////////////////// 69 // synchronize level signal to destination clock domain // 70 ////////////////////////////////////////////////////////// 71 logic dst_level; 72 73 prim_flop_2sync #(.Width(1)) prim_flop_2sync ( 74 // source clock domain 75 .d_i (src_level), 76 // destination clock domain 77 .clk_i (clk_dst_i), 78 .rst_ni (rst_dst_ni), 79 .q_o (dst_level) 80 ); 81 82 //////////////////////////////////////// 83 // convert level signal back to pulse // 84 //////////////////////////////////////// 85 logic dst_level_q; 86 87 // delay dst_level by 1 cycle 88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin 89 1/1 if (!rst_dst_ni) begin Tests: T1 T2 T4  90 1/1 dst_level_q <= 1'b0; Tests: T1 T2 T4  91 end else begin 92 1/1 dst_level_q <= dst_level; Tests: T1 T2 T4  93 end 94 end 95 96 // edge detection 97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level; Tests: T6 T11 T21 

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT6,T11,T21
10CoveredT6,T11,T21
11CoveredT21,T56,T34

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT6,T11,T21
10CoveredT21,T56,T34
11CoveredT6,T11,T21

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00


31 if (!rst_src_ni) begin -1- 32 src_level <= 1'b0; ==> 33 end else begin 34 src_level <= src_level ^ src_pulse_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


89 if (!rst_dst_ni) begin -1- 90 dst_level_q <= 1'b0; ==> 91 end else begin 92 dst_level_q <= dst_level; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
DstPulseCheck_A 7271325 1895 0 0
SrcPulseCheck_M 1332231489 1962 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7271325 1895 0 0
T6 7579 1 0 0
T8 627 0 0 0
T11 0 12 0 0
T21 0 9 0 0
T29 456 0 0 0
T30 0 2 0 0
T32 0 7 0 0
T40 0 10 0 0
T41 0 14 0 0
T42 0 4 0 0
T56 0 9 0 0
T57 443 0 0 0
T65 522 0 0 0
T66 406 0 0 0
T67 424 0 0 0
T68 818 0 0 0
T69 615 0 0 0
T82 527 0 0 0
T88 0 7 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 1332231489 1962 0 0
T6 568425 1 0 0
T8 240611 0 0 0
T11 0 12 0 0
T21 0 9 0 0
T29 52546 0 0 0
T30 0 2 0 0
T32 0 7 0 0
T40 0 10 0 0
T41 0 14 0 0
T42 0 4 0 0
T56 0 9 0 0
T57 53142 0 0 0
T65 251010 0 0 0
T66 48764 0 0 0
T67 53084 0 0 0
T68 393069 0 0 0
T69 21542 0 0 0
T82 63369 0 0 0
T88 0 7 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00

30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin 31 1/1 if (!rst_src_ni) begin Tests: T1 T2 T4  32 1/1 src_level <= 1'b0; Tests: T1 T2 T4  33 end else begin 34 1/1 src_level <= src_level ^ src_pulse_i; Tests: T1 T2 T4  35 end 36 end 37 38 39 // source active must come far enough such that the destination domain has time 40 // to create a valid pulse. 41 `ifdef INC_ASSERT 42 //VCS coverage off 43 // pragma coverage off 44 45 // source active flag tracks whether there is an ongoing "toggle" event. 46 // Until this toggle event is accepted by the destination domain (negative edge of 47 // of the pulse output), the source side cannot toggle again. 48 logic effective_rst_n; 49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o; 50 51 logic src_active_flag_d, src_active_flag_q; 52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q; 53 54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin 55 unreachable if (!effective_rst_n) begin 56 unreachable src_active_flag_q <= '0; 57 end else begin 58 unreachable src_active_flag_q <= src_active_flag_d; 59 end 60 end 61 62 //VCS coverage on 63 // pragma coverage on 64 65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni) 66 `endif 67 68 ////////////////////////////////////////////////////////// 69 // synchronize level signal to destination clock domain // 70 ////////////////////////////////////////////////////////// 71 logic dst_level; 72 73 prim_flop_2sync #(.Width(1)) prim_flop_2sync ( 74 // source clock domain 75 .d_i (src_level), 76 // destination clock domain 77 .clk_i (clk_dst_i), 78 .rst_ni (rst_dst_ni), 79 .q_o (dst_level) 80 ); 81 82 //////////////////////////////////////// 83 // convert level signal back to pulse // 84 //////////////////////////////////////// 85 logic dst_level_q; 86 87 // delay dst_level by 1 cycle 88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin 89 1/1 if (!rst_dst_ni) begin Tests: T1 T2 T4  90 1/1 dst_level_q <= 1'b0; Tests: T1 T2 T4  91 end else begin 92 1/1 dst_level_q <= dst_level; Tests: T1 T2 T4  93 end 94 end 95 96 // edge detection 97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level; Tests: T1 T2 T4 

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT6,T11,T21
10CoveredT6,T11,T21
11CoveredT21,T56,T34

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT6,T11,T21
10CoveredT21,T56,T34
11CoveredT6,T11,T21

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00


31 if (!rst_src_ni) begin -1- 32 src_level <= 1'b0; ==> 33 end else begin 34 src_level <= src_level ^ src_pulse_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


89 if (!rst_dst_ni) begin -1- 90 dst_level_q <= 1'b0; ==> 91 end else begin 92 dst_level_q <= dst_level; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
DstPulseCheck_A 1332231489 1955 0 0
SrcPulseCheck_M 7271325 1955 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1332231489 1955 0 0
T6 568425 1 0 0
T8 240611 0 0 0
T11 0 12 0 0
T21 0 9 0 0
T29 52546 0 0 0
T30 0 2 0 0
T32 0 7 0 0
T40 0 10 0 0
T41 0 14 0 0
T42 0 4 0 0
T56 0 9 0 0
T57 53142 0 0 0
T65 251010 0 0 0
T66 48764 0 0 0
T67 53084 0 0 0
T68 393069 0 0 0
T69 21542 0 0 0
T82 63369 0 0 0
T88 0 7 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 7271325 1955 0 0
T6 7579 1 0 0
T8 627 0 0 0
T11 0 12 0 0
T21 0 9 0 0
T29 456 0 0 0
T30 0 2 0 0
T32 0 7 0 0
T40 0 10 0 0
T41 0 14 0 0
T42 0 4 0 0
T56 0 9 0 0
T57 443 0 0 0
T65 522 0 0 0
T66 406 0 0 0
T67 424 0 0 0
T68 818 0 0 0
T69 615 0 0 0
T82 527 0 0 0
T88 0 7 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00

30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin 31 1/1 if (!rst_src_ni) begin Tests: T1 T2 T4  32 1/1 src_level <= 1'b0; Tests: T1 T2 T4  33 end else begin 34 1/1 src_level <= src_level ^ src_pulse_i; Tests: T1 T2 T4  35 end 36 end 37 38 39 // source active must come far enough such that the destination domain has time 40 // to create a valid pulse. 41 `ifdef INC_ASSERT 42 //VCS coverage off 43 // pragma coverage off 44 45 // source active flag tracks whether there is an ongoing "toggle" event. 46 // Until this toggle event is accepted by the destination domain (negative edge of 47 // of the pulse output), the source side cannot toggle again. 48 logic effective_rst_n; 49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o; 50 51 logic src_active_flag_d, src_active_flag_q; 52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q; 53 54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin 55 unreachable if (!effective_rst_n) begin 56 unreachable src_active_flag_q <= '0; 57 end else begin 58 unreachable src_active_flag_q <= src_active_flag_d; 59 end 60 end 61 62 //VCS coverage on 63 // pragma coverage on 64 65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni) 66 `endif 67 68 ////////////////////////////////////////////////////////// 69 // synchronize level signal to destination clock domain // 70 ////////////////////////////////////////////////////////// 71 logic dst_level; 72 73 prim_flop_2sync #(.Width(1)) prim_flop_2sync ( 74 // source clock domain 75 .d_i (src_level), 76 // destination clock domain 77 .clk_i (clk_dst_i), 78 .rst_ni (rst_dst_ni), 79 .q_o (dst_level) 80 ); 81 82 //////////////////////////////////////// 83 // convert level signal back to pulse // 84 //////////////////////////////////////// 85 logic dst_level_q; 86 87 // delay dst_level by 1 cycle 88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin 89 1/1 if (!rst_dst_ni) begin Tests: T1 T2 T4  90 1/1 dst_level_q <= 1'b0; Tests: T1 T2 T4  91 end else begin 92 1/1 dst_level_q <= dst_level; Tests: T1 T2 T4  93 end 94 end 95 96 // edge detection 97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level; Tests: T6 T11 T21 

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT6,T11,T21
10CoveredT6,T11,T21
11CoveredT21,T56,T34

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT6,T11,T21
10CoveredT21,T56,T34
11CoveredT6,T11,T21

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00


31 if (!rst_src_ni) begin -1- 32 src_level <= 1'b0; ==> 33 end else begin 34 src_level <= src_level ^ src_pulse_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


89 if (!rst_dst_ni) begin -1- 90 dst_level_q <= 1'b0; ==> 91 end else begin 92 dst_level_q <= dst_level; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
DstPulseCheck_A 7271325 1907 0 0
SrcPulseCheck_M 1332231489 1970 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7271325 1907 0 0
T6 7579 1 0 0
T8 627 0 0 0
T11 0 12 0 0
T21 0 9 0 0
T29 456 0 0 0
T30 0 2 0 0
T32 0 7 0 0
T40 0 10 0 0
T41 0 14 0 0
T42 0 4 0 0
T56 0 9 0 0
T57 443 0 0 0
T65 522 0 0 0
T66 406 0 0 0
T67 424 0 0 0
T68 818 0 0 0
T69 615 0 0 0
T82 527 0 0 0
T88 0 7 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 1332231489 1970 0 0
T6 568425 1 0 0
T8 240611 0 0 0
T11 0 12 0 0
T21 0 9 0 0
T29 52546 0 0 0
T30 0 2 0 0
T32 0 7 0 0
T40 0 10 0 0
T41 0 14 0 0
T42 0 4 0 0
T56 0 9 0 0
T57 53142 0 0 0
T65 251010 0 0 0
T66 48764 0 0 0
T67 53084 0 0 0
T68 393069 0 0 0
T69 21542 0 0 0
T82 63369 0 0 0
T88 0 7 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00

30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin 31 1/1 if (!rst_src_ni) begin Tests: T1 T2 T4  32 1/1 src_level <= 1'b0; Tests: T1 T2 T4  33 end else begin 34 1/1 src_level <= src_level ^ src_pulse_i; Tests: T1 T2 T4  35 end 36 end 37 38 39 // source active must come far enough such that the destination domain has time 40 // to create a valid pulse. 41 `ifdef INC_ASSERT 42 //VCS coverage off 43 // pragma coverage off 44 45 // source active flag tracks whether there is an ongoing "toggle" event. 46 // Until this toggle event is accepted by the destination domain (negative edge of 47 // of the pulse output), the source side cannot toggle again. 48 logic effective_rst_n; 49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o; 50 51 logic src_active_flag_d, src_active_flag_q; 52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q; 53 54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin 55 unreachable if (!effective_rst_n) begin 56 unreachable src_active_flag_q <= '0; 57 end else begin 58 unreachable src_active_flag_q <= src_active_flag_d; 59 end 60 end 61 62 //VCS coverage on 63 // pragma coverage on 64 65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni) 66 `endif 67 68 ////////////////////////////////////////////////////////// 69 // synchronize level signal to destination clock domain // 70 ////////////////////////////////////////////////////////// 71 logic dst_level; 72 73 prim_flop_2sync #(.Width(1)) prim_flop_2sync ( 74 // source clock domain 75 .d_i (src_level), 76 // destination clock domain 77 .clk_i (clk_dst_i), 78 .rst_ni (rst_dst_ni), 79 .q_o (dst_level) 80 ); 81 82 //////////////////////////////////////// 83 // convert level signal back to pulse // 84 //////////////////////////////////////// 85 logic dst_level_q; 86 87 // delay dst_level by 1 cycle 88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin 89 1/1 if (!rst_dst_ni) begin Tests: T1 T2 T4  90 1/1 dst_level_q <= 1'b0; Tests: T1 T2 T4  91 end else begin 92 1/1 dst_level_q <= dst_level; Tests: T1 T2 T4  93 end 94 end 95 96 // edge detection 97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level; Tests: T1 T2 T4 

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT6,T11,T21
10CoveredT6,T11,T21
11CoveredT21,T56,T34

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT6,T11,T21
10CoveredT21,T56,T34
11CoveredT6,T11,T21

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00


31 if (!rst_src_ni) begin -1- 32 src_level <= 1'b0; ==> 33 end else begin 34 src_level <= src_level ^ src_pulse_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


89 if (!rst_dst_ni) begin -1- 90 dst_level_q <= 1'b0; ==> 91 end else begin 92 dst_level_q <= dst_level; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
DstPulseCheck_A 1332231489 1964 0 0
SrcPulseCheck_M 7271325 1964 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1332231489 1964 0 0
T6 568425 1 0 0
T8 240611 0 0 0
T11 0 12 0 0
T21 0 9 0 0
T29 52546 0 0 0
T30 0 2 0 0
T32 0 7 0 0
T40 0 10 0 0
T41 0 14 0 0
T42 0 4 0 0
T56 0 9 0 0
T57 53142 0 0 0
T65 251010 0 0 0
T66 48764 0 0 0
T67 53084 0 0 0
T68 393069 0 0 0
T69 21542 0 0 0
T82 63369 0 0 0
T88 0 7 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 7271325 1964 0 0
T6 7579 1 0 0
T8 627 0 0 0
T11 0 12 0 0
T21 0 9 0 0
T29 456 0 0 0
T30 0 2 0 0
T32 0 7 0 0
T40 0 10 0 0
T41 0 14 0 0
T42 0 4 0 0
T56 0 9 0 0
T57 443 0 0 0
T65 522 0 0 0
T66 406 0 0 0
T67 424 0 0 0
T68 818 0 0 0
T69 615 0 0 0
T82 527 0 0 0
T88 0 7 0 0