Group : sysrst_ctrl_env_pkg::sysrst_ctrl_auto_blk_key_output_vseq::sysrst_ctrl_auto_blk_out_ctl_cg
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Group : sysrst_ctrl_env_pkg::sysrst_ctrl_auto_blk_key_output_vseq::sysrst_ctrl_auto_blk_out_ctl_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 92.50 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/seq_lib/sysrst_ctrl_auto_blk_key_output_vseq.sv

5 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
sysrst_ctrl_auto_blk_out_ctl_cg_(4) 75.00 1 100 1 64 64
sysrst_ctrl_auto_blk_out_ctl_cg_(3) 87.50 1 100 1 64 64
sysrst_ctrl_auto_blk_out_ctl_cg 100.00 1 100 1 64 64
sysrst_ctrl_auto_blk_out_ctl_cg_(1) 100.00 1 100 1 64 64
sysrst_ctrl_auto_blk_out_ctl_cg_(2) 100.00 1 100 1 64 64




Group Instance : sysrst_ctrl_auto_blk_out_ctl_cg_(4)
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
75.00 1 100 1 64 64




Summary for Group Instance sysrst_ctrl_auto_blk_out_ctl_cg_(4)

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 1 11 91.67
Crosses 12 5 7 58.33


Variables for Group Instance sysrst_ctrl_auto_blk_out_ctl_cg_(4)
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_key0_out_sel 2 0 2 100.00 100 1 1 2
cp_key0_out_value 2 0 2 100.00 100 1 1 2
cp_key1_out_sel 2 0 2 100.00 100 1 1 2
cp_key1_out_value 2 1 1 50.00 100 1 1 2
cp_key2_out_sel 2 0 2 100.00 100 1 1 2
cp_key2_out_value 2 0 2 100.00 100 1 1 2


Crosses for Group Instance sysrst_ctrl_auto_blk_out_ctl_cg_(4)
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cross_key0_out_sel_value 4 1 3 75.00 100 1 1 0
cross_key1_out_sel_value 4 2 2 50.00 100 1 1 0
cross_key2_out_sel_value 4 2 2 50.00 100 1 1 0



Group Instance : sysrst_ctrl_auto_blk_out_ctl_cg_(3)
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
87.50 1 100 1 64 64




Summary for Group Instance sysrst_ctrl_auto_blk_out_ctl_cg_(3)

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00
Crosses 12 3 9 75.00


Variables for Group Instance sysrst_ctrl_auto_blk_out_ctl_cg_(3)
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_key0_out_sel 2 0 2 100.00 100 1 1 2
cp_key0_out_value 2 0 2 100.00 100 1 1 2
cp_key1_out_sel 2 0 2 100.00 100 1 1 2
cp_key1_out_value 2 0 2 100.00 100 1 1 2
cp_key2_out_sel 2 0 2 100.00 100 1 1 2
cp_key2_out_value 2 0 2 100.00 100 1 1 2


Crosses for Group Instance sysrst_ctrl_auto_blk_out_ctl_cg_(3)
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cross_key0_out_sel_value 4 1 3 75.00 100 1 1 0
cross_key1_out_sel_value 4 1 3 75.00 100 1 1 0
cross_key2_out_sel_value 4 1 3 75.00 100 1 1 0



Group Instance : sysrst_ctrl_auto_blk_out_ctl_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance sysrst_ctrl_auto_blk_out_ctl_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00
Crosses 12 0 12 100.00


Variables for Group Instance sysrst_ctrl_auto_blk_out_ctl_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_key0_out_sel 2 0 2 100.00 100 1 1 2
cp_key0_out_value 2 0 2 100.00 100 1 1 2
cp_key1_out_sel 2 0 2 100.00 100 1 1 2
cp_key1_out_value 2 0 2 100.00 100 1 1 2
cp_key2_out_sel 2 0 2 100.00 100 1 1 2
cp_key2_out_value 2 0 2 100.00 100 1 1 2


Crosses for Group Instance sysrst_ctrl_auto_blk_out_ctl_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cross_key0_out_sel_value 4 0 4 100.00 100 1 1 0
cross_key1_out_sel_value 4 0 4 100.00 100 1 1 0
cross_key2_out_sel_value 4 0 4 100.00 100 1 1 0



Group Instance : sysrst_ctrl_auto_blk_out_ctl_cg_(1)
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance sysrst_ctrl_auto_blk_out_ctl_cg_(1)

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00
Crosses 12 0 12 100.00


Variables for Group Instance sysrst_ctrl_auto_blk_out_ctl_cg_(1)
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_key0_out_sel 2 0 2 100.00 100 1 1 2
cp_key0_out_value 2 0 2 100.00 100 1 1 2
cp_key1_out_sel 2 0 2 100.00 100 1 1 2
cp_key1_out_value 2 0 2 100.00 100 1 1 2
cp_key2_out_sel 2 0 2 100.00 100 1 1 2
cp_key2_out_value 2 0 2 100.00 100 1 1 2


Crosses for Group Instance sysrst_ctrl_auto_blk_out_ctl_cg_(1)
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cross_key0_out_sel_value 4 0 4 100.00 100 1 1 0
cross_key1_out_sel_value 4 0 4 100.00 100 1 1 0
cross_key2_out_sel_value 4 0 4 100.00 100 1 1 0



Group Instance : sysrst_ctrl_auto_blk_out_ctl_cg_(2)
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance sysrst_ctrl_auto_blk_out_ctl_cg_(2)

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00
Crosses 12 0 12 100.00


Variables for Group Instance sysrst_ctrl_auto_blk_out_ctl_cg_(2)
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_key0_out_sel 2 0 2 100.00 100 1 1 2
cp_key0_out_value 2 0 2 100.00 100 1 1 2
cp_key1_out_sel 2 0 2 100.00 100 1 1 2
cp_key1_out_value 2 0 2 100.00 100 1 1 2
cp_key2_out_sel 2 0 2 100.00 100 1 1 2
cp_key2_out_value 2 0 2 100.00 100 1 1 2


Crosses for Group Instance sysrst_ctrl_auto_blk_out_ctl_cg_(2)
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cross_key0_out_sel_value 4 0 4 100.00 100 1 1 0
cross_key1_out_sel_value 4 0 4 100.00 100 1 1 0
cross_key2_out_sel_value 4 0 4 100.00 100 1 1 0


Summary for Variable cp_key0_out_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key0_out_sel

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNT
auto[0] 2 1 T94 2
auto[1] 1 1 T94 1



Summary for Variable cp_key0_out_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key0_out_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNT
auto[0] 2 1 T94 2
auto[1] 1 1 T94 1



Summary for Variable cp_key1_out_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key1_out_sel

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNT
auto[0] 1 1 T94 1
auto[1] 2 1 T94 2



Summary for Variable cp_key1_out_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_key1_out_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[0]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNT
auto[1] 3 1 T94 3



Summary for Variable cp_key2_out_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key2_out_sel

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNT
auto[0] 1 1 T94 1
auto[1] 2 1 T94 2



Summary for Variable cp_key2_out_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key2_out_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNT
auto[0] 1 1 T94 1
auto[1] 2 1 T94 2



Summary for Cross cross_key0_out_sel_value

Samples crossed: cp_key0_out_value cp_key0_out_sel
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 1 3 75.00 1


Automatically Generated Cross Bins for cross_key0_out_sel_value

Uncovered bins
cp_key0_out_valuecp_key0_out_selCOUNTAT LEASTNUMBERSTATUS
[auto[1]] [auto[1]] 0 1 1


Covered bins
cp_key0_out_valuecp_key0_out_selCOUNTAT LEASTSTATUSTESTCOUNT
auto[0] auto[0] 1 1 T94 1
auto[0] auto[1] 1 1 T94 1
auto[1] auto[0] 1 1 T94 1



Summary for Cross cross_key1_out_sel_value

Samples crossed: cp_key1_out_value cp_key1_out_sel
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 2 2 50.00 2


Automatically Generated Cross Bins for cross_key1_out_sel_value

Element holes
cp_key1_out_valuecp_key1_out_selCOUNTAT LEASTNUMBERSTATUS
[auto[0]] * -- -- 2


Covered bins
cp_key1_out_valuecp_key1_out_selCOUNTAT LEASTSTATUSTESTCOUNT
auto[1] auto[0] 1 1 T94 1
auto[1] auto[1] 2 1 T94 2



Summary for Cross cross_key2_out_sel_value

Samples crossed: cp_key2_out_value cp_key2_out_sel
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 2 2 50.00 2


Automatically Generated Cross Bins for cross_key2_out_sel_value

Uncovered bins
cp_key2_out_valuecp_key2_out_selCOUNTAT LEASTNUMBERSTATUS
[auto[0]] [auto[1]] 0 1 1
[auto[1]] [auto[0]] 0 1 1


Covered bins
cp_key2_out_valuecp_key2_out_selCOUNTAT LEASTSTATUSTESTCOUNT
auto[0] auto[0] 1 1 T94 1
auto[1] auto[1] 2 1 T94 2


Summary for Variable cp_key0_out_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key0_out_sel

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNT
auto[0] 4 1 T192 1 T381 3
auto[1] 2 1 T192 2 - -



Summary for Variable cp_key0_out_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key0_out_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNT
auto[0] 2 1 T192 1 T381 1
auto[1] 4 1 T192 2 T381 2



Summary for Variable cp_key1_out_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key1_out_sel

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNT
auto[0] 1 1 T192 1 - -
auto[1] 5 1 T192 2 T381 3



Summary for Variable cp_key1_out_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key1_out_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNT
auto[0] 3 1 T192 2 T381 1
auto[1] 3 1 T192 1 T381 2



Summary for Variable cp_key2_out_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key2_out_sel

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNT
auto[0] 1 1 T192 1 - -
auto[1] 5 1 T192 2 T381 3



Summary for Variable cp_key2_out_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key2_out_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNT
auto[0] 3 1 T192 1 T381 2
auto[1] 3 1 T192 2 T381 1



Summary for Cross cross_key0_out_sel_value

Samples crossed: cp_key0_out_value cp_key0_out_sel
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 1 3 75.00 1


Automatically Generated Cross Bins for cross_key0_out_sel_value

Uncovered bins
cp_key0_out_valuecp_key0_out_selCOUNTAT LEASTNUMBERSTATUS
[auto[0]] [auto[1]] 0 1 1


Covered bins
cp_key0_out_valuecp_key0_out_selCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNT
auto[0] auto[0] 2 1 T192 1 T381 1
auto[1] auto[0] 2 1 T381 2 - -
auto[1] auto[1] 2 1 T192 2 - -



Summary for Cross cross_key1_out_sel_value

Samples crossed: cp_key1_out_value cp_key1_out_sel
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 1 3 75.00 1


Automatically Generated Cross Bins for cross_key1_out_sel_value

Uncovered bins
cp_key1_out_valuecp_key1_out_selCOUNTAT LEASTNUMBERSTATUS
[auto[1]] [auto[0]] 0 1 1


Covered bins
cp_key1_out_valuecp_key1_out_selCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNT
auto[0] auto[0] 1 1 T192 1 - -
auto[0] auto[1] 2 1 T192 1 T381 1
auto[1] auto[1] 3 1 T192 1 T381 2



Summary for Cross cross_key2_out_sel_value

Samples crossed: cp_key2_out_value cp_key2_out_sel
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 1 3 75.00 1


Automatically Generated Cross Bins for cross_key2_out_sel_value

Uncovered bins
cp_key2_out_valuecp_key2_out_selCOUNTAT LEASTNUMBERSTATUS
[auto[0]] [auto[0]] 0 1 1


Covered bins
cp_key2_out_valuecp_key2_out_selCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNT
auto[0] auto[1] 3 1 T192 1 T381 2
auto[1] auto[0] 1 1 T192 1 - -
auto[1] auto[1] 2 1 T192 1 T381 1


Summary for Variable cp_key0_out_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key0_out_sel

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 113 1 T4 2 T25 1 T26 1
auto[1] 129 1 T4 1 T25 2 T26 2



Summary for Variable cp_key0_out_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key0_out_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 114 1 T4 2 T26 2 T43 2
auto[1] 128 1 T4 1 T25 3 T26 1



Summary for Variable cp_key1_out_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key1_out_sel

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 126 1 T4 1 T25 1 T26 1
auto[1] 116 1 T4 2 T25 2 T26 2



Summary for Variable cp_key1_out_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key1_out_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 114 1 T4 2 T25 2 T26 3
auto[1] 128 1 T4 1 T25 1 T43 2



Summary for Variable cp_key2_out_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key2_out_sel

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 120 1 T4 2 T25 1 T26 2
auto[1] 122 1 T4 1 T25 2 T26 1



Summary for Variable cp_key2_out_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key2_out_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 112 1 T4 2 T25 3 T26 2
auto[1] 130 1 T4 1 T26 1 T44 2



Summary for Cross cross_key0_out_sel_value

Samples crossed: cp_key0_out_value cp_key0_out_sel
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cross_key0_out_sel_value

Bins
cp_key0_out_valuecp_key0_out_selCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 57 1 T4 2 T43 2 T45 1
auto[0] auto[1] 57 1 T26 2 T45 1 T36 1
auto[1] auto[0] 56 1 T25 1 T26 1 T44 2
auto[1] auto[1] 72 1 T4 1 T25 2 T43 1



Summary for Cross cross_key1_out_sel_value

Samples crossed: cp_key1_out_value cp_key1_out_sel
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cross_key1_out_sel_value

Bins
cp_key1_out_valuecp_key1_out_selCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 57 1 T4 1 T25 1 T26 1
auto[0] auto[1] 57 1 T4 1 T25 1 T26 2
auto[1] auto[0] 69 1 T44 2 T45 1 T32 2
auto[1] auto[1] 59 1 T4 1 T25 1 T43 2



Summary for Cross cross_key2_out_sel_value

Samples crossed: cp_key2_out_value cp_key2_out_sel
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cross_key2_out_sel_value

Bins
cp_key2_out_valuecp_key2_out_selCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 56 1 T4 1 T25 1 T26 1
auto[0] auto[1] 56 1 T4 1 T25 2 T26 1
auto[1] auto[0] 64 1 T4 1 T26 1 T44 1
auto[1] auto[1] 66 1 T44 1 T45 2 T36 1


Summary for Variable cp_key0_out_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key0_out_sel

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 21 1 T55 3 T86 2 T90 2
auto[1] 17 1 T86 1 T90 1 T94 2



Summary for Variable cp_key0_out_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key0_out_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 20 1 T55 1 T86 2 T90 2
auto[1] 18 1 T55 2 T86 1 T90 1



Summary for Variable cp_key1_out_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key1_out_sel

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 14 1 T55 2 T86 1 T94 1
auto[1] 24 1 T55 1 T86 2 T90 3



Summary for Variable cp_key1_out_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key1_out_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 18 1 T55 2 T86 1 T90 1
auto[1] 20 1 T55 1 T86 2 T90 2



Summary for Variable cp_key2_out_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key2_out_sel

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 17 1 T55 2 T90 3 T94 1
auto[1] 21 1 T55 1 T86 3 T94 2



Summary for Variable cp_key2_out_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key2_out_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 20 1 T86 2 T90 1 T94 2
auto[1] 18 1 T55 3 T86 1 T90 2



Summary for Cross cross_key0_out_sel_value

Samples crossed: cp_key0_out_value cp_key0_out_sel
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cross_key0_out_sel_value

Bins
cp_key0_out_valuecp_key0_out_selCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 12 1 T55 1 T86 1 T90 1
auto[0] auto[1] 8 1 T86 1 T90 1 T94 2
auto[1] auto[0] 9 1 T55 2 T86 1 T90 1
auto[1] auto[1] 9 1 T381 2 T382 1 T103 1



Summary for Cross cross_key1_out_sel_value

Samples crossed: cp_key1_out_value cp_key1_out_sel
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cross_key1_out_sel_value

Bins
cp_key1_out_valuecp_key1_out_selCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 8 1 T55 2 T86 1 T94 1
auto[0] auto[1] 10 1 T90 1 T94 2 T192 1
auto[1] auto[0] 6 1 T382 1 T235 1 T258 1
auto[1] auto[1] 14 1 T55 1 T86 2 T90 2



Summary for Cross cross_key2_out_sel_value

Samples crossed: cp_key2_out_value cp_key2_out_sel
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cross_key2_out_sel_value

Bins
cp_key2_out_valuecp_key2_out_selCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 11 1 T90 1 T94 1 T192 1
auto[0] auto[1] 9 1 T86 2 T94 1 T272 1
auto[1] auto[0] 6 1 T55 2 T90 2 T192 1
auto[1] auto[1] 12 1 T55 1 T86 1 T94 1


Summary for Variable cp_key0_out_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key0_out_sel

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 10 1 T78 1 T86 1 T90 3
auto[1] 12 1 T78 2 T86 2 T94 1



Summary for Variable cp_key0_out_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key0_out_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 11 1 T78 2 T86 1 T90 1
auto[1] 11 1 T78 1 T86 2 T90 2



Summary for Variable cp_key1_out_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key1_out_sel

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 12 1 T78 2 T90 1 T94 2
auto[1] 10 1 T78 1 T86 3 T90 2



Summary for Variable cp_key1_out_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key1_out_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 11 1 T78 1 T86 3 T192 1
auto[1] 11 1 T78 2 T90 3 T94 3



Summary for Variable cp_key2_out_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key2_out_sel

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 10 1 T78 1 T86 1 T90 1
auto[1] 12 1 T78 2 T86 2 T90 2



Summary for Variable cp_key2_out_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key2_out_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 10 1 T78 3 T86 1 T90 2
auto[1] 12 1 T86 2 T90 1 T94 2



Summary for Cross cross_key0_out_sel_value

Samples crossed: cp_key0_out_value cp_key0_out_sel
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cross_key0_out_sel_value

Bins
cp_key0_out_valuecp_key0_out_selCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 4 1 T90 1 T211 1 T381 1
auto[0] auto[1] 7 1 T78 2 T86 1 T192 2
auto[1] auto[0] 6 1 T78 1 T86 1 T90 2
auto[1] auto[1] 5 1 T86 1 T94 1 T192 1



Summary for Cross cross_key1_out_sel_value

Samples crossed: cp_key1_out_value cp_key1_out_sel
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cross_key1_out_sel_value

Bins
cp_key1_out_valuecp_key1_out_selCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 5 1 T192 1 T211 1 T381 1
auto[0] auto[1] 6 1 T78 1 T86 3 T381 1
auto[1] auto[0] 7 1 T78 2 T90 1 T94 2
auto[1] auto[1] 4 1 T90 2 T94 1 T192 1



Summary for Cross cross_key2_out_sel_value

Samples crossed: cp_key2_out_value cp_key2_out_sel
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cross_key2_out_sel_value

Bins
cp_key2_out_valuecp_key2_out_selCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 4 1 T78 1 T90 1 T94 1
auto[0] auto[1] 6 1 T78 2 T86 1 T90 1
auto[1] auto[0] 6 1 T86 1 T192 1 T211 1
auto[1] auto[1] 6 1 T86 1 T90 1 T94 2

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