Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_intr_status_obj::sysrst_ctrl_combo_intr_status_cg
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Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_intr_status_obj::sysrst_ctrl_combo_intr_status_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
37.38 37.38 1 100 1 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
sysrst_ctrl_combo_intr_status_cg 37.38 1 100 1 64 64




Group Instance : sysrst_ctrl_combo_intr_status_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
37.38 1 100 1 64 64




Summary for Group Instance sysrst_ctrl_combo_intr_status_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 20 0 20 100.00
Crosses 384 253 131 34.11


Variables for Group Instance sysrst_ctrl_combo_intr_status_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_ac_present_sel 2 0 2 100.00 100 1 1 2
cp_combo0_h2l 2 0 2 100.00 100 1 1 2
cp_combo1_h2l 2 0 2 100.00 100 1 1 2
cp_combo2_h2l 2 0 2 100.00 100 1 1 2
cp_combo3_h2l 2 0 2 100.00 100 1 1 2
cp_interrupt 2 0 2 100.00 100 1 1 2
cp_key0_in_sel 2 0 2 100.00 100 1 1 2
cp_key1_in_sel 2 0 2 100.00 100 1 1 2
cp_key2_in_sel 2 0 2 100.00 100 1 1 2
cp_pwrb_in_sel 2 0 2 100.00 100 1 1 2


Crosses for Group Instance sysrst_ctrl_combo_intr_status_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cross_combo0 96 64 32 33.33 100 1 1 0
cross_combo1 96 63 33 34.38 100 1 1 0
cross_combo2 96 63 33 34.38 100 1 1 0
cross_combo3 96 63 33 34.38 100 1 1 0


Summary for Variable cp_ac_present_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_ac_present_sel

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 79 1 T13 2 T20 1 T14 2
auto[1] 119 1 T13 2 T20 1 T24 2



Summary for Variable cp_combo0_h2l

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_combo0_h2l

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 174 1 T13 1 T20 2 T24 2
auto[1] 24 1 T13 3 T30 2 T59 1



Summary for Variable cp_combo1_h2l

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_combo1_h2l

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 190 1 T13 3 T20 2 T24 2
auto[1] 8 1 T13 1 T123 1 T80 2



Summary for Variable cp_combo2_h2l

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_combo2_h2l

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 174 1 T13 4 T20 2 T24 2
auto[1] 24 1 T14 2 T15 2 T31 2



Summary for Variable cp_combo3_h2l

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_combo3_h2l

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 184 1 T13 1 T20 2 T24 2
auto[1] 14 1 T13 3 T29 2 T30 2



Summary for Variable cp_interrupt

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_interrupt

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 183 1 T13 2 T20 2 T24 2
auto[1] 15 1 T13 2 T30 1 T59 1



Summary for Variable cp_key0_in_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key0_in_sel

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 82 1 T13 2 T14 1 T25 1
auto[1] 116 1 T13 2 T20 2 T24 2



Summary for Variable cp_key1_in_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key1_in_sel

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 78 1 T13 2 T14 1 T25 1
auto[1] 120 1 T13 2 T20 2 T24 2



Summary for Variable cp_key2_in_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key2_in_sel

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 76 1 T13 1 T20 2 T24 1
auto[1] 122 1 T13 3 T24 1 T14 1



Summary for Variable cp_pwrb_in_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_pwrb_in_sel

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 77 1 T13 2 T20 1 T14 1
auto[1] 121 1 T13 2 T20 1 T24 2



Summary for Cross cross_combo0

Samples crossed: cp_combo0_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 96 64 32 33.33 64
Automatically Generated Cross Bins 96 64 32 33.33 64
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cross_combo0

Element holes
cp_combo0_h2lcp_key0_in_selcp_key1_in_selcp_key2_in_selcp_pwrb_in_selcp_ac_present_selcp_interruptCOUNTAT LEASTNUMBERSTATUS
[auto[0]] [auto[0]] * * * * [auto[1]] -- -- 16
[auto[0]] [auto[1]] [auto[0]] [auto[0]] * * [auto[1]] -- -- 4
[auto[0]] [auto[1]] [auto[0]] [auto[1]] [auto[0]] [auto[1]] * -- -- 2
[auto[0]] [auto[1]] [auto[0]] [auto[1]] [auto[1]] * [auto[1]] -- -- 2
[auto[0]] [auto[1]] [auto[1]] * * * [auto[1]] -- -- 8
[auto[1]] [auto[0]] * * * * [auto[1]] -- -- 16
[auto[1]] [auto[1]] [auto[0]] * * * [auto[1]] -- -- 8
[auto[1]] [auto[1]] [auto[1]] [auto[0]] * * [auto[1]] -- -- 4
[auto[1]] [auto[1]] [auto[1]] [auto[1]] [auto[0]] * [auto[1]] -- -- 2


Uncovered bins
cp_combo0_h2lcp_key0_in_selcp_key1_in_selcp_key2_in_selcp_pwrb_in_selcp_ac_present_selcp_interruptCOUNTAT LEASTNUMBERSTATUS
[auto[0]] [auto[1]] [auto[0]] [auto[1]] [auto[0]] [auto[0]] [auto[1]] 0 1 1
[auto[1]] [auto[1]] [auto[1]] [auto[1]] [auto[1]] [auto[0]] [auto[1]] 0 1 1


Covered bins
cp_combo0_h2lcp_key0_in_selcp_key1_in_selcp_key2_in_selcp_pwrb_in_selcp_ac_present_selcp_interruptCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] auto[0] auto[0] 4 1 T77 1 T82 1 T83 1
auto[0] auto[0] auto[0] auto[0] auto[0] auto[1] auto[0] 3 1 T81 1 T92 1 T179 1
auto[0] auto[0] auto[0] auto[0] auto[1] auto[0] auto[0] 3 1 T15 1 T180 1 T181 1
auto[0] auto[0] auto[0] auto[0] auto[1] auto[1] auto[0] 5 1 T76 1 T61 1 T142 1
auto[0] auto[0] auto[0] auto[1] auto[0] auto[0] auto[0] 7 1 T13 1 T59 1 T78 1
auto[0] auto[0] auto[0] auto[1] auto[0] auto[1] auto[0] 8 1 T67 1 T61 1 T182 1
auto[0] auto[0] auto[0] auto[1] auto[1] auto[0] auto[0] 5 1 T25 1 T136 1 T78 1
auto[0] auto[0] auto[0] auto[1] auto[1] auto[1] auto[0] 7 1 T59 1 T64 1 T88 1
auto[0] auto[0] auto[1] auto[0] auto[0] auto[0] auto[0] 1 1 T80 1 - - - -
auto[0] auto[0] auto[1] auto[0] auto[0] auto[1] auto[0] 1 1 T183 1 - - - -
auto[0] auto[0] auto[1] auto[0] auto[1] auto[0] auto[0] 7 1 T14 1 T124 1 T91 1
auto[0] auto[0] auto[1] auto[0] auto[1] auto[1] auto[0] 6 1 T56 1 T60 1 T97 1
auto[0] auto[0] auto[1] auto[1] auto[0] auto[0] auto[0] 6 1 T30 1 T64 1 T121 1
auto[0] auto[0] auto[1] auto[1] auto[0] auto[1] auto[0] 6 1 T184 1 T136 1 T125 1
auto[0] auto[0] auto[1] auto[1] auto[1] auto[0] auto[0] 4 1 T64 2 T185 1 T186 1
auto[0] auto[0] auto[1] auto[1] auto[1] auto[1] auto[0] 7 1 T29 1 T31 1 T121 1
auto[0] auto[1] auto[0] auto[0] auto[0] auto[0] auto[0] 7 1 T14 1 T29 1 T67 1
auto[0] auto[1] auto[0] auto[0] auto[0] auto[1] auto[0] 8 1 T31 1 T60 1 T61 1
auto[0] auto[1] auto[0] auto[0] auto[1] auto[0] auto[0] 3 1 T126 1 T91 1 T179 1
auto[0] auto[1] auto[0] auto[0] auto[1] auto[1] auto[0] 1 1 T187 1 - - - -
auto[0] auto[1] auto[0] auto[1] auto[0] auto[0] auto[0] 6 1 T15 1 T88 1 T188 1
auto[0] auto[1] auto[0] auto[1] auto[1] auto[0] auto[0] 4 1 T189 1 T183 1 T190 1
auto[0] auto[1] auto[0] auto[1] auto[1] auto[1] auto[0] 4 1 T61 1 T191 1 T192 1
auto[0] auto[1] auto[1] auto[0] auto[0] auto[0] auto[0] 4 1 T123 1 T91 1 T85 1
auto[0] auto[1] auto[1] auto[0] auto[0] auto[1] auto[0] 5 1 T20 1 T56 1 T76 1
auto[0] auto[1] auto[1] auto[0] auto[1] auto[0] auto[0] 5 1 T20 1 T125 1 T193 1
auto[0] auto[1] auto[1] auto[0] auto[1] auto[1] auto[0] 7 1 T24 1 T64 1 T122 2
auto[0] auto[1] auto[1] auto[1] auto[0] auto[0] auto[0] 2 1 T193 1 T181 1 - -
auto[0] auto[1] auto[1] auto[1] auto[0] auto[1] auto[0] 3 1 T194 1 T190 1 T195 1
auto[0] auto[1] auto[1] auto[1] auto[1] auto[0] auto[0] 5 1 T25 1 T184 1 T56 1
auto[0] auto[1] auto[1] auto[1] auto[1] auto[1] auto[0] 30 1 T24 1 T14 1 T15 1
auto[1] auto[1] auto[1] auto[1] auto[1] auto[1] auto[1] 15 1 T13 2 T30 1 T59 1


User Defined Cross Bins for cross_combo0

Excluded/Illegal bins
NAMECOUNTSTATUS
invalid0 0 Excluded



Summary for Cross cross_combo1

Samples crossed: cp_combo1_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 96 63 33 34.38 63
Automatically Generated Cross Bins 96 63 33 34.38 63
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cross_combo1

Element holes
cp_combo1_h2lcp_key0_in_selcp_key1_in_selcp_key2_in_selcp_pwrb_in_selcp_ac_present_selcp_interruptCOUNTAT LEASTNUMBERSTATUS
[auto[0]] [auto[0]] * * * * [auto[1]] -- -- 16
[auto[0]] [auto[1]] [auto[0]] [auto[0]] * * [auto[1]] -- -- 4
[auto[0]] [auto[1]] [auto[0]] [auto[1]] [auto[0]] [auto[1]] * -- -- 2
[auto[0]] [auto[1]] [auto[0]] [auto[1]] [auto[1]] * [auto[1]] -- -- 2
[auto[0]] [auto[1]] [auto[1]] [auto[0]] * * [auto[1]] -- -- 4
[auto[0]] [auto[1]] [auto[1]] [auto[1]] [auto[0]] * [auto[1]] -- -- 2
[auto[1]] [auto[0]] * * * * [auto[1]] -- -- 16
[auto[1]] [auto[1]] [auto[0]] * * * [auto[1]] -- -- 8
[auto[1]] [auto[1]] [auto[1]] [auto[0]] * * [auto[1]] -- -- 4
[auto[1]] [auto[1]] [auto[1]] [auto[1]] [auto[0]] * [auto[1]] -- -- 2


Uncovered bins
cp_combo1_h2lcp_key0_in_selcp_key1_in_selcp_key2_in_selcp_pwrb_in_selcp_ac_present_selcp_interruptCOUNTAT LEASTNUMBERSTATUS
[auto[0]] [auto[1]] [auto[0]] [auto[1]] [auto[0]] [auto[0]] [auto[1]] 0 1 1
[auto[0]] [auto[1]] [auto[1]] [auto[1]] [auto[1]] [auto[0]] [auto[1]] 0 1 1
[auto[1]] [auto[1]] [auto[1]] [auto[1]] [auto[1]] [auto[0]] [auto[1]] 0 1 1


Covered bins
cp_combo1_h2lcp_key0_in_selcp_key1_in_selcp_key2_in_selcp_pwrb_in_selcp_ac_present_selcp_interruptCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] auto[0] auto[0] 5 1 T13 1 T77 1 T82 1
auto[0] auto[0] auto[0] auto[0] auto[0] auto[1] auto[0] 3 1 T81 1 T92 1 T179 1
auto[0] auto[0] auto[0] auto[0] auto[1] auto[0] auto[0] 3 1 T15 1 T180 1 T181 1
auto[0] auto[0] auto[0] auto[0] auto[1] auto[1] auto[0] 5 1 T76 1 T61 1 T142 1
auto[0] auto[0] auto[0] auto[1] auto[0] auto[0] auto[0] 7 1 T13 1 T59 1 T78 1
auto[0] auto[0] auto[0] auto[1] auto[0] auto[1] auto[0] 8 1 T67 1 T61 1 T182 1
auto[0] auto[0] auto[0] auto[1] auto[1] auto[0] auto[0] 5 1 T25 1 T136 1 T78 1
auto[0] auto[0] auto[0] auto[1] auto[1] auto[1] auto[0] 7 1 T59 1 T64 1 T88 1
auto[0] auto[0] auto[1] auto[0] auto[0] auto[0] auto[0] 1 1 T80 1 - - - -
auto[0] auto[0] auto[1] auto[0] auto[0] auto[1] auto[0] 1 1 T183 1 - - - -
auto[0] auto[0] auto[1] auto[0] auto[1] auto[0] auto[0] 7 1 T14 1 T124 1 T91 1
auto[0] auto[0] auto[1] auto[0] auto[1] auto[1] auto[0] 6 1 T56 1 T60 1 T97 1
auto[0] auto[0] auto[1] auto[1] auto[0] auto[0] auto[0] 7 1 T30 1 T64 1 T121 1
auto[0] auto[0] auto[1] auto[1] auto[0] auto[1] auto[0] 6 1 T184 1 T136 1 T125 1
auto[0] auto[0] auto[1] auto[1] auto[1] auto[0] auto[0] 4 1 T64 2 T185 1 T186 1
auto[0] auto[0] auto[1] auto[1] auto[1] auto[1] auto[0] 7 1 T29 1 T31 1 T121 1
auto[0] auto[1] auto[0] auto[0] auto[0] auto[0] auto[0] 7 1 T14 1 T29 1 T67 1
auto[0] auto[1] auto[0] auto[0] auto[0] auto[1] auto[0] 8 1 T31 1 T60 1 T61 1
auto[0] auto[1] auto[0] auto[0] auto[1] auto[0] auto[0] 3 1 T126 1 T91 1 T179 1
auto[0] auto[1] auto[0] auto[0] auto[1] auto[1] auto[0] 2 1 T30 1 T187 1 - -
auto[0] auto[1] auto[0] auto[1] auto[0] auto[0] auto[0] 7 1 T15 1 T88 1 T89 1
auto[0] auto[1] auto[0] auto[1] auto[1] auto[0] auto[0] 4 1 T189 1 T183 1 T190 1
auto[0] auto[1] auto[0] auto[1] auto[1] auto[1] auto[0] 4 1 T61 1 T191 1 T192 1
auto[0] auto[1] auto[1] auto[0] auto[0] auto[0] auto[0] 4 1 T123 1 T91 1 T85 1
auto[0] auto[1] auto[1] auto[0] auto[0] auto[1] auto[0] 6 1 T20 1 T56 1 T76 1
auto[0] auto[1] auto[1] auto[0] auto[1] auto[0] auto[0] 6 1 T20 1 T125 1 T193 1
auto[0] auto[1] auto[1] auto[0] auto[1] auto[1] auto[0] 8 1 T24 1 T64 1 T122 2
auto[0] auto[1] auto[1] auto[1] auto[0] auto[0] auto[0] 3 1 T193 1 T141 1 T181 1
auto[0] auto[1] auto[1] auto[1] auto[0] auto[1] auto[0] 3 1 T194 1 T190 1 T195 1
auto[0] auto[1] auto[1] auto[1] auto[1] auto[0] auto[0] 5 1 T25 1 T184 1 T56 1
auto[0] auto[1] auto[1] auto[1] auto[1] auto[1] auto[0] 24 1 T24 1 T14 1 T15 1
auto[0] auto[1] auto[1] auto[1] auto[1] auto[1] auto[1] 14 1 T13 1 T30 1 T59 1
auto[1] auto[1] auto[1] auto[1] auto[1] auto[1] auto[1] 1 1 T13 1 - - - -


User Defined Cross Bins for cross_combo1

Excluded/Illegal bins
NAMECOUNTSTATUS
invalid0 0 Excluded



Summary for Cross cross_combo2

Samples crossed: cp_combo2_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 96 63 33 34.38 63
Automatically Generated Cross Bins 96 63 33 34.38 63
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cross_combo2

Element holes
cp_combo2_h2lcp_key0_in_selcp_key1_in_selcp_key2_in_selcp_pwrb_in_selcp_ac_present_selcp_interruptCOUNTAT LEASTNUMBERSTATUS
[auto[0]] [auto[0]] * * * * [auto[1]] -- -- 16
[auto[0]] [auto[1]] [auto[0]] [auto[0]] * * [auto[1]] -- -- 4
[auto[0]] [auto[1]] [auto[0]] [auto[1]] [auto[0]] [auto[1]] * -- -- 2
[auto[0]] [auto[1]] [auto[0]] [auto[1]] [auto[1]] * [auto[1]] -- -- 2
[auto[0]] [auto[1]] [auto[1]] [auto[0]] * * [auto[1]] -- -- 4
[auto[0]] [auto[1]] [auto[1]] [auto[1]] [auto[0]] * [auto[1]] -- -- 2
[auto[1]] [auto[0]] * * * * [auto[1]] -- -- 16
[auto[1]] [auto[1]] [auto[0]] * * * [auto[1]] -- -- 8
[auto[1]] [auto[1]] [auto[1]] [auto[0]] * * [auto[1]] -- -- 4
[auto[1]] [auto[1]] [auto[1]] [auto[1]] [auto[0]] * [auto[1]] -- -- 2


Uncovered bins
cp_combo2_h2lcp_key0_in_selcp_key1_in_selcp_key2_in_selcp_pwrb_in_selcp_ac_present_selcp_interruptCOUNTAT LEASTNUMBERSTATUS
[auto[0]] [auto[1]] [auto[0]] [auto[1]] [auto[0]] [auto[0]] [auto[1]] 0 1 1
[auto[0]] [auto[1]] [auto[1]] [auto[1]] [auto[1]] [auto[0]] [auto[1]] 0 1 1
[auto[1]] [auto[1]] [auto[1]] [auto[1]] [auto[1]] [auto[0]] [auto[1]] 0 1 1


Covered bins
cp_combo2_h2lcp_key0_in_selcp_key1_in_selcp_key2_in_selcp_pwrb_in_selcp_ac_present_selcp_interruptCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] auto[0] auto[0] 5 1 T13 1 T77 1 T82 1
auto[0] auto[0] auto[0] auto[0] auto[0] auto[1] auto[0] 3 1 T81 1 T92 1 T179 1
auto[0] auto[0] auto[0] auto[0] auto[1] auto[0] auto[0] 3 1 T15 1 T180 1 T181 1
auto[0] auto[0] auto[0] auto[0] auto[1] auto[1] auto[0] 5 1 T76 1 T61 1 T142 1
auto[0] auto[0] auto[0] auto[1] auto[0] auto[0] auto[0] 7 1 T13 1 T59 1 T78 1
auto[0] auto[0] auto[0] auto[1] auto[0] auto[1] auto[0] 8 1 T67 1 T61 1 T182 1
auto[0] auto[0] auto[0] auto[1] auto[1] auto[0] auto[0] 5 1 T25 1 T136 1 T78 1
auto[0] auto[0] auto[0] auto[1] auto[1] auto[1] auto[0] 7 1 T59 1 T64 1 T88 1
auto[0] auto[0] auto[1] auto[0] auto[0] auto[0] auto[0] 1 1 T80 1 - - - -
auto[0] auto[0] auto[1] auto[0] auto[0] auto[1] auto[0] 1 1 T183 1 - - - -
auto[0] auto[0] auto[1] auto[0] auto[1] auto[0] auto[0] 7 1 T14 1 T124 1 T91 1
auto[0] auto[0] auto[1] auto[0] auto[1] auto[1] auto[0] 5 1 T56 1 T60 1 T187 1
auto[0] auto[0] auto[1] auto[1] auto[0] auto[0] auto[0] 7 1 T30 1 T64 1 T121 1
auto[0] auto[0] auto[1] auto[1] auto[0] auto[1] auto[0] 5 1 T184 1 T136 1 T125 1
auto[0] auto[0] auto[1] auto[1] auto[1] auto[0] auto[0] 4 1 T64 2 T185 1 T186 1
auto[0] auto[0] auto[1] auto[1] auto[1] auto[1] auto[0] 6 1 T29 1 T121 1 T196 1
auto[0] auto[1] auto[0] auto[0] auto[0] auto[0] auto[0] 6 1 T29 1 T67 1 T79 1
auto[0] auto[1] auto[0] auto[0] auto[0] auto[1] auto[0] 7 1 T31 1 T60 1 T77 1
auto[0] auto[1] auto[0] auto[0] auto[1] auto[0] auto[0] 3 1 T126 1 T91 1 T179 1
auto[0] auto[1] auto[0] auto[0] auto[1] auto[1] auto[0] 2 1 T30 1 T187 1 - -
auto[0] auto[1] auto[0] auto[1] auto[0] auto[0] auto[0] 5 1 T88 1 T89 1 T188 1
auto[0] auto[1] auto[0] auto[1] auto[1] auto[0] auto[0] 4 1 T189 1 T183 1 T190 1
auto[0] auto[1] auto[0] auto[1] auto[1] auto[1] auto[0] 4 1 T61 1 T191 1 T192 1
auto[0] auto[1] auto[1] auto[0] auto[0] auto[0] auto[0] 5 1 T123 1 T91 1 T85 1
auto[0] auto[1] auto[1] auto[0] auto[0] auto[1] auto[0] 6 1 T20 1 T56 1 T76 1
auto[0] auto[1] auto[1] auto[0] auto[1] auto[0] auto[0] 6 1 T20 1 T125 1 T193 1
auto[0] auto[1] auto[1] auto[0] auto[1] auto[1] auto[0] 7 1 T24 1 T64 1 T122 2
auto[0] auto[1] auto[1] auto[1] auto[0] auto[0] auto[0] 3 1 T193 1 T141 1 T181 1
auto[0] auto[1] auto[1] auto[1] auto[0] auto[1] auto[0] 3 1 T194 1 T190 1 T195 1
auto[0] auto[1] auto[1] auto[1] auto[1] auto[0] auto[0] 5 1 T25 1 T184 1 T56 1
auto[0] auto[1] auto[1] auto[1] auto[1] auto[1] auto[0] 15 1 T24 1 T29 1 T56 1
auto[0] auto[1] auto[1] auto[1] auto[1] auto[1] auto[1] 14 1 T13 2 T30 1 T59 1
auto[1] auto[1] auto[1] auto[1] auto[1] auto[1] auto[1] 1 1 T197 1 - - - -


User Defined Cross Bins for cross_combo2

Excluded/Illegal bins
NAMECOUNTSTATUS
invalid0 0 Excluded



Summary for Cross cross_combo3

Samples crossed: cp_combo3_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 96 63 33 34.38 63
Automatically Generated Cross Bins 96 63 33 34.38 63
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cross_combo3

Element holes
cp_combo3_h2lcp_key0_in_selcp_key1_in_selcp_key2_in_selcp_pwrb_in_selcp_ac_present_selcp_interruptCOUNTAT LEASTNUMBERSTATUS
[auto[0]] [auto[0]] * * * * [auto[1]] -- -- 16
[auto[0]] [auto[1]] [auto[0]] [auto[0]] * * [auto[1]] -- -- 4
[auto[0]] [auto[1]] [auto[0]] [auto[1]] [auto[0]] [auto[1]] * -- -- 2
[auto[0]] [auto[1]] [auto[0]] [auto[1]] [auto[1]] * [auto[1]] -- -- 2
[auto[0]] [auto[1]] [auto[1]] [auto[0]] * * [auto[1]] -- -- 4
[auto[0]] [auto[1]] [auto[1]] [auto[1]] [auto[0]] * [auto[1]] -- -- 2
[auto[1]] [auto[0]] * * * * [auto[1]] -- -- 16
[auto[1]] [auto[1]] [auto[0]] * * * [auto[1]] -- -- 8
[auto[1]] [auto[1]] [auto[1]] [auto[0]] * * [auto[1]] -- -- 4
[auto[1]] [auto[1]] [auto[1]] [auto[1]] [auto[0]] * [auto[1]] -- -- 2


Uncovered bins
cp_combo3_h2lcp_key0_in_selcp_key1_in_selcp_key2_in_selcp_pwrb_in_selcp_ac_present_selcp_interruptCOUNTAT LEASTNUMBERSTATUS
[auto[0]] [auto[1]] [auto[0]] [auto[1]] [auto[0]] [auto[0]] [auto[1]] 0 1 1
[auto[0]] [auto[1]] [auto[1]] [auto[1]] [auto[1]] [auto[0]] [auto[1]] 0 1 1
[auto[1]] [auto[1]] [auto[1]] [auto[1]] [auto[1]] [auto[0]] [auto[1]] 0 1 1


Covered bins
cp_combo3_h2lcp_key0_in_selcp_key1_in_selcp_key2_in_selcp_pwrb_in_selcp_ac_present_selcp_interruptCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] auto[0] auto[0] 4 1 T77 1 T82 1 T83 1
auto[0] auto[0] auto[0] auto[0] auto[0] auto[1] auto[0] 3 1 T81 1 T92 1 T179 1
auto[0] auto[0] auto[0] auto[0] auto[1] auto[0] auto[0] 3 1 T15 1 T180 1 T181 1
auto[0] auto[0] auto[0] auto[0] auto[1] auto[1] auto[0] 5 1 T76 1 T61 1 T142 1
auto[0] auto[0] auto[0] auto[1] auto[0] auto[0] auto[0] 7 1 T13 1 T59 1 T78 1
auto[0] auto[0] auto[0] auto[1] auto[0] auto[1] auto[0] 8 1 T67 1 T61 1 T182 1
auto[0] auto[0] auto[0] auto[1] auto[1] auto[0] auto[0] 5 1 T25 1 T136 1 T78 1
auto[0] auto[0] auto[0] auto[1] auto[1] auto[1] auto[0] 7 1 T59 1 T64 1 T88 1
auto[0] auto[0] auto[1] auto[0] auto[0] auto[0] auto[0] 1 1 T80 1 - - - -
auto[0] auto[0] auto[1] auto[0] auto[0] auto[1] auto[0] 1 1 T183 1 - - - -
auto[0] auto[0] auto[1] auto[0] auto[1] auto[0] auto[0] 7 1 T14 1 T124 1 T91 1
auto[0] auto[0] auto[1] auto[0] auto[1] auto[1] auto[0] 5 1 T56 1 T97 1 T187 1
auto[0] auto[0] auto[1] auto[1] auto[0] auto[0] auto[0] 7 1 T30 1 T64 1 T121 1
auto[0] auto[0] auto[1] auto[1] auto[0] auto[1] auto[0] 6 1 T184 1 T136 1 T125 1
auto[0] auto[0] auto[1] auto[1] auto[1] auto[0] auto[0] 4 1 T64 2 T185 1 T186 1
auto[0] auto[0] auto[1] auto[1] auto[1] auto[1] auto[0] 6 1 T31 1 T121 1 T196 1
auto[0] auto[1] auto[0] auto[0] auto[0] auto[0] auto[0] 7 1 T14 1 T29 1 T67 1
auto[0] auto[1] auto[0] auto[0] auto[0] auto[1] auto[0] 8 1 T31 1 T60 1 T61 1
auto[0] auto[1] auto[0] auto[0] auto[1] auto[0] auto[0] 3 1 T126 1 T91 1 T179 1
auto[0] auto[1] auto[0] auto[0] auto[1] auto[1] auto[0] 1 1 T187 1 - - - -
auto[0] auto[1] auto[0] auto[1] auto[0] auto[0] auto[0] 7 1 T15 1 T88 1 T89 1
auto[0] auto[1] auto[0] auto[1] auto[1] auto[0] auto[0] 4 1 T189 1 T183 1 T190 1
auto[0] auto[1] auto[0] auto[1] auto[1] auto[1] auto[0] 4 1 T61 1 T191 1 T192 1
auto[0] auto[1] auto[1] auto[0] auto[0] auto[0] auto[0] 5 1 T123 1 T91 1 T85 1
auto[0] auto[1] auto[1] auto[0] auto[0] auto[1] auto[0] 6 1 T20 1 T56 1 T76 1
auto[0] auto[1] auto[1] auto[0] auto[1] auto[0] auto[0] 6 1 T20 1 T125 1 T193 1
auto[0] auto[1] auto[1] auto[0] auto[1] auto[1] auto[0] 7 1 T24 1 T64 1 T122 2
auto[0] auto[1] auto[1] auto[1] auto[0] auto[0] auto[0] 3 1 T193 1 T141 1 T181 1
auto[0] auto[1] auto[1] auto[1] auto[0] auto[1] auto[0] 3 1 T194 1 T190 1 T195 1
auto[0] auto[1] auto[1] auto[1] auto[1] auto[0] auto[0] 5 1 T25 1 T184 1 T56 1
auto[0] auto[1] auto[1] auto[1] auto[1] auto[1] auto[0] 25 1 T24 1 T14 1 T15 1
auto[0] auto[1] auto[1] auto[1] auto[1] auto[1] auto[1] 11 1 T59 1 T88 1 T89 2
auto[1] auto[1] auto[1] auto[1] auto[1] auto[1] auto[1] 4 1 T13 2 T30 1 T197 1


User Defined Cross Bins for cross_combo3

Excluded/Illegal bins
NAMECOUNTSTATUS
invalid0 0 Excluded

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