Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_detect_action_obj::sysrst_ctrl_combo_detect_action_cg
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Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_detect_action_obj::sysrst_ctrl_combo_detect_action_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

4 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
sysrst_ctrl_combo_detect_action_cg_0 100.00 1 100 1 64 64
sysrst_ctrl_combo_detect_action_cg_1 100.00 1 100 1 64 64
sysrst_ctrl_combo_detect_action_cg_2 100.00 1 100 1 64 64
sysrst_ctrl_combo_detect_action_cg_3 100.00 1 100 1 64 64



Group Instance : sysrst_ctrl_combo_detect_action_cg_0
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance sysrst_ctrl_combo_detect_action_cg_0

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 28 0 28 100.00


Variables for Group Instance sysrst_ctrl_combo_detect_action_cg_0
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_ac_present_sel 2 0 2 100.00 100 1 1 2
cp_bat_disable 2 0 2 100.00 100 1 1 2
cp_ec_rst 2 0 2 100.00 100 1 1 2
cp_interrupt 2 0 2 100.00 100 1 1 2
cp_key0_in_sel 2 0 2 100.00 100 1 1 2
cp_key1_in_sel 2 0 2 100.00 100 1 1 2
cp_key2_in_sel 2 0 2 100.00 100 1 1 2
cp_precondition_ac_present_sel 2 0 2 100.00 100 1 1 2
cp_precondition_key0_in_sel 2 0 2 100.00 100 1 1 2
cp_precondition_key1_in_sel 2 0 2 100.00 100 1 1 2
cp_precondition_key2_in_sel 2 0 2 100.00 100 1 1 2
cp_precondition_pwrb_in_sel 2 0 2 100.00 100 1 1 2
cp_pwrb_in_sel 2 0 2 100.00 100 1 1 2
cp_rst_req 2 0 2 100.00 100 1 1 2


Group Instance : sysrst_ctrl_combo_detect_action_cg_1
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance sysrst_ctrl_combo_detect_action_cg_1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 28 0 28 100.00


Variables for Group Instance sysrst_ctrl_combo_detect_action_cg_1
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_ac_present_sel 2 0 2 100.00 100 1 1 2
cp_bat_disable 2 0 2 100.00 100 1 1 2
cp_ec_rst 2 0 2 100.00 100 1 1 2
cp_interrupt 2 0 2 100.00 100 1 1 2
cp_key0_in_sel 2 0 2 100.00 100 1 1 2
cp_key1_in_sel 2 0 2 100.00 100 1 1 2
cp_key2_in_sel 2 0 2 100.00 100 1 1 2
cp_precondition_ac_present_sel 2 0 2 100.00 100 1 1 2
cp_precondition_key0_in_sel 2 0 2 100.00 100 1 1 2
cp_precondition_key1_in_sel 2 0 2 100.00 100 1 1 2
cp_precondition_key2_in_sel 2 0 2 100.00 100 1 1 2
cp_precondition_pwrb_in_sel 2 0 2 100.00 100 1 1 2
cp_pwrb_in_sel 2 0 2 100.00 100 1 1 2
cp_rst_req 2 0 2 100.00 100 1 1 2


Group Instance : sysrst_ctrl_combo_detect_action_cg_2
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance sysrst_ctrl_combo_detect_action_cg_2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 28 0 28 100.00


Variables for Group Instance sysrst_ctrl_combo_detect_action_cg_2
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_ac_present_sel 2 0 2 100.00 100 1 1 2
cp_bat_disable 2 0 2 100.00 100 1 1 2
cp_ec_rst 2 0 2 100.00 100 1 1 2
cp_interrupt 2 0 2 100.00 100 1 1 2
cp_key0_in_sel 2 0 2 100.00 100 1 1 2
cp_key1_in_sel 2 0 2 100.00 100 1 1 2
cp_key2_in_sel 2 0 2 100.00 100 1 1 2
cp_precondition_ac_present_sel 2 0 2 100.00 100 1 1 2
cp_precondition_key0_in_sel 2 0 2 100.00 100 1 1 2
cp_precondition_key1_in_sel 2 0 2 100.00 100 1 1 2
cp_precondition_key2_in_sel 2 0 2 100.00 100 1 1 2
cp_precondition_pwrb_in_sel 2 0 2 100.00 100 1 1 2
cp_pwrb_in_sel 2 0 2 100.00 100 1 1 2
cp_rst_req 2 0 2 100.00 100 1 1 2


Group Instance : sysrst_ctrl_combo_detect_action_cg_3
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance sysrst_ctrl_combo_detect_action_cg_3

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 28 0 28 100.00


Variables for Group Instance sysrst_ctrl_combo_detect_action_cg_3
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_ac_present_sel 2 0 2 100.00 100 1 1 2
cp_bat_disable 2 0 2 100.00 100 1 1 2
cp_ec_rst 2 0 2 100.00 100 1 1 2
cp_interrupt 2 0 2 100.00 100 1 1 2
cp_key0_in_sel 2 0 2 100.00 100 1 1 2
cp_key1_in_sel 2 0 2 100.00 100 1 1 2
cp_key2_in_sel 2 0 2 100.00 100 1 1 2
cp_precondition_ac_present_sel 2 0 2 100.00 100 1 1 2
cp_precondition_key0_in_sel 2 0 2 100.00 100 1 1 2
cp_precondition_key1_in_sel 2 0 2 100.00 100 1 1 2
cp_precondition_key2_in_sel 2 0 2 100.00 100 1 1 2
cp_precondition_pwrb_in_sel 2 0 2 100.00 100 1 1 2
cp_pwrb_in_sel 2 0 2 100.00 100 1 1 2
cp_rst_req 2 0 2 100.00 100 1 1 2


Summary for Variable cp_ac_present_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_ac_present_sel

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 592 1 T11 11 T32 5 T30 1
auto[1] 123 1 T174 1 T43 3 T91 3


Summary for Variable cp_bat_disable

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_bat_disable

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 379 1 T32 5 T30 1 T40 5
auto[1] 336 1 T11 11 T40 4 T88 6


Summary for Variable cp_ec_rst

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_ec_rst

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 399 1 T11 11 T32 5 T40 6
auto[1] 316 1 T30 1 T40 3 T88 6


Summary for Variable cp_interrupt

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_interrupt

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 388 1 T32 5 T40 1 T88 1
auto[1] 327 1 T11 11 T30 1 T40 8


Summary for Variable cp_key0_in_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key0_in_sel

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 552 1 T11 11 T30 1 T40 9
auto[1] 163 1 T32 5 T174 1 T178 8


Summary for Variable cp_key1_in_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key1_in_sel

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 486 1 T11 11 T32 5 T30 1
auto[1] 229 1 T40 6 T174 1 T251 2


Summary for Variable cp_key2_in_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key2_in_sel

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 565 1 T11 11 T32 5 T30 1
auto[1] 150 1 T251 2 T91 3 T92 4


Summary for Variable cp_precondition_ac_present_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_precondition_ac_present_sel

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 640 1 T11 11 T32 5 T30 1
auto[1] 75 1 T124 4 T199 1 T327 1


Summary for Variable cp_precondition_key0_in_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_precondition_key0_in_sel

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 657 1 T11 11 T32 5 T30 1
auto[1] 58 1 T91 3 T199 1 T475 3


Summary for Variable cp_precondition_key1_in_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_precondition_key1_in_sel

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 665 1 T11 11 T32 5 T30 1
auto[1] 50 1 T91 3 T199 1 T350 8


Summary for Variable cp_precondition_key2_in_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_precondition_key2_in_sel

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 624 1 T11 11 T32 5 T30 1
auto[1] 91 1 T40 6 T199 1 T329 3


Summary for Variable cp_precondition_pwrb_in_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 661 1 T11 11 T32 5 T30 1
auto[1] 54 1 T92 4 T329 3 T350 8


Summary for Variable cp_pwrb_in_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_pwrb_in_sel

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 573 1 T11 11 T30 1 T40 3
auto[1] 142 1 T32 5 T40 6 T361 4


Summary for Variable cp_rst_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_rst_req

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 383 1 T11 11 T32 5 T40 3
auto[1] 332 1 T30 1 T40 6 T88 6


Summary for Variable cp_ac_present_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_ac_present_sel

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 625 1 T11 11 T30 1 T40 9
auto[1] 125 1 T6 8 T32 2 T121 6


Summary for Variable cp_bat_disable

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_bat_disable

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 393 1 T6 8 T30 1 T40 5
auto[1] 357 1 T11 11 T32 2 T40 4


Summary for Variable cp_ec_rst

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_ec_rst

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 419 1 T6 8 T11 11 T40 6
auto[1] 331 1 T32 2 T30 1 T40 3


Summary for Variable cp_interrupt

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_interrupt

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 414 1 T32 2 T40 1 T42 9
auto[1] 336 1 T6 8 T11 11 T30 1


Summary for Variable cp_key0_in_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key0_in_sel

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 573 1 T6 8 T11 11 T32 2
auto[1] 177 1 T41 4 T88 7 T251 2


Summary for Variable cp_key1_in_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key1_in_sel

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 536 1 T6 8 T11 11 T30 1
auto[1] 214 1 T32 2 T42 9 T121 6


Summary for Variable cp_key2_in_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key2_in_sel

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 587 1 T6 8 T11 11 T32 2
auto[1] 163 1 T40 4 T41 4 T88 7


Summary for Variable cp_precondition_ac_present_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_precondition_ac_present_sel

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 633 1 T6 8 T11 11 T32 2
auto[1] 117 1 T88 7 T91 2 T199 4


Summary for Variable cp_precondition_key0_in_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_precondition_key0_in_sel

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 681 1 T6 8 T11 11 T32 2
auto[1] 69 1 T40 4 T92 1 T124 1


Summary for Variable cp_precondition_key1_in_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_precondition_key1_in_sel

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 669 1 T6 8 T11 11 T32 2
auto[1] 81 1 T92 1 T329 1 T138 2


Summary for Variable cp_precondition_key2_in_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_precondition_key2_in_sel

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 696 1 T6 8 T11 11 T32 2
auto[1] 54 1 T91 2 T431 17 T430 1


Summary for Variable cp_precondition_pwrb_in_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 669 1 T6 8 T11 11 T32 2
auto[1] 81 1 T91 2 T351 1 T441 1


Summary for Variable cp_pwrb_in_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_pwrb_in_sel

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 603 1 T6 8 T11 11 T30 1
auto[1] 147 1 T32 2 T174 14 T178 8


Summary for Variable cp_rst_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_rst_req

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 408 1 T6 8 T11 11 T40 3
auto[1] 342 1 T32 2 T30 1 T40 6


Summary for Variable cp_ac_present_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_ac_present_sel

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 584 1 T11 11 T40 3 T41 6
auto[1] 156 1 T32 4 T30 1 T40 6


Summary for Variable cp_bat_disable

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_bat_disable

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 348 1 T30 1 T40 5 T88 1
auto[1] 392 1 T11 11 T32 4 T40 4


Summary for Variable cp_ec_rst

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_ec_rst

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 382 1 T11 11 T40 6 T42 3
auto[1] 358 1 T32 4 T30 1 T40 3


Summary for Variable cp_interrupt

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_interrupt

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 388 1 T40 1 T42 3 T41 6
auto[1] 352 1 T11 11 T32 4 T30 1


Summary for Variable cp_key0_in_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key0_in_sel

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 596 1 T11 11 T32 4 T30 1
auto[1] 144 1 T42 3 T88 2 T174 11


Summary for Variable cp_key1_in_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key1_in_sel

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 556 1 T11 11 T32 4 T30 1
auto[1] 184 1 T42 3 T41 6 T178 1


Summary for Variable cp_key2_in_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key2_in_sel

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 559 1 T40 3 T41 6 T88 7
auto[1] 181 1 T11 11 T32 4 T30 1


Summary for Variable cp_precondition_ac_present_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_precondition_ac_present_sel

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 662 1 T11 11 T32 4 T30 1
auto[1] 78 1 T134 6 T350 6 T431 10


Summary for Variable cp_precondition_key0_in_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_precondition_key0_in_sel

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 634 1 T32 4 T40 9 T42 3
auto[1] 106 1 T11 11 T30 1 T199 3


Summary for Variable cp_precondition_key1_in_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_precondition_key1_in_sel

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 657 1 T32 4 T30 1 T40 3
auto[1] 83 1 T11 11 T40 6 T411 13


Summary for Variable cp_precondition_key2_in_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_precondition_key2_in_sel

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 667 1 T11 11 T32 4 T30 1
auto[1] 73 1 T88 2 T92 7 T134 6


Summary for Variable cp_precondition_pwrb_in_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 702 1 T11 11 T32 4 T30 1
auto[1] 38 1 T88 2 T199 3 T350 6


Summary for Variable cp_pwrb_in_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_pwrb_in_sel

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 495 1 T32 4 T30 1 T40 9
auto[1] 245 1 T11 11 T42 3 T41 6


Summary for Variable cp_rst_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_rst_req

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 383 1 T11 11 T40 3 T88 1
auto[1] 357 1 T32 4 T30 1 T40 6


Summary for Variable cp_ac_present_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_ac_present_sel

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 575 1 T11 11 T32 5 T30 1
auto[1] 166 1 T42 3 T251 1 T43 4


Summary for Variable cp_bat_disable

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_bat_disable

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 343 1 T30 1 T40 5 T42 3
auto[1] 398 1 T11 11 T32 5 T40 4


Summary for Variable cp_ec_rst

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_ec_rst

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 391 1 T11 11 T40 6 T42 3
auto[1] 350 1 T32 5 T30 1 T40 3


Summary for Variable cp_interrupt

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_interrupt

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 425 1 T32 5 T40 1 T41 8
auto[1] 316 1 T11 11 T30 1 T40 8


Summary for Variable cp_key0_in_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key0_in_sel

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 584 1 T11 11 T30 1 T40 9
auto[1] 157 1 T32 5 T41 8 T174 7


Summary for Variable cp_key1_in_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key1_in_sel

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 588 1 T11 11 T30 1 T40 9
auto[1] 153 1 T32 5 T42 3 T345 3


Summary for Variable cp_key2_in_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key2_in_sel

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 605 1 T11 11 T32 5 T30 1
auto[1] 136 1 T42 3 T178 8 T251 1


Summary for Variable cp_precondition_ac_present_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_precondition_ac_present_sel

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 670 1 T11 11 T32 5 T30 1
auto[1] 71 1 T350 6 T431 5 T420 7


Summary for Variable cp_precondition_key0_in_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_precondition_key0_in_sel

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 681 1 T11 11 T32 5 T30 1
auto[1] 60 1 T44 4 T328 2 T199 4


Summary for Variable cp_precondition_key1_in_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_precondition_key1_in_sel

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 687 1 T11 11 T32 5 T30 1
auto[1] 54 1 T328 2 T199 4 T350 6


Summary for Variable cp_precondition_key2_in_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_precondition_key2_in_sel

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 644 1 T11 11 T32 5 T30 1
auto[1] 97 1 T92 7 T351 1 T431 5


Summary for Variable cp_precondition_pwrb_in_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 655 1 T11 11 T32 5 T30 1
auto[1] 86 1 T431 5 T122 5 T411 11


Summary for Variable cp_pwrb_in_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_pwrb_in_sel

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 626 1 T11 11 T32 5 T30 1
auto[1] 115 1 T42 3 T174 7 T251 1


Summary for Variable cp_rst_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_rst_req

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 383 1 T11 11 T32 5 T40 3
auto[1] 358 1 T30 1 T40 6 T42 3