Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.12	95.12	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	95.12	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.12	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	4	58	93.55

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	4	27	87.10	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1844

1

T3

43

T4

6

T7

25

auto[1]

563

1

T5

10

T3

9

T4

1

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1863

1

T5

10

T3

39

T4

3

auto[1]

544

1

T3

13

T4

4

T10

6

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1778

1

T5

10

T3

52

T4

6

auto[1]

629

1

T4

1

T7

12

T38

7

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1708

1

T5

10

T3

52

T4

1

auto[1]

699

1

T4

6

T7

7

T40

15

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2132

1

T5

10

T3

48

T4

7

auto[1]

275

1

T3

4

T7

5

T38

7

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2144

1

T5

10

T3

52

T4

7

auto[1]

263

1

T7

14

T253

7

T269

72

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2231

1

T5

10

T3

48

T4

7

auto[1]

176

1

T3

4

T37

3

T29

1

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2242

1

T5

10

T3

52

T4

7

auto[1]

165

1

T29

5

T117

8

T254

2

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2154

1

T5

10

T3

34

T4

7

auto[1]

253

1

T3

18

T38

7

T76

10

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1837

1

T5

10

T3

52

T4

4

auto[1]

570

1

T4

3

T7

5

T37

3

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	4	27	87.10	4
Automatically Generated Cross Bins	31	4	27	87.10	4
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	auto[0]	auto[0]	770	1			T5	10		T4	7		T40	15
auto[0]	auto[0]	auto[0]	auto[0]	auto[1]	85	1			T7	4		T39	1		T253	4
auto[0]	auto[0]	auto[0]	auto[1]	auto[0]	105	1			T3	18		T253	10		T356	4
auto[0]	auto[0]	auto[0]	auto[1]	auto[1]	27	1			T38	7		T254	1		T363	3
auto[0]	auto[0]	auto[1]	auto[0]	auto[0]	55	1			T29	4		T364	3		T365	3
auto[0]	auto[0]	auto[1]	auto[0]	auto[1]	12	1			T117	5		T357	1		T366	2
auto[0]	auto[0]	auto[1]	auto[1]	auto[0]	15	1			T254	2		T356	4		T367	7
auto[0]	auto[0]	auto[1]	auto[1]	auto[1]	4	1			T88	4		-	-		-	-
auto[0]	auto[1]	auto[0]	auto[0]	auto[0]	59	1			T37	3		T76	14		T270	17
auto[0]	auto[1]	auto[0]	auto[0]	auto[1]	42	1			T3	4		T76	11		T270	24
auto[0]	auto[1]	auto[0]	auto[1]	auto[0]	18	1			T76	10		T90	4		T368	4
auto[0]	auto[1]	auto[0]	auto[1]	auto[1]	7	1			T270	7		-	-		-	-
auto[0]	auto[1]	auto[1]	auto[0]	auto[0]	3	1			T29	1		T363	2		-	-
auto[0]	auto[1]	auto[1]	auto[0]	auto[1]	9	1			T117	3		T369	6		-	-
auto[0]	auto[1]	auto[1]	auto[1]	auto[0]	4	1			T88	3		T370	1		-	-
auto[1]	auto[0]	auto[0]	auto[0]	auto[0]	73	1			T7	8		T269	24		T371	12
auto[1]	auto[0]	auto[0]	auto[0]	auto[1]	55	1			T269	19		T311	9		T372	15
auto[1]	auto[0]	auto[0]	auto[1]	auto[0]	31	1			T253	4		T269	18		T369	2
auto[1]	auto[0]	auto[1]	auto[0]	auto[0]	20	1			T269	11		T373	1		T363	2
auto[1]	auto[0]	auto[1]	auto[0]	auto[1]	9	1			T372	8		T359	1		-	-
auto[1]	auto[0]	auto[1]	auto[1]	auto[0]	1	1			T369	1		-	-		-	-
auto[1]	auto[0]	auto[1]	auto[1]	auto[1]	2	1			T374	2		-	-		-	-
auto[1]	auto[1]	auto[0]	auto[0]	auto[0]	15	1			T357	2		T375	2		T376	1
auto[1]	auto[1]	auto[0]	auto[0]	auto[1]	1	1			T352	1		-	-		-	-
auto[1]	auto[1]	auto[0]	auto[1]	auto[0]	1	1			T377	1		-	-		-	-
auto[1]	auto[1]	auto[1]	auto[0]	auto[0]	3	1			T367	2		T89	1		-	-
auto[1]	auto[1]	auto[1]	auto[0]	auto[1]	1	1			T378	1		-	-		-	-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

88

1

T5

10

T3

9

T270

17

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

65

1

T37

3

T39

1

T76

14

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

43

1

T58

4

T124

5

T91

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

124

1

T4

3

T40

10

T76

10

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

48

1

T7

4

T40

5

T312

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

95

1

T76

11

T118

8

T264

6

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

24

1

T122

2

T118

4

T91

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

97

1

T7

4

T38

7

T234

9

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

89

1

T122

3

T80

5

T253

4

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

88

1

T7

4

T11

4

T269

43

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

21

1

T121

2

T266

1

T351

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

83

1

T234

5

T311

9

T87

7

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

23

1

T81

1

T257

1

T312

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

43

1

T58

1

T122

2

T124

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

6

1

T353

1

T379

2

T380

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

80

1

T3

13

T29

1

T81

12

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

53

1

T4

1

T29

4

T80

8

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

55

1

T117

5

T266

7

T270

12

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

37

1

T122

2

T118

4

T87

3

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

96

1

T121

6

T266

7

T270

12

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

17

1

T11

1

T351

1

T87

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

15

1

T4

2

T10

3

T124

3

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

12

1

T10

3

T381

1

T153

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

53

1

T264

10

T254

1

T271

6

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

8

1

T381

1

T382

1

T109

4

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

1

1

T132

1

-

-

-

-

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

12

1

T255

2

T264

2

T381

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

36

1

T118

5

T255

3

T266

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

4

1

T11

1

T273

1

T132

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

7

1

T4

1

T58

1

T80

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

4

1

T383

2

T384

2

-

-

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded