Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.12	95.12	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	95.12	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.12	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	4	58	93.55

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	4	27	87.10	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2004

1

T1

5

T25

8

T6

5

auto[1]

638

1

T1

14

T6

13

T10

4

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1977

1

T1

12

T25

4

T6

14

auto[1]

665

1

T1

7

T25

4

T6

4

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2035

1

T1

19

T25

4

T6

13

auto[1]

607

1

T25

4

T6

5

T26

10

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2006

1

T1

12

T25

6

T6

15

auto[1]

636

1

T1

7

T25

2

T6

3

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2364

1

T1

19

T25

4

T6

18

auto[1]

278

1

T25

4

T26

19

T42

16

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2389

1

T1

19

T25

8

T6

18

auto[1]

253

1

T26

10

T12

16

T42

3

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2374

1

T1

19

T25

8

T6

18

auto[1]

268

1

T26

9

T12

8

T42

2

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2451

1

T1

19

T25

8

T6

18

auto[1]

191

1

T26

2

T12

6

T42

4

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2419

1

T1

19

T25

4

T6

18

auto[1]

223

1

T25

4

T12

6

T42

4

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2022

1

T1

17

T25

8

T6

11

auto[1]

620

1

T1

2

T6

7

T26

19

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	4	27	87.10	4
Automatically Generated Cross Bins	31	4	27	87.10	4
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

cp_precondition_key0_in_sel

cp_precondition_key1_in_sel

cp_precondition_key2_in_sel

cp_precondition_pwrb_in_sel

cp_precondition_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

934

1

T1

19

T6

18

T10

7

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

90

1

T42

4

T256

2

T118

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

55

1

T33

1

T65

2

T68

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

30

1

T25

4

T181

10

T75

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

60

1

T26

2

T255

1

T330

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

5

1

T178

2

T339

1

T340

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

30

1

T181

4

T341

1

T168

5

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

6

1

T42

2

T87

2

T78

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

64

1

T65

3

T106

2

T254

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

30

1

T65

1

T181

9

T327

8

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

8

1

T106

2

T325

6

-

-

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

11

1

T329

7

T332

4

-

-

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

32

1

T12

6

T327

7

T328

4

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

7

1

T66

4

T342

1

T332

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

6

1

T339

1

T144

3

T343

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

74

1

T12

10

T106

4

T254

3

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

21

1

T42

2

T178

2

T327

3

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

34

1

T12

4

T75

1

T344

7

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

9

1

T254

3

T90

2

T329

4

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

19

1

T256

1

T321

9

T168

4

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

2

1

T345

1

T325

1

-

-

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

2

1

T68

1

T255

1

-

-

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

43

1

T178

4

T144

36

T340

3

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

10

1

T346

4

T347

1

T348

5

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

6

1

T12

2

T331

4

-

-

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

4

1

T66

2

T349

2

-

-

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

1

1

T350

1

-

-

-

-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

172

1

T1

12

T6

11

T12

4

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

101

1

T72

9

T40

1

T256

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

47

1

T10

1

T132

6

T106

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

98

1

T12

2

T32

14

T71

11

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

80

1

T10

3

T80

3

T178

8

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

66

1

T102

2

T181

9

T153

7

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

27

1

T265

3

T144

24

-

-

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

132

1

T42

2

T107

9

T319

6

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

82

1

T68

1

T255

1

T351

4

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

31

1

T60

1

T108

5

T171

8

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

16

1

T106

4

T257

3

T176

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

53

1

T32

5

T60

1

T254

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

15

1

T72

5

T254

3

T195

5

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

52

1

T6

3

T12

10

T42

6

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

11

1

T107

2

T75

1

T323

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

182

1

T26

2

T65

1

T68

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

46

1

T352

5

T353

2

T95

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

80

1

T12

6

T66

4

T132

4

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

14

1

T6

2

T102

1

T255

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

59

1

T1

3

T10

1

T65

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

24

1

T1

2

T107

2

T317

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

27

1

T1

2

T319

2

T118

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

14

1

T153

2

T93

1

T354

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

55

1

T25

2

T10

2

T60

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

24

1

T352

3

T317

2

T80

4

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

22

1

T6

2

T178

2

T322

6

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

15

1

T71

1

T108

1

T137

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

18

1

T25

2

T33

1

T352

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

12

1

T123

3

T324

2

T355

4

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

15

1

T72

1

T93

2

T286

6

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

3

1

T123

2

T267

1

-

-

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded