Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
91.46	91.46	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	91.46	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.46	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	7	55	88.71

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	7	24	77.42	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1765

1

T20

27

T32

4

T42

8

auto[1]

607

1

T20

1

T32

3

T92

2

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1897

1

T20

22

T32

4

T42

6

auto[1]

475

1

T20

6

T32

3

T42

2

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1736

1

T20

28

T42

8

T92

13

auto[1]

636

1

T32

7

T92

7

T40

3

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1802

1

T20

28

T32

7

T42

7

auto[1]

570

1

T42

1

T95

2

T41

6

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2158

1

T20

22

T32

7

T42

8

auto[1]

214

1

T20

6

T92

4

T95

5

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2111

1

T20

28

T32

7

T42

7

auto[1]

261

1

T42

1

T92

2

T95

2

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2182

1

T20

28

T32

7

T42

6

auto[1]

190

1

T42

2

T224

9

T261

4

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2225

1

T20

27

T32

7

T42

8

auto[1]

147

1

T20

1

T92

6

T95

2

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2197

1

T20

27

T32

7

T42

8

auto[1]

175

1

T20

1

T92

5

T95

2

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1813

1

T20

28

T32

3

T42

5

auto[1]

559

1

T32

4

T42

3

T40

2

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	7	24	77.42	7
Automatically Generated Cross Bins	31	7	24	77.42	7
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Element holes

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	*	[auto[1]]	[auto[1]]	--	--	2
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	--	--	2

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[0]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_precondition_key0_in_sel

cp_precondition_key1_in_sel

cp_precondition_key2_in_sel

cp_precondition_pwrb_in_sel

cp_precondition_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

795

1

T32

7

T40

3

T43

16

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

81

1

T224

4

T261

2

T354

22

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

42

1

T92

2

T41

3

T224

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

13

1

T355

2

T356

9

T357

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

29

1

T225

3

T253

5

T334

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

9

1

T92

1

T41

3

T348

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

16

1

T20

1

T346

1

T358

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

3

1

T225

1

T359

2

-

-

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

58

1

T42

2

T224

5

T227

4

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

21

1

T224

4

T360

2

T345

4

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

28

1

T345

7

T350

11

T359

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

3

1

T345

3

-

-

-

-

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

8

1

T261

2

T360

1

T228

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

7

1

T360

1

T361

2

T362

4

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

3

1

T253

3

-

-

-

-

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

105

1

T42

1

T232

5

T233

6

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

20

1

T250

8

T363

1

T361

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

21

1

T41

3

T221

4

T107

3

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

32

1

T232

5

T222

6

T364

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

2

1

T346

1

T365

1

-

-

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

11

1

T92

1

T41

2

T350

7

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

29

1

T261

2

T253

4

T350

11

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

2

1

T359

1

T366

1

-

-

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

2

1

T355

2

-

-

-

-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

102

1

T20

1

T92

1

T43

10

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

87

1

T232

5

T222

11

T224

4

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

50

1

T44

6

T236

5

T129

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

124

1

T41

3

T235

10

T133

11

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

60

1

T235

4

T221

2

T237

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

41

1

T42

1

T329

5

T164

5

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

30

1

T44

2

T133

4

T112

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

142

1

T92

3

T39

20

T41

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

70

1

T329

8

T167

3

T239

8

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

70

1

T32

4

T43

6

T44

7

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

29

1

T104

1

T251

2

T236

4

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

51

1

T104

3

T135

5

T250

8

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

25

1

T235

3

T252

2

T367

4

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

27

1

T234

1

T135

2

T261

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

12

1

T114

1

T332

3

T368

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

53

1

T334

6

T241

9

T369

11

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

48

1

T104

6

T253

3

T339

5

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

47

1

T42

2

T237

4

T225

3

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

18

1

T111

4

T112

4

T261

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

63

1

T224

4

T354

11

T370

4

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

17

1

T133

3

T371

2

T332

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

21

1

T234

4

T371

3

T115

4

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

8

1

T255

2

T258

2

T372

4

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

26

1

T225

1

T167

4

T369

7

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

38

1

T32

3

T40

1

T224

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

29

1

T40

2

T252

1

T329

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

10

1

T254

2

T373

6

T374

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

18

1

T251

3

T371

2

T167

3

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

17

1

T41

3

T329

3

T368

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

1

1

T375

1

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

6

1

T238

1

T262

1

T263

1

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded