Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg
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Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
91.46 91.46 1 100 1 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
sysrst_ctrl_combo_key_combinations_cg 91.46 1 100 1 64 64



Group Instance : sysrst_ctrl_combo_key_combinations_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
91.46 1 100 1 64 64



Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   
Variables 20 0 20 100.00
Crosses 62 7 55 88.71


Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_ac_present_sel 2 0 2 100.00 100 1 1 2
cp_key0_in_sel 2 0 2 100.00 100 1 1 2
cp_key1_in_sel 2 0 2 100.00 100 1 1 2
cp_key2_in_sel 2 0 2 100.00 100 1 1 2
cp_precondition_ac_present_sel 2 0 2 100.00 100 1 1 2
cp_precondition_key0_in_sel 2 0 2 100.00 100 1 1 2
cp_precondition_key1_in_sel 2 0 2 100.00 100 1 1 2
cp_precondition_key2_in_sel 2 0 2 100.00 100 1 1 2
cp_precondition_pwrb_in_sel 2 0 2 100.00 100 1 1 2
cp_pwrb_in_sel 2 0 2 100.00 100 1 1 2


Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg
CROSS   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   PRINT MISSING   COMMENT   
cross_key_combinations_combo_precondition_sel 31 7 24 77.42 100 1 1 0
cross_key_combinations_combo_detection_sel 31 0 31 100.00 100 1 1 0


Summary for Variable cp_ac_present_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_ac_present_sel

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 2376 1 T11 44 T32 10 T30 3
auto[1] 570 1 T6 8 T32 6 T30 1


Summary for Variable cp_key0_in_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key0_in_sel

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 2305 1 T6 8 T11 44 T32 6
auto[1] 641 1 T32 10 T42 3 T41 12


Summary for Variable cp_key1_in_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key1_in_sel

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 2166 1 T6 8 T11 44 T32 9
auto[1] 780 1 T32 7 T40 6 T42 15


Summary for Variable cp_key2_in_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key2_in_sel

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 2316 1 T6 8 T11 33 T32 12
auto[1] 630 1 T11 11 T32 4 T30 1


Summary for Variable cp_precondition_ac_present_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_precondition_ac_present_sel

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 2605 1 T6 8 T11 44 T32 16
auto[1] 341 1 T88 7 T91 2 T124 4


Summary for Variable cp_precondition_key0_in_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_precondition_key0_in_sel

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 2653 1 T6 8 T11 33 T32 16
auto[1] 293 1 T11 11 T30 1 T40 4


Summary for Variable cp_precondition_key1_in_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_precondition_key1_in_sel

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 2678 1 T6 8 T11 33 T32 16
auto[1] 268 1 T11 11 T40 6 T91 3


Summary for Variable cp_precondition_key2_in_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_precondition_key2_in_sel

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 2631 1 T6 8 T11 44 T32 16
auto[1] 315 1 T40 6 T88 2 T91 2


Summary for Variable cp_precondition_pwrb_in_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 2687 1 T6 8 T11 44 T32 16
auto[1] 259 1 T88 2 T91 2 T92 4


Summary for Variable cp_pwrb_in_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_pwrb_in_sel

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 2297 1 T6 8 T11 33 T32 9
auto[1] 649 1 T11 11 T32 7 T40 6


Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel
CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   MISSING   
TOTAL 31 7 24 77.42 7
Automatically Generated Cross Bins 31 7 24 77.42 7
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Element holes
cp_precondition_key0_in_sel   cp_precondition_key1_in_sel   cp_precondition_key2_in_sel   cp_precondition_pwrb_in_sel   cp_precondition_ac_present_sel   COUNT   AT LEAST   NUMBER   STATUS   
[auto[1]] [auto[0]] [auto[1]] [auto[1]] * -- -- 2
[auto[1]] [auto[1]] [auto[0]] [auto[1]] * -- -- 2


Uncovered bins
cp_precondition_key0_in_sel   cp_precondition_key1_in_sel   cp_precondition_key2_in_sel   cp_precondition_pwrb_in_sel   cp_precondition_ac_present_sel   COUNT   AT LEAST   NUMBER   STATUS   
[auto[0]] [auto[1]] [auto[1]] [auto[1]] [auto[1]] 0 1 1
[auto[1]] [auto[1]] [auto[0]] [auto[0]] [auto[1]] 0 1 1
[auto[1]] [auto[1]] [auto[1]] [auto[1]] [auto[0]] 0 1 1


Covered bins
cp_precondition_key0_in_sel   cp_precondition_key1_in_sel   cp_precondition_key2_in_sel   cp_precondition_pwrb_in_sel   cp_precondition_ac_present_sel   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] auto[0] auto[0] auto[0] auto[0] 869 1 T6 8 T32 11 T42 6
auto[0] auto[0] auto[0] auto[0] auto[1] 64 1 T88 6 T124 4 T199 4
auto[0] auto[0] auto[0] auto[1] auto[0] 64 1 T92 3 T265 1 T427 2
auto[0] auto[0] auto[0] auto[1] auto[1] 17 1 T350 4 T351 1 T326 8
auto[0] auto[0] auto[1] auto[0] auto[0] 116 1 T40 6 T92 6 T328 7
auto[0] auto[0] auto[1] auto[0] auto[1] 31 1 T134 6 T428 9 T429 5
auto[0] auto[0] auto[1] auto[1] auto[0] 32 1 T88 1 T329 3 T430 2
auto[0] auto[0] auto[1] auto[1] auto[1] 12 1 T91 2 T431 5 T432 2
auto[0] auto[1] auto[0] auto[0] auto[0] 32 1 T40 6 T433 2 T415 2
auto[0] auto[1] auto[0] auto[0] auto[1] 36 1 T350 4 T411 8 T434 9
auto[0] auto[1] auto[0] auto[1] auto[0] 35 1 T350 4 T138 2 T425 3
auto[0] auto[1] auto[0] auto[1] auto[1] 21 1 T411 16 T435 3 T436 2
auto[0] auto[1] auto[1] auto[0] auto[0] 38 1 T431 17 T437 5 T438 4
auto[0] auto[1] auto[1] auto[0] auto[1] 5 1 T439 2 T440 3 - -
auto[0] auto[1] auto[1] auto[1] auto[0] 1 1 T344 1 - - - -
auto[1] auto[0] auto[0] auto[0] auto[0] 51 1 T30 1 T40 4 T124 1
auto[1] auto[0] auto[0] auto[0] auto[1] 69 1 T420 4 T425 5 T428 22
auto[1] auto[0] auto[0] auto[1] auto[0] 36 1 T199 3 T420 2 T413 28
auto[1] auto[0] auto[0] auto[1] auto[1] 9 1 T441 1 T442 1 T443 5
auto[1] auto[0] auto[1] auto[0] auto[0] 17 1 T444 9 T445 2 T446 1
auto[1] auto[0] auto[1] auto[0] auto[1] 27 1 T431 10 T444 5 T447 2
auto[1] auto[1] auto[0] auto[0] auto[0] 47 1 T11 11 T91 3 T92 1
auto[1] auto[1] auto[1] auto[0] auto[0] 10 1 T448 5 T449 4 T450 1
auto[1] auto[1] auto[1] auto[0] auto[1] 1 1 T199 1 - - - -


User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins
NAMECOUNTSTATUS
detection_disable 0 Excluded


Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel
CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   MISSING   
TOTAL 31 0 31 100.00
Automatically Generated Cross Bins 31 0 31 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins
cp_key0_in_sel   cp_key1_in_sel   cp_key2_in_sel   cp_pwrb_in_sel   cp_ac_present_sel   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] auto[0] auto[0] auto[0] auto[1] 91 1 T6 8 T124 1 T361 11
auto[0] auto[0] auto[0] auto[1] auto[0] 146 1 T174 14 T178 8 T44 4
auto[0] auto[0] auto[0] auto[1] auto[1] 42 1 T451 5 T452 8 T445 2
auto[0] auto[0] auto[1] auto[0] auto[0] 119 1 T40 4 T178 8 T92 1
auto[0] auto[0] auto[1] auto[0] auto[1] 81 1 T32 4 T30 1 T40 6
auto[0] auto[0] auto[1] auto[1] auto[0] 68 1 T11 11 T318 8 T361 4
auto[0] auto[0] auto[1] auto[1] auto[1] 18 1 T318 5 T361 2 T331 2
auto[0] auto[1] auto[0] auto[0] auto[0] 173 1 T91 2 T124 4 T134 6
auto[0] auto[1] auto[0] auto[0] auto[1] 81 1 T121 6 T345 3 T199 3
auto[0] auto[1] auto[0] auto[1] auto[0] 73 1 T40 6 T41 6 T362 7
auto[0] auto[1] auto[0] auto[1] auto[1] 26 1 T32 2 T185 4 T219 1
auto[0] auto[1] auto[1] auto[0] auto[0] 72 1 T363 8 T350 4 T139 3
auto[0] auto[1] auto[1] auto[0] auto[1] 24 1 T272 1 T274 4 T142 1
auto[0] auto[1] auto[1] auto[1] auto[0] 25 1 T139 1 T453 2 T108 1
auto[0] auto[1] auto[1] auto[1] auto[1] 14 1 T42 3 T274 2 T334 3
auto[1] auto[0] auto[0] auto[0] auto[0] 172 1 T41 8 T174 11 T178 8
auto[1] auto[0] auto[0] auto[0] auto[1] 35 1 T88 1 T43 4 T92 3
auto[1] auto[0] auto[0] auto[1] auto[0] 53 1 T174 7 T193 1 T351 1
auto[1] auto[0] auto[0] auto[1] auto[1] 15 1 T219 2 T238 2 T367 2
auto[1] auto[0] auto[1] auto[0] auto[0] 57 1 T41 4 T88 6 T362 6
auto[1] auto[0] auto[1] auto[0] auto[1] 27 1 T121 4 T362 1 T139 1
auto[1] auto[0] auto[1] auto[1] auto[0] 19 1 T251 2 T137 1 T274 3
auto[1] auto[0] auto[1] auto[1] auto[1] 5 1 T251 1 T185 1 T414 3
auto[1] auto[1] auto[0] auto[0] auto[0] 73 1 T32 5 T410 4 T407 7
auto[1] auto[1] auto[0] auto[0] auto[1] 26 1 T174 1 T43 6 T108 1
auto[1] auto[1] auto[0] auto[1] auto[0] 48 1 T352 1 T272 1 T431 22
auto[1] auto[1] auto[0] auto[1] auto[1] 5 1 T185 2 T136 1 T349 1
auto[1] auto[1] auto[1] auto[0] auto[0] 23 1 T251 2 T92 3 T327 1
auto[1] auto[1] auto[1] auto[0] auto[1] 19 1 T363 1 T137 1 T453 4
auto[1] auto[1] auto[1] auto[1] auto[0] 5 1 T274 2 T454 2 T452 1
auto[1] auto[1] auto[1] auto[1] auto[1] 5 1 T42 3 T178 1 T455 1


User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins
NAMECOUNTSTATUS
detection_disable 0 Excluded