Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

747

1

T13

12

T49

10

T50

12

auto[1]

796

1

T13

6

T49

10

T50

8

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

360

1

T13

4

T49

3

T50

8

from_0to1

354

1

T13

4

T49

4

T50

7

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

761

1

T13

9

T49

10

T50

12

auto[1]

782

1

T13

9

T49

10

T50

8

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

804

1

T13

10

T49

11

T50

11

auto[1]

739

1

T13

8

T49

9

T50

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

41

1

T13

1

T50

2

T51

1

auto[0]

from_1to0

auto[0]

auto[1]

39

1

T50

2

T146

2

T184

1

auto[0]

from_1to0

auto[1]

auto[0]

41

1

T39

1

T212

1

T213

2

auto[0]

from_1to0

auto[1]

auto[1]

47

1

T13

1

T49

1

T51

3

auto[0]

from_0to1

auto[0]

auto[0]

31

1

T13

1

T51

1

T41

1

auto[0]

from_0to1

auto[0]

auto[1]

45

1

T50

1

T51

1

T53

1

auto[0]

from_0to1

auto[1]

auto[0]

67

1

T13

1

T49

2

T50

2

auto[0]

from_0to1

auto[1]

auto[1]

28

1

T13

1

T50

1

T212

2

auto[1]

from_1to0

auto[0]

auto[0]

57

1

T13

2

T49

1

T50

1

auto[1]

from_1to0

auto[0]

auto[1]

38

1

T50

1

T53

1

T54

1

auto[1]

from_1to0

auto[1]

auto[0]

47

1

T50

1

T54

2

T31

1

auto[1]

from_1to0

auto[1]

auto[1]

50

1

T49

1

T50

1

T53

2

auto[1]

from_0to1

auto[0]

auto[0]

44

1

T49

2

T50

2

T51

1

auto[1]

from_0to1

auto[0]

auto[1]

41

1

T13

1

T50

1

T53

1

auto[1]

from_0to1

auto[1]

auto[0]

44

1

T41

1

T146

2

T214

1

auto[1]

from_0to1

auto[1]

auto[1]

54

1

T54

1

T41

1

T31

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

767

1

T13

5

T49

9

T50

9

auto[1]

776

1

T13

13

T49

11

T50

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

389

1

T13

5

T49

6

T50

4

from_0to1

378

1

T13

4

T49

6

T50

3

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

784

1

T13

8

T49

8

T50

13

auto[1]

759

1

T13

10

T49

12

T50

7

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

783

1

T13

10

T49

10

T50

11

auto[1]

760

1

T13

8

T49

10

T50

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

42

1

T13

1

T49

1

T39

1

auto[0]

from_1to0

auto[0]

auto[1]

53

1

T50

1

T51

1

T54

1

auto[0]

from_1to0

auto[1]

auto[0]

48

1

T13

1

T51

2

T53

3

auto[0]

from_1to0

auto[1]

auto[1]

47

1

T50

1

T39

1

T146

1

auto[0]

from_0to1

auto[0]

auto[0]

50

1

T49

1

T50

1

T51

1

auto[0]

from_0to1

auto[0]

auto[1]

50

1

T49

1

T51

1

T39

1

auto[0]

from_0to1

auto[1]

auto[0]

54

1

T49

2

T53

1

T54

1

auto[0]

from_0to1

auto[1]

auto[1]

41

1

T49

1

T51

1

T53

1

auto[1]

from_1to0

auto[0]

auto[0]

50

1

T13

1

T50

1

T53

1

auto[1]

from_1to0

auto[0]

auto[1]

51

1

T13

1

T50

1

T51

1

auto[1]

from_1to0

auto[1]

auto[0]

56

1

T49

2

T51

1

T54

1

auto[1]

from_1to0

auto[1]

auto[1]

42

1

T13

1

T49

3

T51

2

auto[1]

from_0to1

auto[0]

auto[0]

39

1

T50

1

T212

1

T213

1

auto[1]

from_0to1

auto[0]

auto[1]

48

1

T51

1

T39

2

T41

1

auto[1]

from_0to1

auto[1]

auto[0]

60

1

T13

2

T49

1

T50

1

auto[1]

from_0to1

auto[1]

auto[1]

36

1

T13

2

T51

1

T41

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

783

1

T13

12

T49

10

T50

10

auto[1]

760

1

T13

6

T49

10

T50

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

358

1

T13

5

T49

5

T50

5

from_0to1

355

1

T13

5

T49

5

T50

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

728

1

T13

8

T49

9

T50

11

auto[1]

815

1

T13

10

T49

11

T50

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

769

1

T13

9

T49

7

T50

9

auto[1]

774

1

T13

9

T49

13

T50

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

38

1

T13

1

T50

2

T39

1

auto[0]

from_1to0

auto[0]

auto[1]

33

1

T49

3

T51

2

T39

1

auto[0]

from_1to0

auto[1]

auto[0]

64

1

T13

1

T53

1

T54

1

auto[0]

from_1to0

auto[1]

auto[1]

51

1

T13

1

T50

1

T54

2

auto[0]

from_0to1

auto[0]

auto[0]

36

1

T13

2

T50

1

T51

1

auto[0]

from_0to1

auto[0]

auto[1]

42

1

T49

2

T50

1

T51

1

auto[0]

from_0to1

auto[1]

auto[0]

42

1

T49

1

T53

2

T39

2

auto[0]

from_0to1

auto[1]

auto[1]

50

1

T13

2

T50

1

T51

1

auto[1]

from_1to0

auto[0]

auto[0]

46

1

T51

1

T53

1

T54

1

auto[1]

from_1to0

auto[0]

auto[1]

40

1

T13

2

T49

1

T50

1

auto[1]

from_1to0

auto[1]

auto[0]

44

1

T50

1

T51

2

T53

1

auto[1]

from_1to0

auto[1]

auto[1]

42

1

T49

1

T51

1

T39

1

auto[1]

from_0to1

auto[0]

auto[0]

53

1

T50

1

T51

1

T53

1

auto[1]

from_0to1

auto[0]

auto[1]

40

1

T50

1

T51

2

T41

1

auto[1]

from_0to1

auto[1]

auto[0]

45

1

T13

1

T49

2

T54

1

auto[1]

from_0to1

auto[1]

auto[1]

47

1

T50

1

T54

1

T39

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

786

1

T13

10

T49

15

T50

9

auto[1]

757

1

T13

8

T49

5

T50

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

367

1

T13

3

T49

6

T50

6

from_0to1

360

1

T13

3

T49

5

T50

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

763

1

T13

13

T49

10

T50

13

auto[1]

780

1

T13

5

T49

10

T50

7

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

796

1

T13

14

T49

10

T50

10

auto[1]

747

1

T13

4

T49

10

T50

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

44

1

T13

1

T50

1

T53

2

auto[0]

from_1to0

auto[0]

auto[1]

47

1

T49

3

T50

1

T51

1

auto[0]

from_1to0

auto[1]

auto[0]

49

1

T49

1

T50

1

T53

1

auto[0]

from_1to0

auto[1]

auto[1]

44

1

T49

1

T39

2

T212

2

auto[0]

from_0to1

auto[0]

auto[0]

68

1

T13

1

T49

1

T50

1

auto[0]

from_0to1

auto[0]

auto[1]

38

1

T50

1

T53

1

T39

1

auto[0]

from_0to1

auto[1]

auto[0]

46

1

T53

1

T41

1

T214

1

auto[0]

from_0to1

auto[1]

auto[1]

45

1

T49

2

T51

1

T53

1

auto[1]

from_1to0

auto[0]

auto[0]

45

1

T51

1

T41

1

T146

1

auto[1]

from_1to0

auto[0]

auto[1]

50

1

T13

1

T49

1

T50

1

auto[1]

from_1to0

auto[1]

auto[0]

39

1

T13

1

T51

1

T146

1

auto[1]

from_1to0

auto[1]

auto[1]

49

1

T50

2

T51

1

T39

1

auto[1]

from_0to1

auto[0]

auto[0]

45

1

T13

1

T50

2

T51

1

auto[1]

from_0to1

auto[0]

auto[1]

32

1

T50

1

T41

2

T146

1

auto[1]

from_0to1

auto[1]

auto[0]

43

1

T13

1

T49

2

T41

1

auto[1]

from_0to1

auto[1]

auto[1]

43

1

T50

1

T54

1

T212

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

767

1

T13

11

T49

8

T50

8

auto[1]

776

1

T13

7

T49

12

T50

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

364

1

T13

4

T49

3

T50

4

from_0to1

373

1

T13

4

T49

4

T50

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

768

1

T13

8

T49

8

T50

10

auto[1]

775

1

T13

10

T49

12

T50

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

777

1

T13

8

T49

8

T50

7

auto[1]

766

1

T13

10

T49

12

T50

13

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

46

1

T13

1

T49

1

T54

1

auto[0]

from_1to0

auto[0]

auto[1]

39

1

T13

1

T49

1

T51

1

auto[0]

from_1to0

auto[1]

auto[0]

40

1

T49

1

T53

2

T54

1

auto[0]

from_1to0

auto[1]

auto[1]

53

1

T13

1

T50

2

T51

1

auto[0]

from_0to1

auto[0]

auto[0]

41

1

T53

1

T54

1

T39

1

auto[0]

from_0to1

auto[0]

auto[1]

54

1

T13

1

T49

1

T50

1

auto[0]

from_0to1

auto[1]

auto[0]

48

1

T51

2

T54

1

T39

1

auto[0]

from_0to1

auto[1]

auto[1]

41

1

T13

1

T50

1

T51

1

auto[1]

from_1to0

auto[0]

auto[0]

38

1

T50

1

T51

1

T39

1

auto[1]

from_1to0

auto[0]

auto[1]

53

1

T13

1

T50

1

T146

1

auto[1]

from_1to0

auto[1]

auto[0]

45

1

T53

2

T39

1

T212

1

auto[1]

from_1to0

auto[1]

auto[1]

50

1

T51

3

T39

1

T41

1

auto[1]

from_0to1

auto[0]

auto[0]

50

1

T50

1

T51

1

T54

1

auto[1]

from_0to1

auto[0]

auto[1]

49

1

T51

2

T53

1

T39

1

auto[1]

from_0to1

auto[1]

auto[0]

54

1

T13

1

T51

1

T53

3

auto[1]

from_0to1

auto[1]

auto[1]

36

1

T13

1

T49

3

T50

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

772

1

T13

7

T49

14

T50

9

auto[1]

771

1

T13

11

T49

6

T50

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

387

1

T13

3

T49

6

T50

5

from_0to1

378

1

T13

3

T49

6

T50

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

790

1

T13

9

T49

12

T50

7

auto[1]

753

1

T13

9

T49

8

T50

13

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

758

1

T13

12

T49

7

T50

8

auto[1]

785

1

T13

6

T49

13

T50

12

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

54

1

T49

2

T53

2

T41

1

auto[0]

from_1to0

auto[0]

auto[1]

51

1

T49

2

T51

2

T53

1

auto[0]

from_1to0

auto[1]

auto[0]

50

1

T13

1

T50

1

T54

1

auto[0]

from_1to0

auto[1]

auto[1]

50

1

T49

1

T50

2

T51

1

auto[0]

from_0to1

auto[0]

auto[0]

45

1

T49

2

T53

1

T54

2

auto[0]

from_0to1

auto[0]

auto[1]

44

1

T49

2

T50

1

T51

1

auto[0]

from_0to1

auto[1]

auto[0]

42

1

T13

1

T49

1

T41

1

auto[0]

from_0to1

auto[1]

auto[1]

55

1

T54

1

T39

2

T146

1

auto[1]

from_1to0

auto[0]

auto[0]

46

1

T13

1

T53

2

T54

2

auto[1]

from_1to0

auto[0]

auto[1]

50

1

T49

1

T50

2

T54

1

auto[1]

from_1to0

auto[1]

auto[0]

40

1

T51

1

T54

1

T212

1

auto[1]

from_1to0

auto[1]

auto[1]

46

1

T13

1

T51

1

T53

1

auto[1]

from_0to1

auto[0]

auto[0]

51

1

T50

1

T53

1

T41

1

auto[1]

from_0to1

auto[0]

auto[1]

57

1

T13

1

T50

1

T51

1

auto[1]

from_0to1

auto[1]

auto[0]

49

1

T13

1

T50

1

T41

1

auto[1]

from_0to1

auto[1]

auto[1]

35

1

T49

1

T50

1

T51

3

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

750

1

T13

15

T49

11

T50

13

auto[1]

793

1

T13

3

T49

9

T50

7

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

379

1

T13

3

T49

5

T50

4

from_0to1

377

1

T13

2

T49

6

T50

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

749

1

T13

12

T49

9

T50

11

auto[1]

794

1

T13

6

T49

11

T50

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

780

1

T13

14

T49

7

T50

6

auto[1]

763

1

T13

4

T49

13

T50

14

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

46

1

T13

2

T49

1

T50

1

auto[0]

from_1to0

auto[0]

auto[1]

48

1

T54

2

T41

1

T212

1

auto[0]

from_1to0

auto[1]

auto[0]

59

1

T13

1

T53

1

T214

1

auto[0]

from_1to0

auto[1]

auto[1]

37

1

T49

1

T50

1

T53

2

auto[0]

from_0to1

auto[0]

auto[0]

42

1

T13

1

T50

1

T53

1

auto[0]

from_0to1

auto[0]

auto[1]

36

1

T49

1

T50

1

T54

1

auto[0]

from_0to1

auto[1]

auto[0]

55

1

T13

1

T49

1

T51

1

auto[0]

from_0to1

auto[1]

auto[1]

43

1

T49

1

T50

1

T41

1

auto[1]

from_1to0

auto[0]

auto[0]

46

1

T53

1

T39

2

T146

3

auto[1]

from_1to0

auto[0]

auto[1]

58

1

T49

1

T50

1

T51

2

auto[1]

from_1to0

auto[1]

auto[0]

45

1

T49

1

T41

1

T212

1

auto[1]

from_1to0

auto[1]

auto[1]

40

1

T49

1

T50

1

T39

1

auto[1]

from_0to1

auto[0]

auto[0]

48

1

T50

1

T51

1

T54

1

auto[1]

from_0to1

auto[0]

auto[1]

51

1

T49

1

T53

3

T54

1

auto[1]

from_0to1

auto[1]

auto[0]

46

1

T49

1

T51

2

T53

1

auto[1]

from_0to1

auto[1]

auto[1]

56

1

T49

1

T51

1

T54

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

767

1

T13

11

T49

13

T50

9

auto[1]

776

1

T13

7

T49

7

T50

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

387

1

T13

5

T49

4

T50

6

from_0to1

385

1

T13

4

T49

5

T50

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

786

1

T13

11

T49

12

T50

10

auto[1]

757

1

T13

7

T49

8

T50

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

794

1

T13

8

T49

10

T50

10

auto[1]

749

1

T13

10

T49

10

T50

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

51

1

T13

1

T50

1

T51

1

auto[0]

from_1to0

auto[0]

auto[1]

46

1

T49

1

T51

1

T54

1

auto[0]

from_1to0

auto[1]

auto[0]

46

1

T13

1

T53

1

T54

1

auto[0]

from_1to0

auto[1]

auto[1]

60

1

T13

1

T50

1

T53

2

auto[0]

from_0to1

auto[0]

auto[0]

53

1

T49

2

T51

2

T54

1

auto[0]

from_0to1

auto[0]

auto[1]

43

1

T13

1

T49

1

T50

1

auto[0]

from_0to1

auto[1]

auto[0]

46

1

T53

2

T54

1

T41

1

auto[0]

from_0to1

auto[1]

auto[1]

41

1

T50

1

T212

2

T214

1

auto[1]

from_1to0

auto[0]

auto[0]

43

1

T13

1

T49

1

T50

2

auto[1]

from_1to0

auto[0]

auto[1]

47

1

T50

1

T51

1

T39

1

auto[1]

from_1to0

auto[1]

auto[0]

43

1

T146

1

T214

1

T31

1

auto[1]

from_1to0

auto[1]

auto[1]

51

1

T13

1

T49

2

T50

1

auto[1]

from_0to1

auto[0]

auto[0]

57

1

T13

1

T49

1

T53

1

auto[1]

from_0to1

auto[0]

auto[1]

45

1

T13

1

T49

1

T50

1

auto[1]

from_0to1

auto[1]

auto[0]

50

1

T13

1

T50

2

T51

1

auto[1]

from_0to1

auto[1]

auto[1]

50

1

T50

1

T51

1

T39

1