Group : sysrst_ctrl_env_pkg::sysrst_ctrl_wakeup_event_obj::sysrst_ctrl_wkup_event_cg
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Group : sysrst_ctrl_env_pkg::sysrst_ctrl_wakeup_event_obj::sysrst_ctrl_wkup_event_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
57.58 57.58 1 100 1 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
sysrst_ctrl_wkup_event_cg 57.58 1 100 1 64 64




Group Instance : sysrst_ctrl_wkup_event_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
57.58 1 100 1 64 64




Summary for Group Instance sysrst_ctrl_wkup_event_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00
Crosses 23 14 9 39.13


Variables for Group Instance sysrst_ctrl_wkup_event_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_h2l_pwrb 2 0 2 100.00 100 1 1 2
cp_h_ac_present 2 0 2 100.00 100 1 1 2
cp_interrupt_gen 2 0 2 100.00 100 1 1 2
cp_l2h_lid_open 2 0 2 100.00 100 1 1 2
cp_wakeup_sts 2 0 2 100.00 100 1 1 2


Crosses for Group Instance sysrst_ctrl_wkup_event_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cross_wkup_sts 23 14 9 39.13 100 1 1 0


Summary for Variable cp_h2l_pwrb

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_h2l_pwrb

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 687 1 T1 2 T47 1 T42 2
auto[1] 593 1 T47 2 T42 2 T2 1



Summary for Variable cp_h_ac_present

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_h_ac_present

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 743 1 T1 2 T47 2 T42 2
auto[1] 537 1 T47 1 T42 2 T2 1



Summary for Variable cp_interrupt_gen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_interrupt_gen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1242 1 T1 2 T47 3 T42 4
auto[1] 38 1 T2 1 T3 1 T37 5



Summary for Variable cp_l2h_lid_open

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_l2h_lid_open

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 791 1 T1 2 T47 2 T42 2
auto[1] 489 1 T47 1 T42 2 T2 1



Summary for Variable cp_wakeup_sts

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_wakeup_sts

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1218 1 T1 2 T47 3 T42 4
auto[1] 62 1 T2 1 T3 1 T6 1



Summary for Cross cross_wkup_sts

Samples crossed: cp_wakeup_sts cp_h2l_pwrb cp_l2h_lid_open cp_h_ac_present cp_interrupt_gen
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 23 14 9 39.13 14
Automatically Generated Cross Bins 23 14 9 39.13 14
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cross_wkup_sts

Element holes
cp_wakeup_stscp_h2l_pwrbcp_l2h_lid_opencp_h_ac_presentcp_interrupt_genCOUNTAT LEASTNUMBERSTATUS
[auto[1]] [auto[0]] * * * -- -- 8
[auto[1]] [auto[1]] [auto[0]] [auto[1]] * -- -- 2
[auto[1]] [auto[1]] [auto[1]] * * -- -- 4


Covered bins
cp_wakeup_stscp_h2l_pwrbcp_l2h_lid_opencp_h_ac_presentcp_interrupt_genCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 311 1 T1 2 T48 1 T13 2
auto[0] auto[0] auto[0] auto[1] auto[0] 132 1 T17 1 T44 1 T13 2
auto[0] auto[0] auto[1] auto[0] auto[0] 100 1 T47 1 T42 2 T45 1
auto[0] auto[0] auto[1] auto[1] auto[0] 138 1 T2 1 T17 2 T43 1
auto[0] auto[1] auto[0] auto[0] auto[0] 141 1 T47 1 T17 2 T34 2
auto[0] auto[1] auto[0] auto[1] auto[0] 139 1 T47 1 T42 2 T17 2
auto[0] auto[1] auto[1] auto[0] auto[0] 125 1 T43 1 T13 2 T50 2
auto[0] auto[1] auto[1] auto[1] auto[0] 121 1 T3 1 T17 1 T43 2
auto[1] auto[1] auto[0] auto[0] auto[1] 27 1 T2 1 T3 1 T37 3


User Defined Cross Bins for cross_wkup_sts

Excluded/Illegal bins
NAMECOUNTSTATUS
invalid0 0 Excluded
invalid1 0 Excluded

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