Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

694

1

T17

2

T26

10

T74

12

auto[1]

691

1

T17

3

T26

10

T74

8

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

335

1

T17

1

T26

6

T74

5

from_0to1

325

1

T17

2

T26

6

T74

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

705

1

T17

2

T26

8

T74

10

auto[1]

680

1

T17

3

T26

12

T74

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

668

1

T17

1

T26

12

T74

10

auto[1]

717

1

T17

4

T26

8

T74

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

47

1

T87

1

T89

1

T171

1

auto[0]

from_1to0

auto[0]

auto[1]

37

1

T26

1

T74

1

T87

1

auto[0]

from_1to0

auto[1]

auto[0]

26

1

T86

1

T89

1

T201

1

auto[0]

from_1to0

auto[1]

auto[1]

47

1

T26

1

T74

1

T87

1

auto[0]

from_0to1

auto[0]

auto[0]

42

1

T26

2

T74

1

T87

2

auto[0]

from_0to1

auto[0]

auto[1]

41

1

T17

1

T86

1

T87

1

auto[0]

from_0to1

auto[1]

auto[0]

37

1

T26

2

T201

1

T59

1

auto[0]

from_0to1

auto[1]

auto[1]

36

1

T26

1

T74

1

T87

2

auto[1]

from_1to0

auto[0]

auto[0]

39

1

T17

1

T26

2

T87

2

auto[1]

from_1to0

auto[0]

auto[1]

48

1

T74

1

T86

1

T87

1

auto[1]

from_1to0

auto[1]

auto[0]

45

1

T26

1

T74

1

T87

2

auto[1]

from_1to0

auto[1]

auto[1]

46

1

T26

1

T74

1

T86

1

auto[1]

from_0to1

auto[0]

auto[0]

41

1

T74

1

T89

3

T395

2

auto[1]

from_0to1

auto[0]

auto[1]

38

1

T74

1

T86

1

T87

3

auto[1]

from_0to1

auto[1]

auto[0]

44

1

T74

1

T86

1

T87

1

auto[1]

from_0to1

auto[1]

auto[1]

46

1

T17

1

T26

1

T86

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

711

1

T17

2

T26

12

T74

10

auto[1]

674

1

T17

3

T26

8

T74

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

345

1

T17

2

T26

6

T74

6

from_0to1

338

1

T17

1

T26

5

T74

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

672

1

T17

1

T26

9

T74

14

auto[1]

713

1

T17

4

T26

11

T74

6

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

682

1

T17

4

T26

11

T74

12

auto[1]

703

1

T17

1

T26

9

T74

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

39

1

T86

1

T396

1

T215

1

auto[0]

from_1to0

auto[0]

auto[1]

47

1

T26

1

T74

1

T87

2

auto[0]

from_1to0

auto[1]

auto[0]

46

1

T17

1

T26

2

T87

2

auto[0]

from_1to0

auto[1]

auto[1]

35

1

T26

2

T89

1

T397

2

auto[0]

from_0to1

auto[0]

auto[0]

52

1

T26

2

T74

2

T86

1

auto[0]

from_0to1

auto[0]

auto[1]

42

1

T74

2

T87

1

T89

1

auto[0]

from_0to1

auto[1]

auto[0]

40

1

T87

3

T201

1

T171

1

auto[0]

from_0to1

auto[1]

auto[1]

45

1

T86

1

T87

2

T89

1

auto[1]

from_1to0

auto[0]

auto[0]

38

1

T17

1

T26

1

T74

1

auto[1]

from_1to0

auto[0]

auto[1]

50

1

T74

1

T86

3

T89

1

auto[1]

from_1to0

auto[1]

auto[0]

42

1

T74

2

T86

1

T87

1

auto[1]

from_1to0

auto[1]

auto[1]

48

1

T74

1

T89

1

T201

1

auto[1]

from_0to1

auto[0]

auto[0]

36

1

T26

1

T74

2

T86

1

auto[1]

from_0to1

auto[0]

auto[1]

37

1

T26

1

T86

1

T396

1

auto[1]

from_0to1

auto[1]

auto[0]

44

1

T17

1

T26

1

T89

2

auto[1]

from_0to1

auto[1]

auto[1]

42

1

T86

1

T201

2

T59

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

692

1

T17

2

T26

11

T74

9

auto[1]

693

1

T17

3

T26

9

T74

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

339

1

T17

2

T26

5

T74

3

from_0to1

333

1

T17

1

T26

4

T74

3

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

671

1

T17

3

T26

10

T74

8

auto[1]

714

1

T17

2

T26

10

T74

12

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

709

1

T17

3

T26

8

T74

15

auto[1]

676

1

T17

2

T26

12

T74

5

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

35

1

T87

2

T89

2

T398

3

auto[0]

from_1to0

auto[0]

auto[1]

44

1

T26

2

T87

1

T89

1

auto[0]

from_1to0

auto[1]

auto[0]

40

1

T17

1

T26

1

T86

1

auto[0]

from_1to0

auto[1]

auto[1]

44

1

T87

1

T201

1

T171

1

auto[0]

from_0to1

auto[0]

auto[0]

41

1

T26

1

T74

1

T399

2

auto[0]

from_0to1

auto[0]

auto[1]

46

1

T87

1

T59

1

T399

1

auto[0]

from_0to1

auto[1]

auto[0]

47

1

T26

1

T74

1

T86

1

auto[0]

from_0to1

auto[1]

auto[1]

47

1

T86

1

T87

2

T201

1

auto[1]

from_1to0

auto[0]

auto[0]

43

1

T17

1

T74

2

T86

1

auto[1]

from_1to0

auto[0]

auto[1]

50

1

T87

1

T201

1

T59

2

auto[1]

from_1to0

auto[1]

auto[0]

46

1

T26

2

T86

1

T87

1

auto[1]

from_1to0

auto[1]

auto[1]

37

1

T74

1

T87

1

T89

1

auto[1]

from_0to1

auto[0]

auto[0]

32

1

T87

2

T201

1

T171

2

auto[1]

from_0to1

auto[0]

auto[1]

29

1

T87

2

T89

1

T59

1

auto[1]

from_0to1

auto[1]

auto[0]

44

1

T74

1

T86

1

T89

1

auto[1]

from_0to1

auto[1]

auto[1]

47

1

T17

1

T26

2

T89

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

711

1

T17

3

T26

11

T74

12

auto[1]

674

1

T17

2

T26

9

T74

8

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

319

1

T26

4

T74

2

T86

6

from_0to1

323

1

T17

1

T26

4

T74

3

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

664

1

T17

2

T26

11

T74

10

auto[1]

721

1

T17

3

T26

9

T74

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

704

1

T17

2

T26

10

T74

7

auto[1]

681

1

T17

3

T26

10

T74

13

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

43

1

T86

3

T87

3

T59

1

auto[0]

from_1to0

auto[0]

auto[1]

40

1

T26

1

T87

4

T201

1

auto[0]

from_1to0

auto[1]

auto[0]

46

1

T26

1

T74

2

T86

1

auto[0]

from_1to0

auto[1]

auto[1]

43

1

T86

1

T87

1

T89

1

auto[0]

from_0to1

auto[0]

auto[0]

38

1

T398

1

T215

1

T249

1

auto[0]

from_0to1

auto[0]

auto[1]

36

1

T17

1

T74

1

T86

1

auto[0]

from_0to1

auto[1]

auto[0]

43

1

T86

1

T87

2

T89

1

auto[0]

from_0to1

auto[1]

auto[1]

42

1

T26

1

T86

1

T87

1

auto[1]

from_1to0

auto[0]

auto[0]

40

1

T86

1

T89

1

T171

1

auto[1]

from_1to0

auto[0]

auto[1]

24

1

T59

1

T215

1

T400

1

auto[1]

from_1to0

auto[1]

auto[0]

39

1

T26

1

T89

1

T201

1

auto[1]

from_1to0

auto[1]

auto[1]

44

1

T26

1

T201

1

T395

4

auto[1]

from_0to1

auto[0]

auto[0]

47

1

T26

1

T74

1

T86

1

auto[1]

from_0to1

auto[0]

auto[1]

36

1

T26

1

T86

1

T87

1

auto[1]

from_0to1

auto[1]

auto[0]

39

1

T74

1

T201

1

T399

2

auto[1]

from_0to1

auto[1]

auto[1]

42

1

T26

1

T87

1

T201

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

691

1

T17

3

T26

9

T74

11

auto[1]

694

1

T17

2

T26

11

T74

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

311

1

T17

1

T26

5

T74

4

from_0to1

312

1

T17

2

T26

5

T74

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

695

1

T17

5

T26

9

T74

9

auto[1]

690

1

T26

11

T74

11

T86

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

703

1

T17

2

T26

11

T74

8

auto[1]

682

1

T17

3

T26

9

T74

12

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

36

1

T17

1

T74

1

T86

2

auto[0]

from_1to0

auto[0]

auto[1]

43

1

T26

1

T74

1

T87

1

auto[0]

from_1to0

auto[1]

auto[0]

40

1

T26

1

T74

1

T59

1

auto[0]

from_1to0

auto[1]

auto[1]

35

1

T87

1

T89

2

T201

1

auto[0]

from_0to1

auto[0]

auto[0]

42

1

T17

1

T26

1

T87

1

auto[0]

from_0to1

auto[0]

auto[1]

31

1

T17

1

T74

1

T395

1

auto[0]

from_0to1

auto[1]

auto[0]

45

1

T26

2

T86

1

T201

1

auto[0]

from_0to1

auto[1]

auto[1]

28

1

T74

1

T89

1

T171

1

auto[1]

from_1to0

auto[0]

auto[0]

40

1

T86

1

T87

1

T201

1

auto[1]

from_1to0

auto[0]

auto[1]

38

1

T26

1

T86

1

T87

2

auto[1]

from_1to0

auto[1]

auto[0]

37

1

T26

1

T87

1

T171

1

auto[1]

from_1to0

auto[1]

auto[1]

42

1

T26

1

T74

1

T86

1

auto[1]

from_0to1

auto[0]

auto[0]

38

1

T86

1

T87

2

T171

2

auto[1]

from_0to1

auto[0]

auto[1]

40

1

T26

1

T74

1

T86

2

auto[1]

from_0to1

auto[1]

auto[0]

42

1

T26

1

T86

1

T89

2

auto[1]

from_0to1

auto[1]

auto[1]

46

1

T74

1

T87

3

T59

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

693

1

T17

1

T26

10

T74

12

auto[1]

692

1

T17

4

T26

10

T74

8

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

323

1

T26

6

T74

4

T86

5

from_0to1

324

1

T26

5

T74

4

T86

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

719

1

T17

3

T26

12

T74

15

auto[1]

666

1

T17

2

T26

8

T74

5

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

685

1

T17

2

T26

9

T74

13

auto[1]

700

1

T17

3

T26

11

T74

7

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

34

1

T26

1

T74

2

T89

1

auto[0]

from_1to0

auto[0]

auto[1]

46

1

T26

1

T74

1

T87

1

auto[0]

from_1to0

auto[1]

auto[0]

43

1

T26

1

T74

1

T86

2

auto[0]

from_1to0

auto[1]

auto[1]

41

1

T26

1

T86

1

T87

1

auto[0]

from_0to1

auto[0]

auto[0]

48

1

T26

1

T74

1

T87

3

auto[0]

from_0to1

auto[0]

auto[1]

35

1

T26

1

T86

1

T87

1

auto[0]

from_0to1

auto[1]

auto[0]

39

1

T86

1

T87

1

T201

2

auto[0]

from_0to1

auto[1]

auto[1]

45

1

T26

1

T89

1

T399

1

auto[1]

from_1to0

auto[0]

auto[0]

39

1

T26

1

T87

1

T201

1

auto[1]

from_1to0

auto[0]

auto[1]

50

1

T26

1

T201

2

T171

1

auto[1]

from_1to0

auto[1]

auto[0]

33

1

T87

2

T395

1

T189

1

auto[1]

from_1to0

auto[1]

auto[1]

37

1

T86

2

T87

1

T59

1

auto[1]

from_0to1

auto[0]

auto[0]

39

1

T74

1

T86

1

T87

1

auto[1]

from_0to1

auto[0]

auto[1]

40

1

T74

1

T86

1

T87

1

auto[1]

from_0to1

auto[1]

auto[0]

34

1

T26

1

T87

1

T395

2

auto[1]

from_0to1

auto[1]

auto[1]

44

1

T26

1

T74

1

T86

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

700

1

T17

1

T26

13

T74

6

auto[1]

685

1

T17

4

T26

7

T74

14

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

318

1

T17

1

T26

4

T74

4

from_0to1

319

1

T17

1

T26

4

T74

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

660

1

T17

4

T26

11

T74

10

auto[1]

725

1

T17

1

T26

9

T74

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

696

1

T17

3

T26

11

T74

8

auto[1]

689

1

T17

2

T26

9

T74

12

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

45

1

T26

2

T74

1

T59

1

auto[0]

from_1to0

auto[0]

auto[1]

36

1

T26

1

T86

2

T87

2

auto[0]

from_1to0

auto[1]

auto[0]

41

1

T87

2

T201

1

T59

1

auto[0]

from_1to0

auto[1]

auto[1]

30

1

T26

1

T86

1

T87

1

auto[0]

from_0to1

auto[0]

auto[0]

34

1

T26

1

T74

1

T87

1

auto[0]

from_0to1

auto[0]

auto[1]

39

1

T26

1

T74

1

T86

1

auto[0]

from_0to1

auto[1]

auto[0]

43

1

T87

1

T171

1

T189

2

auto[0]

from_0to1

auto[1]

auto[1]

47

1

T87

2

T89

2

T201

1

auto[1]

from_1to0

auto[0]

auto[0]

39

1

T17

1

T74

1

T87

1

auto[1]

from_1to0

auto[0]

auto[1]

37

1

T74

2

T87

3

T171

1

auto[1]

from_1to0

auto[1]

auto[0]

37

1

T86

1

T87

1

T59

1

auto[1]

from_1to0

auto[1]

auto[1]

53

1

T89

1

T201

1

T395

1

auto[1]

from_0to1

auto[0]

auto[0]

36

1

T86

1

T201

1

T399

2

auto[1]

from_0to1

auto[0]

auto[1]

35

1

T17

1

T26

1

T87

1

auto[1]

from_0to1

auto[1]

auto[0]

46

1

T26

1

T74

1

T86

2

auto[1]

from_0to1

auto[1]

auto[1]

39

1

T74

2

T87

3

T201

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

692

1

T17

3

T26

12

T74

8

auto[1]

693

1

T17

2

T26

8

T74

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

332

1

T26

3

T74

5

T86

5

from_0to1

334

1

T17

1

T26

3

T74

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

703

1

T17

2

T26

12

T74

9

auto[1]

682

1

T17

3

T26

8

T74

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

698

1

T17

3

T26

8

T74

9

auto[1]

687

1

T17

2

T26

12

T74

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

36

1

T86

1

T87

1

T59

2

auto[0]

from_1to0

auto[0]

auto[1]

41

1

T26

1

T86

1

T87

4

auto[0]

from_1to0

auto[1]

auto[0]

35

1

T74

1

T86

1

T87

1

auto[0]

from_1to0

auto[1]

auto[1]

45

1

T26

1

T74

1

T86

1

auto[0]

from_0to1

auto[0]

auto[0]

40

1

T87

4

T89

1

T201

1

auto[0]

from_0to1

auto[0]

auto[1]

49

1

T87

1

T89

1

T201

1

auto[0]

from_0to1

auto[1]

auto[0]

43

1

T86

2

T201

2

T396

1

auto[0]

from_0to1

auto[1]

auto[1]

35

1

T26

1

T74

1

T87

3

auto[1]

from_1to0

auto[0]

auto[0]

45

1

T74

2

T87

2

T89

1

auto[1]

from_1to0

auto[0]

auto[1]

33

1

T86

1

T87

1

T89

1

auto[1]

from_1to0

auto[1]

auto[0]

50

1

T74

1

T171

3

T395

1

auto[1]

from_1to0

auto[1]

auto[1]

47

1

T26

1

T87

2

T89

1

auto[1]

from_0to1

auto[0]

auto[0]

37

1

T17

1

T86

1

T89

3

auto[1]

from_0to1

auto[0]

auto[1]

38

1

T74

2

T86

1

T87

3

auto[1]

from_0to1

auto[1]

auto[0]

51

1

T26

1

T74

1

T89

1

auto[1]

from_0to1

auto[1]

auto[1]

41

1

T26

1

T74

1

T87

1