Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

988

1

T13

9

T74

12

T191

7

auto[1]

932

1

T13

11

T74

8

T191

13

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

450

1

T13

5

T74

3

T191

2

from_0to1

437

1

T13

5

T74

3

T191

2

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

977

1

T13

10

T74

9

T191

10

auto[1]

943

1

T13

10

T74

11

T191

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

935

1

T13

8

T74

7

T191

8

auto[1]

985

1

T13

12

T74

13

T191

12

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

48

1

T13

1

T44

1

T306

2

auto[0]

from_1to0

auto[0]

auto[1]

54

1

T13

1

T191

1

T225

1

auto[0]

from_1to0

auto[1]

auto[0]

53

1

T74

1

T225

1

T62

1

auto[0]

from_1to0

auto[1]

auto[1]

57

1

T74

2

T62

3

T259

1

auto[0]

from_0to1

auto[0]

auto[0]

64

1

T13

1

T44

3

T225

5

auto[0]

from_0to1

auto[0]

auto[1]

54

1

T306

2

T259

1

T307

1

auto[0]

from_0to1

auto[1]

auto[0]

56

1

T74

1

T44

1

T62

1

auto[0]

from_0to1

auto[1]

auto[1]

46

1

T13

1

T62

2

T307

1

auto[1]

from_1to0

auto[0]

auto[0]

61

1

T13

1

T225

2

T256

3

auto[1]

from_1to0

auto[0]

auto[1]

55

1

T13

2

T191

1

T44

1

auto[1]

from_1to0

auto[1]

auto[0]

59

1

T44

2

T62

2

T259

1

auto[1]

from_1to0

auto[1]

auto[1]

63

1

T306

1

T259

1

T397

1

auto[1]

from_0to1

auto[0]

auto[0]

55

1

T62

3

T259

2

T307

1

auto[1]

from_0to1

auto[0]

auto[1]

56

1

T74

1

T191

1

T44

1

auto[1]

from_0to1

auto[1]

auto[0]

49

1

T191

1

T256

2

T259

1

auto[1]

from_0to1

auto[1]

auto[1]

57

1

T13

3

T74

1

T256

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

969

1

T13

11

T74

9

T191

10

auto[1]

951

1

T13

9

T74

11

T191

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

452

1

T13

3

T74

4

T191

4

from_0to1

457

1

T13

4

T74

5

T191

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

924

1

T13

8

T74

13

T191

10

auto[1]

996

1

T13

12

T74

7

T191

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

957

1

T13

12

T74

7

T191

10

auto[1]

963

1

T13

8

T74

13

T191

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

68

1

T191

1

T225

1

T306

1

auto[0]

from_1to0

auto[0]

auto[1]

55

1

T74

2

T191

1

T44

2

auto[0]

from_1to0

auto[1]

auto[0]

51

1

T44

1

T306

1

T256

1

auto[0]

from_1to0

auto[1]

auto[1]

64

1

T13

1

T44

1

T225

1

auto[0]

from_0to1

auto[0]

auto[0]

54

1

T13

1

T74

1

T191

1

auto[0]

from_0to1

auto[0]

auto[1]

62

1

T74

2

T225

1

T62

2

auto[0]

from_0to1

auto[1]

auto[0]

60

1

T13

3

T191

1

T62

3

auto[0]

from_0to1

auto[1]

auto[1]

61

1

T44

1

T62

2

T306

2

auto[1]

from_1to0

auto[0]

auto[0]

53

1

T13

1

T62

1

T260

2

auto[1]

from_1to0

auto[0]

auto[1]

55

1

T13

1

T74

1

T191

1

auto[1]

from_1to0

auto[1]

auto[0]

58

1

T191

1

T44

1

T62

3

auto[1]

from_1to0

auto[1]

auto[1]

48

1

T74

1

T44

2

T62

3

auto[1]

from_0to1

auto[0]

auto[0]

53

1

T44

1

T225

1

T260

1

auto[1]

from_0to1

auto[0]

auto[1]

35

1

T74

1

T191

1

T44

1

auto[1]

from_0to1

auto[1]

auto[0]

64

1

T44

1

T259

1

T260

1

auto[1]

from_0to1

auto[1]

auto[1]

68

1

T74

1

T191

2

T44

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

980

1

T13

10

T74

12

T191

12

auto[1]

940

1

T13

10

T74

8

T191

8

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

473

1

T13

6

T74

5

T191

6

from_0to1

466

1

T13

7

T74

5

T191

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

968

1

T13

9

T74

10

T191

9

auto[1]

952

1

T13

11

T74

10

T191

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

951

1

T13

10

T74

9

T191

9

auto[1]

969

1

T13

10

T74

11

T191

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

56

1

T13

2

T62

1

T306

2

auto[0]

from_1to0

auto[0]

auto[1]

67

1

T13

2

T191

2

T225

1

auto[0]

from_1to0

auto[1]

auto[0]

63

1

T74

2

T191

2

T62

2

auto[0]

from_1to0

auto[1]

auto[1]

75

1

T74

2

T44

2

T62

2

auto[0]

from_0to1

auto[0]

auto[0]

59

1

T74

1

T191

1

T62

1

auto[0]

from_0to1

auto[0]

auto[1]

58

1

T74

2

T191

1

T62

1

auto[0]

from_0to1

auto[1]

auto[0]

54

1

T13

1

T62

2

T259

1

auto[0]

from_0to1

auto[1]

auto[1]

62

1

T13

3

T74

1

T191

1

auto[1]

from_1to0

auto[0]

auto[0]

50

1

T62

1

T256

2

T259

1

auto[1]

from_1to0

auto[0]

auto[1]

64

1

T13

1

T74

1

T44

3

auto[1]

from_1to0

auto[1]

auto[0]

50

1

T13

1

T191

2

T225

2

auto[1]

from_1to0

auto[1]

auto[1]

48

1

T44

1

T225

2

T62

2

auto[1]

from_0to1

auto[0]

auto[0]

70

1

T13

1

T74

1

T44

1

auto[1]

from_0to1

auto[0]

auto[1]

58

1

T191

1

T44

4

T225

1

auto[1]

from_0to1

auto[1]

auto[0]

57

1

T13

1

T191

2

T44

1

auto[1]

from_0to1

auto[1]

auto[1]

48

1

T13

1

T225

1

T62

4

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

989

1

T13

10

T74

9

T191

9

auto[1]

931

1

T13

10

T74

11

T191

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

475

1

T13

4

T74

5

T191

6

from_0to1

476

1

T13

3

T74

6

T191

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1007

1

T13

10

T74

11

T191

8

auto[1]

913

1

T13

10

T74

9

T191

12

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

966

1

T13

13

T74

10

T191

8

auto[1]

954

1

T13

7

T74

10

T191

12

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

54

1

T13

1

T306

1

T397

1

auto[0]

from_1to0

auto[0]

auto[1]

51

1

T74

1

T225

2

T306

2

auto[0]

from_1to0

auto[1]

auto[0]

59

1

T74

2

T191

1

T44

1

auto[0]

from_1to0

auto[1]

auto[1]

65

1

T13

1

T62

3

T259

1

auto[0]

from_0to1

auto[0]

auto[0]

85

1

T13

1

T191

1

T44

1

auto[0]

from_0to1

auto[0]

auto[1]

61

1

T74

1

T225

1

T62

3

auto[0]

from_0to1

auto[1]

auto[0]

43

1

T13

2

T44

2

T306

1

auto[0]

from_0to1

auto[1]

auto[1]

54

1

T191

2

T62

2

T259

1

auto[1]

from_1to0

auto[0]

auto[0]

58

1

T191

1

T44

2

T62

1

auto[1]

from_1to0

auto[0]

auto[1]

70

1

T74

1

T191

2

T62

1

auto[1]

from_1to0

auto[1]

auto[0]

49

1

T13

2

T74

1

T44

1

auto[1]

from_1to0

auto[1]

auto[1]

69

1

T191

2

T44

1

T256

1

auto[1]

from_0to1

auto[0]

auto[0]

56

1

T74

1

T44

1

T225

1

auto[1]

from_0to1

auto[0]

auto[1]

63

1

T74

1

T191

1

T306

1

auto[1]

from_0to1

auto[1]

auto[0]

62

1

T74

2

T191

1

T62

1

auto[1]

from_0to1

auto[1]

auto[1]

52

1

T74

1

T191

1

T44

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

969

1

T13

13

T74

8

T191

10

auto[1]

951

1

T13

7

T74

12

T191

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

475

1

T13

5

T74

5

T191

6

from_0to1

480

1

T13

5

T74

6

T191

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

984

1

T13

9

T74

13

T191

12

auto[1]

936

1

T13

11

T74

7

T191

8

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

966

1

T13

11

T74

12

T191

11

auto[1]

954

1

T13

9

T74

8

T191

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

64

1

T13

2

T74

2

T191

2

auto[0]

from_1to0

auto[0]

auto[1]

65

1

T74

1

T191

1

T44

2

auto[0]

from_1to0

auto[1]

auto[0]

64

1

T13

1

T225

2

T62

4

auto[0]

from_1to0

auto[1]

auto[1]

53

1

T225

1

T62

2

T306

1

auto[0]

from_0to1

auto[0]

auto[0]

58

1

T191

2

T44

1

T225

2

auto[0]

from_0to1

auto[0]

auto[1]

58

1

T13

1

T225

1

T62

1

auto[0]

from_0to1

auto[1]

auto[0]

66

1

T13

1

T191

1

T62

2

auto[0]

from_0to1

auto[1]

auto[1]

62

1

T13

1

T74

1

T225

1

auto[1]

from_1to0

auto[0]

auto[0]

48

1

T13

1

T74

1

T225

1

auto[1]

from_1to0

auto[0]

auto[1]

60

1

T191

2

T44

1

T62

1

auto[1]

from_1to0

auto[1]

auto[0]

69

1

T13

1

T191

1

T44

1

auto[1]

from_1to0

auto[1]

auto[1]

52

1

T74

1

T44

1

T225

1

auto[1]

from_0to1

auto[0]

auto[0]

67

1

T74

2

T44

1

T225

1

auto[1]

from_0to1

auto[0]

auto[1]

68

1

T13

1

T74

2

T191

1

auto[1]

from_0to1

auto[1]

auto[0]

43

1

T74

1

T44

1

T225

1

auto[1]

from_0to1

auto[1]

auto[1]

58

1

T13

1

T191

1

T44

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

979

1

T13

10

T74

13

T191

14

auto[1]

941

1

T13

10

T74

7

T191

6

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

435

1

T13

5

T74

4

T191

4

from_0to1

440

1

T13

6

T74

4

T191

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

937

1

T13

13

T74

11

T191

5

auto[1]

983

1

T13

7

T74

9

T191

15

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

976

1

T13

10

T74

15

T191

10

auto[1]

944

1

T13

10

T74

5

T191

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

50

1

T74

1

T397

1

T307

1

auto[0]

from_1to0

auto[0]

auto[1]

49

1

T225

1

T62

3

T306

2

auto[0]

from_1to0

auto[1]

auto[0]

55

1

T13

1

T74

1

T191

1

auto[0]

from_1to0

auto[1]

auto[1]

63

1

T13

1

T44

1

T225

1

auto[0]

from_0to1

auto[0]

auto[0]

61

1

T13

2

T74

1

T191

2

auto[0]

from_0to1

auto[0]

auto[1]

55

1

T13

1

T191

1

T259

1

auto[0]

from_0to1

auto[1]

auto[0]

51

1

T74

2

T225

1

T306

1

auto[0]

from_0to1

auto[1]

auto[1]

59

1

T13

1

T44

1

T306

1

auto[1]

from_1to0

auto[0]

auto[0]

49

1

T74

2

T44

1

T62

1

auto[1]

from_1to0

auto[0]

auto[1]

51

1

T13

2

T44

2

T256

3

auto[1]

from_1to0

auto[1]

auto[0]

60

1

T13

1

T191

1

T306

2

auto[1]

from_1to0

auto[1]

auto[1]

58

1

T191

2

T44

1

T225

1

auto[1]

from_0to1

auto[0]

auto[0]

58

1

T13

1

T44

1

T306

1

auto[1]

from_0to1

auto[0]

auto[1]

47

1

T13

1

T44

1

T225

2

auto[1]

from_0to1

auto[1]

auto[0]

60

1

T74

1

T191

1

T44

2

auto[1]

from_0to1

auto[1]

auto[1]

49

1

T44

1

T62

2

T259

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

977

1

T13

7

T74

12

T191

10

auto[1]

943

1

T13

13

T74

8

T191

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

470

1

T13

5

T74

2

T191

6

from_0to1

470

1

T13

5

T74

2

T191

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

970

1

T13

7

T74

10

T191

11

auto[1]

950

1

T13

13

T74

10

T191

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

993

1

T13

11

T74

6

T191

5

auto[1]

927

1

T13

9

T74

14

T191

15

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

65

1

T62

2

T306

3

T260

1

auto[0]

from_1to0

auto[0]

auto[1]

56

1

T191

2

T44

2

T225

1

auto[0]

from_1to0

auto[1]

auto[0]

58

1

T13

1

T62

1

T260

1

auto[0]

from_1to0

auto[1]

auto[1]

53

1

T74

1

T191

1

T44

1

auto[0]

from_0to1

auto[0]

auto[0]

59

1

T74

1

T191

1

T225

1

auto[0]

from_0to1

auto[0]

auto[1]

61

1

T62

1

T260

1

T166

3

auto[0]

from_0to1

auto[1]

auto[0]

60

1

T225

1

T62

3

T398

2

auto[0]

from_0to1

auto[1]

auto[1]

61

1

T74

1

T191

2

T44

1

auto[1]

from_1to0

auto[0]

auto[0]

58

1

T225

1

T62

1

T306

1

auto[1]

from_1to0

auto[0]

auto[1]

59

1

T191

2

T225

1

T62

1

auto[1]

from_1to0

auto[1]

auto[0]

60

1

T13

1

T62

1

T256

2

auto[1]

from_1to0

auto[1]

auto[1]

61

1

T13

3

T74

1

T191

1

auto[1]

from_0to1

auto[0]

auto[0]

58

1

T191

1

T62

1

T256

1

auto[1]

from_0to1

auto[0]

auto[1]

66

1

T13

2

T191

1

T44

1

auto[1]

from_0to1

auto[1]

auto[0]

56

1

T13

1

T44

1

T225

1

auto[1]

from_0to1

auto[1]

auto[1]

49

1

T13

2

T44

1

T62

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

928

1

T13

14

T74

11

T191

10

auto[1]

992

1

T13

6

T74

9

T191

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

446

1

T13

5

T74

4

T191

5

from_0to1

454

1

T13

5

T74

3

T191

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

910

1

T13

9

T74

5

T191

13

auto[1]

1010

1

T13

11

T74

15

T191

7

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

972

1

T13

13

T74

10

T191

9

auto[1]

948

1

T13

7

T74

10

T191

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

46

1

T74

1

T62

1

T256

1

auto[0]

from_1to0

auto[0]

auto[1]

54

1

T13

1

T225

2

T256

1

auto[0]

from_1to0

auto[1]

auto[0]

51

1

T13

1

T74

2

T191

1

auto[0]

from_1to0

auto[1]

auto[1]

57

1

T13

1

T191

1

T44

1

auto[0]

from_0to1

auto[0]

auto[0]

55

1

T13

2

T62

2

T259

2

auto[0]

from_0to1

auto[0]

auto[1]

54

1

T13

1

T191

1

T62

1

auto[0]

from_0to1

auto[1]

auto[0]

55

1

T13

1

T74

1

T44

2

auto[0]

from_0to1

auto[1]

auto[1]

58

1

T13

1

T225

1

T256

2

auto[1]

from_1to0

auto[0]

auto[0]

58

1

T191

1

T44

1

T225

2

auto[1]

from_1to0

auto[0]

auto[1]

57

1

T13

1

T191

2

T306

1

auto[1]

from_1to0

auto[1]

auto[0]

58

1

T74

1

T44

3

T256

2

auto[1]

from_1to0

auto[1]

auto[1]

65

1

T13

1

T225

1

T306

2

auto[1]

from_0to1

auto[0]

auto[0]

54

1

T74

1

T191

3

T44

1

auto[1]

from_0to1

auto[0]

auto[1]

46

1

T44

1

T62

3

T397

1

auto[1]

from_0to1

auto[1]

auto[0]

73

1

T74

1

T191

1

T44

1

auto[1]

from_0to1

auto[1]

auto[1]

59

1

T191

1

T225

2

T62

1