Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	159604	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

124088

1

T4

17

T5

3

T1

317

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	146850	1			T4	22		T5	3		T1	420
values[0x0]	68086	1			T4	12		T5	2		T1	123
values[0x1]	68756	1			T4	10		T1	123		T14	5

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	129435	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

154257

1

T4

23

T5

4

T1

376

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	762	1			T2	5		T3	5		T43	3
valid_sources[0x01]	909	1			T2	3		T18	2		T3	3
valid_sources[0x02]	901	1			T16	6		T2	7		T18	2
valid_sources[0x03]	1121	1			T2	5		T3	3		T43	1
valid_sources[0x04]	995	1			T2	3		T18	1		T19	1
valid_sources[0x05]	884	1			T2	6		T18	1		T3	6
valid_sources[0x06]	981	1			T2	7		T43	1		T25	5
valid_sources[0x07]	1294	1			T2	7		T3	3		T43	5
valid_sources[0x08]	1046	1			T2	6		T3	1		T43	2
valid_sources[0x09]	909	1			T2	5		T3	6		T43	2
valid_sources[0x0a]	929	1			T2	2		T19	1		T20	4
valid_sources[0x0b]	2002	1			T43	3		T25	3		T45	4
valid_sources[0x0c]	1005	1			T2	9		T43	7		T25	2
valid_sources[0x0d]	867	1			T2	2		T18	1		T3	3
valid_sources[0x0e]	1002	1			T2	6		T3	1		T25	3
valid_sources[0x0f]	982	1			T2	1		T3	1		T43	1
valid_sources[0x10]	1032	1			T18	2		T3	6		T61	4
valid_sources[0x11]	1807	1			T2	8		T3	1		T43	5
valid_sources[0x12]	833	1			T17	2		T2	7		T3	3
valid_sources[0x13]	1186	1			T2	7		T3	7		T43	4
valid_sources[0x14]	1378	1			T2	8		T18	1		T3	2
valid_sources[0x15]	1483	1			T2	6		T19	1		T3	3
valid_sources[0x16]	1867	1			T2	5		T18	1		T3	2
valid_sources[0x17]	1448	1			T2	3		T3	1		T43	6
valid_sources[0x18]	877	1			T2	8		T3	3		T43	7
valid_sources[0x19]	969	1			T2	3		T3	5		T43	2
valid_sources[0x1a]	1279	1			T2	1		T3	1		T43	3
valid_sources[0x1b]	892	1			T2	7		T18	2		T3	5
valid_sources[0x1c]	1192	1			T2	2		T43	1		T25	2
valid_sources[0x1d]	876	1			T2	2		T3	3		T43	5
valid_sources[0x1e]	984	1			T3	7		T43	6		T25	3
valid_sources[0x1f]	945	1			T2	13		T18	1		T3	5
valid_sources[0x20]	871	1			T2	11		T18	1		T3	5
valid_sources[0x21]	906	1			T2	5		T3	3		T43	1
valid_sources[0x22]	1709	1			T2	5		T3	10		T43	4
valid_sources[0x23]	936	1			T13	1		T2	2		T3	6
valid_sources[0x24]	1039	1			T2	8		T3	3		T43	3
valid_sources[0x25]	861	1			T2	3		T18	2		T3	4
valid_sources[0x26]	948	1			T2	8		T3	4		T43	9
valid_sources[0x27]	1056	1			T2	3		T3	1		T43	6
valid_sources[0x28]	1019	1			T14	1		T2	3		T18	2
valid_sources[0x29]	994	1			T2	1		T43	4		T25	2
valid_sources[0x2a]	1186	1			T3	1		T43	5		T25	3
valid_sources[0x2b]	949	1			T3	3		T43	1		T45	4
valid_sources[0x2c]	897	1			T2	2		T18	1		T3	5
valid_sources[0x2d]	1171	1			T2	8		T18	1		T3	7
valid_sources[0x2e]	1001	1			T3	2		T43	5		T25	1
valid_sources[0x2f]	1076	1			T2	2		T3	3		T43	6
valid_sources[0x30]	1550	1			T2	3		T3	4		T25	2
valid_sources[0x31]	1083	1			T2	2		T18	1		T3	5
valid_sources[0x32]	1755	1			T17	2		T2	3		T3	5
valid_sources[0x33]	937	1			T2	3		T3	3		T43	1
valid_sources[0x34]	1056	1			T2	2		T3	3		T43	6
valid_sources[0x35]	926	1			T14	1		T2	5		T3	3
valid_sources[0x36]	887	1			T2	5		T3	2		T43	3
valid_sources[0x37]	1022	1			T2	9		T3	1		T43	3
valid_sources[0x38]	854	1			T2	2		T43	2		T25	2
valid_sources[0x39]	2018	1			T2	1		T3	2		T43	1
valid_sources[0x3a]	863	1			T2	2		T3	1		T25	3
valid_sources[0x3b]	970	1			T2	3		T3	5		T25	4
valid_sources[0x3c]	1148	1			T2	3		T18	1		T3	1
valid_sources[0x3d]	1040	1			T15	7		T17	1		T2	8
valid_sources[0x3e]	1205	1			T2	2		T3	1		T43	2
valid_sources[0x3f]	964	1			T2	1		T3	7		T43	5
valid_sources[0x40]	993	1			T2	1		T3	2		T43	10
valid_sources[0x41]	861	1			T14	1		T2	3		T18	1
valid_sources[0x42]	1241	1			T2	5		T18	2		T3	4
valid_sources[0x43]	970	1			T3	1		T43	5		T25	4
valid_sources[0x44]	957	1			T2	6		T19	2		T3	3
valid_sources[0x45]	1219	1			T2	4		T43	1		T25	3
valid_sources[0x46]	892	1			T2	3		T18	2		T20	4
valid_sources[0x47]	970	1			T2	2		T18	1		T3	5
valid_sources[0x48]	988	1			T2	5		T18	1		T3	3
valid_sources[0x49]	907	1			T2	5		T19	2		T3	5
valid_sources[0x4a]	1178	1			T2	4		T3	1		T25	3
valid_sources[0x4b]	999	1			T2	3		T18	1		T3	2
valid_sources[0x4c]	1022	1			T2	6		T18	1		T43	3
valid_sources[0x4d]	902	1			T2	5		T3	2		T43	1
valid_sources[0x4e]	1061	1			T2	7		T18	2		T3	6
valid_sources[0x4f]	868	1			T3	1		T43	2		T25	1
valid_sources[0x50]	951	1			T2	16		T18	1		T3	2
valid_sources[0x51]	948	1			T14	4		T2	4		T19	2
valid_sources[0x52]	1021	1			T2	8		T18	1		T3	2
valid_sources[0x53]	1173	1			T2	8		T3	3		T43	7
valid_sources[0x54]	914	1			T2	1		T18	1		T3	2
valid_sources[0x55]	948	1			T2	4		T18	1		T3	12
valid_sources[0x56]	1289	1			T2	6		T3	3		T43	4
valid_sources[0x57]	860	1			T2	1		T3	5		T43	3
valid_sources[0x58]	928	1			T2	3		T20	7		T3	3
valid_sources[0x59]	812	1			T2	2		T3	2		T43	2
valid_sources[0x5a]	1255	1			T3	3		T43	1		T25	4
valid_sources[0x5b]	948	1			T2	7		T43	7		T25	1
valid_sources[0x5c]	961	1			T15	13		T2	7		T18	1
valid_sources[0x5d]	1059	1			T2	7		T3	1		T43	8
valid_sources[0x5e]	1079	1			T2	4		T3	3		T43	2
valid_sources[0x5f]	1038	1			T3	7		T43	7		T25	2
valid_sources[0x60]	748	1			T2	4		T18	1		T3	5
valid_sources[0x61]	963	1			T2	1		T3	4		T25	5
valid_sources[0x62]	1208	1			T5	1		T2	3		T18	1
valid_sources[0x63]	1469	1			T2	7		T18	1		T3	5
valid_sources[0x64]	1261	1			T2	3		T3	3		T43	4
valid_sources[0x65]	990	1			T18	1		T3	6		T43	5
valid_sources[0x66]	859	1			T2	5		T43	1		T25	2
valid_sources[0x67]	849	1			T2	5		T3	5		T43	13
valid_sources[0x68]	1181	1			T2	5		T18	1		T3	1
valid_sources[0x69]	1179	1			T3	3		T43	3		T25	3
valid_sources[0x6a]	1855	1			T1	666		T2	6		T3	5
valid_sources[0x6b]	812	1			T2	1		T18	1		T19	1
valid_sources[0x6c]	1384	1			T2	5		T3	1		T43	9
valid_sources[0x6d]	959	1			T2	6		T18	1		T3	4
valid_sources[0x6e]	824	1			T2	1		T3	2		T43	2
valid_sources[0x6f]	1141	1			T2	8		T18	1		T3	1
valid_sources[0x70]	1259	1			T17	8		T2	14		T18	1
valid_sources[0x71]	1926	1			T3	5		T43	8		T25	2
valid_sources[0x72]	922	1			T2	7		T18	1		T3	1
valid_sources[0x73]	946	1			T2	9		T18	4		T3	2
valid_sources[0x74]	1545	1			T2	2		T18	1		T43	3
valid_sources[0x75]	1274	1			T2	7		T18	2		T3	3
valid_sources[0x76]	1587	1			T2	2		T3	2		T43	4
valid_sources[0x77]	1040	1			T2	8		T18	2		T19	2
valid_sources[0x78]	1079	1			T2	4		T20	2		T3	5
valid_sources[0x79]	1333	1			T5	1		T2	12		T18	1
valid_sources[0x7a]	760	1			T2	2		T3	2		T43	3
valid_sources[0x7b]	792	1			T2	7		T18	2		T19	4
valid_sources[0x7c]	1683	1			T18	2		T3	2		T43	12
valid_sources[0x7d]	847	1			T2	7		T19	1		T3	3
valid_sources[0x7e]	1171	1			T2	1		T18	3		T3	4
valid_sources[0x7f]	1215	1			T2	4		T19	1		T3	2
valid_sources[0x80]	932	1			T2	3		T20	3		T3	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

66868

1

T4

11

T5

1

T1

204

values[0x0]

all_enables

biggest_size

33477

1

T4

5

T5

2

T1

61

values[0x1]

all_enables

biggest_size

23743

1

T4

1

T1

52

T14

2