Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	147054	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

112966

1

T1

7

T4

25

T5

22

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	138887	1			T1	4		T4	45		T5	22
values[0x0]	60060	1			T1	2		T4	1		T5	14
values[0x1]	61073	1			T1	8		T5	8		T2	5

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	118679	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

141341

1

T1

8

T4

30

T5

25

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1335	1			T4	2		T87	2		T11	1
valid_sources[0x01]	1531	1			T17	2		T103	1		T28	1
valid_sources[0x02]	916	1			T26	1		T66	1		T90	2
valid_sources[0x03]	848	1			T17	2		T76	1		T184	2
valid_sources[0x04]	1295	1			T17	1		T26	2		T87	5
valid_sources[0x05]	1210	1			T17	2		T26	1		T9	1
valid_sources[0x06]	780	1			T1	1		T66	1		T20	3
valid_sources[0x07]	884	1			T16	1		T11	1		T103	3
valid_sources[0x08]	2016	1			T17	2		T26	1		T86	7
valid_sources[0x09]	911	1			T4	3		T16	1		T17	2
valid_sources[0x0a]	924	1			T17	2		T26	1		T9	1
valid_sources[0x0b]	973	1			T5	1		T26	1		T75	4
valid_sources[0x0c]	969	1			T17	2		T26	1		T20	9
valid_sources[0x0d]	852	1			T16	1		T17	2		T7	2
valid_sources[0x0e]	734	1			T11	1		T20	1		T401	2
valid_sources[0x0f]	936	1			T87	2		T90	3		T20	2
valid_sources[0x10]	753	1			T17	1		T87	2		T20	6
valid_sources[0x11]	969	1			T17	1		T103	1		T20	2
valid_sources[0x12]	863	1			T17	2		T75	1		T87	2
valid_sources[0x13]	802	1			T17	1		T88	4		T20	1
valid_sources[0x14]	955	1			T17	1		T75	1		T87	1
valid_sources[0x15]	793	1			T17	1		T26	1		T75	4
valid_sources[0x16]	915	1			T18	5		T26	1		T87	1
valid_sources[0x17]	1032	1			T14	2		T86	6		T103	9
valid_sources[0x18]	864	1			T2	4		T17	1		T26	1
valid_sources[0x19]	867	1			T26	2		T86	2		T87	3
valid_sources[0x1a]	760	1			T26	1		T87	3		T20	3
valid_sources[0x1b]	890	1			T17	1		T86	5		T10	1
valid_sources[0x1c]	1026	1			T4	2		T17	1		T88	5
valid_sources[0x1d]	1031	1			T4	1		T87	2		T103	1
valid_sources[0x1e]	1073	1			T17	3		T6	5		T66	2
valid_sources[0x1f]	858	1			T17	1		T26	1		T87	7
valid_sources[0x20]	758	1			T17	4		T26	2		T76	2
valid_sources[0x21]	896	1			T4	2		T17	1		T26	2
valid_sources[0x22]	1013	1			T5	1		T13	2		T17	1
valid_sources[0x23]	838	1			T5	3		T64	1		T184	2
valid_sources[0x24]	851	1			T17	2		T6	1		T87	6
valid_sources[0x25]	904	1			T5	1		T26	1		T75	4
valid_sources[0x26]	898	1			T87	1		T103	1		T67	1
valid_sources[0x27]	867	1			T4	1		T16	1		T17	2
valid_sources[0x28]	777	1			T17	2		T86	1		T87	2
valid_sources[0x29]	1059	1			T1	1		T17	2		T87	5
valid_sources[0x2a]	928	1			T1	1		T17	1		T26	1
valid_sources[0x2b]	2771	1			T14	2		T18	3		T26	1
valid_sources[0x2c]	1511	1			T17	1		T66	1		T20	5
valid_sources[0x2d]	914	1			T75	1		T87	2		T11	1
valid_sources[0x2e]	767	1			T17	2		T87	2		T20	2
valid_sources[0x2f]	764	1			T5	4		T14	1		T17	1
valid_sources[0x30]	954	1			T17	1		T26	1		T76	1
valid_sources[0x31]	943	1			T14	1		T17	1		T18	2
valid_sources[0x32]	779	1			T17	1		T26	1		T75	5
valid_sources[0x33]	874	1			T17	2		T9	2		T103	3
valid_sources[0x34]	930	1			T17	3		T18	3		T26	1
valid_sources[0x35]	744	1			T17	1		T10	1		T203	2
valid_sources[0x36]	935	1			T5	6		T18	2		T11	1
valid_sources[0x37]	999	1			T17	1		T75	1		T20	5
valid_sources[0x38]	778	1			T14	1		T18	2		T87	2
valid_sources[0x39]	863	1			T4	3		T17	1		T103	1
valid_sources[0x3a]	1887	1			T17	3		T26	1		T64	2
valid_sources[0x3b]	1324	1			T17	1		T26	1		T87	4
valid_sources[0x3c]	1151	1			T17	1		T26	1		T103	3
valid_sources[0x3d]	2763	1			T14	2		T17	1		T20	7
valid_sources[0x3e]	958	1			T1	1		T16	1		T75	5
valid_sources[0x3f]	919	1			T26	1		T8	13		T87	3
valid_sources[0x40]	879	1			T20	5		T290	5		T402	1
valid_sources[0x41]	815	1			T75	1		T87	1		T80	3
valid_sources[0x42]	810	1			T2	2		T17	2		T86	3
valid_sources[0x43]	901	1			T17	2		T87	1		T88	6
valid_sources[0x44]	877	1			T14	1		T17	1		T20	5
valid_sources[0x45]	2909	1			T26	1		T20	3		T395	1
valid_sources[0x46]	1840	1			T17	1		T26	1		T6	1
valid_sources[0x47]	850	1			T17	1		T26	1		T88	4
valid_sources[0x48]	772	1			T17	1		T26	1		T87	5
valid_sources[0x49]	900	1			T14	4		T17	1		T87	4
valid_sources[0x4a]	989	1			T17	1		T26	1		T87	8
valid_sources[0x4b]	936	1			T17	2		T11	1		T66	2
valid_sources[0x4c]	968	1			T17	2		T70	2		T205	45
valid_sources[0x4d]	1054	1			T17	1		T64	2		T87	1
valid_sources[0x4e]	951	1			T17	1		T26	3		T87	1
valid_sources[0x4f]	849	1			T14	2		T87	3		T10	1
valid_sources[0x50]	819	1			T14	1		T17	1		T26	2
valid_sources[0x51]	1215	1			T88	3		T66	3		T89	122
valid_sources[0x52]	820	1			T14	1		T87	2		T11	1
valid_sources[0x53]	1688	1			T2	1		T16	1		T26	1
valid_sources[0x54]	862	1			T18	1		T10	1		T103	4
valid_sources[0x55]	1116	1			T4	5		T17	1		T87	3
valid_sources[0x56]	770	1			T17	2		T86	9		T103	1
valid_sources[0x57]	799	1			T87	2		T20	2		T289	1
valid_sources[0x58]	1094	1			T14	4		T17	1		T18	3
valid_sources[0x59]	1419	1			T90	2		T20	6		T69	1
valid_sources[0x5a]	1072	1			T17	2		T26	2		T86	18
valid_sources[0x5b]	774	1			T20	1		T69	1		T289	1
valid_sources[0x5c]	932	1			T16	1		T20	4		T82	3
valid_sources[0x5d]	972	1			T17	1		T103	5		T20	7
valid_sources[0x5e]	942	1			T16	1		T17	4		T26	1
valid_sources[0x5f]	856	1			T87	2		T11	1		T20	7
valid_sources[0x60]	882	1			T26	1		T87	1		T103	32
valid_sources[0x61]	1022	1			T17	1		T25	13		T87	4
valid_sources[0x62]	878	1			T17	1		T86	1		T88	1
valid_sources[0x63]	1075	1			T4	2		T15	5		T17	1
valid_sources[0x64]	930	1			T17	1		T184	2		T28	1
valid_sources[0x65]	848	1			T17	2		T26	2		T20	6
valid_sources[0x66]	898	1			T4	1		T17	2		T20	4
valid_sources[0x67]	1028	1			T64	1		T87	1		T20	3
valid_sources[0x68]	887	1			T87	2		T103	2		T20	5
valid_sources[0x69]	1012	1			T5	4		T17	2		T25	8
valid_sources[0x6a]	1347	1			T17	1		T20	3		T170	1
valid_sources[0x6b]	803	1			T17	2		T87	1		T27	1
valid_sources[0x6c]	879	1			T1	2		T2	1		T17	1
valid_sources[0x6d]	908	1			T5	3		T14	2		T17	1
valid_sources[0x6e]	809	1			T16	1		T17	1		T26	4
valid_sources[0x6f]	941	1			T17	2		T26	1		T25	6
valid_sources[0x70]	1828	1			T17	1		T26	1		T86	3
valid_sources[0x71]	809	1			T26	1		T87	1		T103	1
valid_sources[0x72]	1074	1			T17	1		T26	1		T86	2
valid_sources[0x73]	866	1			T17	3		T26	1		T87	1
valid_sources[0x74]	1554	1			T14	2		T17	1		T26	1
valid_sources[0x75]	891	1			T14	1		T86	9		T87	3
valid_sources[0x76]	953	1			T75	2		T103	12		T20	6
valid_sources[0x77]	811	1			T5	2		T17	2		T26	1
valid_sources[0x78]	869	1			T14	1		T17	1		T26	1
valid_sources[0x79]	821	1			T9	1		T87	2		T20	1
valid_sources[0x7a]	919	1			T26	1		T75	1		T184	1
valid_sources[0x7b]	757	1			T17	1		T86	1		T20	1
valid_sources[0x7c]	1030	1			T17	1		T26	1		T88	4
valid_sources[0x7d]	1869	1			T17	1		T26	2		T64	2
valid_sources[0x7e]	826	1			T26	2		T87	3		T103	3
valid_sources[0x7f]	883	1			T17	1		T26	1		T87	3
valid_sources[0x80]	899	1			T17	1		T87	6		T20	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

62215

1

T1

3

T4

24

T5

12

values[0x0]

all_enables

biggest_size

29550

1

T1

2

T4

1

T5

7

values[0x1]

all_enables

biggest_size

21201

1

T1

2

T5

3

T2

1