Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	160705	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

126371

1

T1

7

T2

7

T4

10

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	146850	1			T1	4		T2	4		T4	8
values[0x0]	69695	1			T1	7		T2	5		T4	3
values[0x1]	70531	1			T1	2		T2	2		T4	5

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	130346	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

156730

1

T1

8

T2

7

T4

13

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1068	1			T11	5		T51	2		T85	2
valid_sources[0x01]	1028	1			T12	2		T81	2		T26	2
valid_sources[0x02]	1222	1			T22	4		T9	1		T10	1
valid_sources[0x03]	943	1			T23	3		T7	2		T26	2
valid_sources[0x04]	1013	1			T23	1		T26	1		T65	2
valid_sources[0x05]	927	1			T11	3		T84	1		T86	3
valid_sources[0x06]	933	1			T26	1		T11	1		T84	2
valid_sources[0x07]	1113	1			T4	4		T24	2		T11	9
valid_sources[0x08]	825	1			T23	2		T65	1		T82	1
valid_sources[0x09]	930	1			T3	1		T22	3		T82	1
valid_sources[0x0a]	948	1			T12	2		T26	1		T11	1
valid_sources[0x0b]	1272	1			T4	1		T10	1		T11	2
valid_sources[0x0c]	843	1			T11	6		T51	1		T87	3
valid_sources[0x0d]	1005	1			T27	2		T11	13		T60	2
valid_sources[0x0e]	1661	1			T65	1		T11	5		T84	1
valid_sources[0x0f]	1010	1			T11	13		T86	1		T32	3
valid_sources[0x10]	845	1			T65	5		T82	1		T11	10
valid_sources[0x11]	1870	1			T11	5		T51	1		T59	1
valid_sources[0x12]	924	1			T65	2		T11	7		T51	2
valid_sources[0x13]	1212	1			T10	1		T101	1		T11	6
valid_sources[0x14]	1051	1			T101	1		T11	2		T32	1
valid_sources[0x15]	824	1			T82	1		T11	7		T51	1
valid_sources[0x16]	1485	1			T26	3		T24	1		T11	1
valid_sources[0x17]	1615	1			T24	1		T11	8		T85	1
valid_sources[0x18]	948	1			T17	3		T26	1		T65	1
valid_sources[0x19]	986	1			T9	1		T11	7		T86	2
valid_sources[0x1a]	865	1			T23	1		T11	5		T32	4
valid_sources[0x1b]	948	1			T26	1		T67	1		T11	6
valid_sources[0x1c]	844	1			T27	2		T11	11		T51	1
valid_sources[0x1d]	1278	1			T11	2		T32	5		T160	5
valid_sources[0x1e]	1111	1			T23	2		T26	2		T11	6
valid_sources[0x1f]	1238	1			T23	2		T26	1		T65	1
valid_sources[0x20]	955	1			T58	1		T30	6		T40	3
valid_sources[0x21]	963	1			T82	1		T11	3		T84	3
valid_sources[0x22]	968	1			T16	1		T26	1		T51	1
valid_sources[0x23]	934	1			T13	63		T11	2		T86	7
valid_sources[0x24]	1146	1			T11	2		T93	1		T85	4
valid_sources[0x25]	1249	1			T220	1		T11	7		T21	281
valid_sources[0x26]	1039	1			T31	10		T11	4		T51	1
valid_sources[0x27]	897	1			T82	2		T9	1		T32	6
valid_sources[0x28]	1251	1			T6	439		T29	6		T11	12
valid_sources[0x29]	1437	1			T11	6		T76	2		T32	3
valid_sources[0x2a]	1029	1			T11	4		T32	3		T30	2
valid_sources[0x2b]	1888	1			T82	1		T11	11		T95	4
valid_sources[0x2c]	970	1			T29	3		T82	1		T220	1
valid_sources[0x2d]	976	1			T9	1		T11	9		T51	2
valid_sources[0x2e]	918	1			T26	1		T11	2		T51	1
valid_sources[0x2f]	2030	1			T26	2		T11	3		T86	2
valid_sources[0x30]	840	1			T22	4		T11	5		T86	3
valid_sources[0x31]	1165	1			T11	10		T85	6		T49	1
valid_sources[0x32]	1867	1			T11	1		T84	2		T157	1
valid_sources[0x33]	1377	1			T11	3		T32	2		T30	2
valid_sources[0x34]	1007	1			T1	1		T3	1		T22	1
valid_sources[0x35]	1339	1			T82	1		T11	3		T49	1
valid_sources[0x36]	1037	1			T22	3		T24	1		T10	2
valid_sources[0x37]	855	1			T26	1		T220	1		T11	7
valid_sources[0x38]	1007	1			T65	1		T66	7		T9	1
valid_sources[0x39]	1992	1			T82	1		T11	5		T51	1
valid_sources[0x3a]	769	1			T26	1		T51	1		T32	4
valid_sources[0x3b]	867	1			T11	3		T32	3		T30	4
valid_sources[0x3c]	1942	1			T23	1		T26	2		T9	1
valid_sources[0x3d]	992	1			T26	3		T65	2		T82	1
valid_sources[0x3e]	926	1			T26	2		T82	2		T84	2
valid_sources[0x3f]	1175	1			T81	1		T26	1		T27	3
valid_sources[0x40]	1182	1			T82	1		T24	1		T32	3
valid_sources[0x41]	1333	1			T65	2		T82	3		T11	2
valid_sources[0x42]	1001	1			T82	1		T24	3		T9	1
valid_sources[0x43]	2096	1			T2	2		T11	7		T32	3
valid_sources[0x44]	1109	1			T82	4		T11	11		T51	2
valid_sources[0x45]	1214	1			T11	2		T58	1		T87	1
valid_sources[0x46]	941	1			T11	2		T95	4		T32	4
valid_sources[0x47]	803	1			T2	1		T11	2		T86	3
valid_sources[0x48]	1022	1			T26	2		T82	1		T11	1
valid_sources[0x49]	911	1			T26	2		T11	3		T86	2
valid_sources[0x4a]	1207	1			T68	5		T24	1		T11	2
valid_sources[0x4b]	1016	1			T26	1		T83	9		T11	1
valid_sources[0x4c]	998	1			T26	4		T11	1		T32	9
valid_sources[0x4d]	1790	1			T26	1		T11	1		T86	3
valid_sources[0x4e]	1071	1			T1	1		T22	3		T11	5
valid_sources[0x4f]	1271	1			T83	52		T11	3		T51	4
valid_sources[0x50]	897	1			T1	1		T23	3		T24	1
valid_sources[0x51]	957	1			T82	1		T11	3		T86	2
valid_sources[0x52]	1183	1			T4	2		T24	1		T11	1
valid_sources[0x53]	1023	1			T95	5		T84	1		T86	1
valid_sources[0x54]	1102	1			T12	2		T11	13		T132	4
valid_sources[0x55]	774	1			T26	1		T11	12		T32	1
valid_sources[0x56]	1161	1			T26	2		T28	11		T11	3
valid_sources[0x57]	947	1			T23	4		T26	2		T60	1
valid_sources[0x58]	1051	1			T26	1		T95	1		T84	1
valid_sources[0x59]	1704	1			T16	4		T26	2		T11	7
valid_sources[0x5a]	1557	1			T16	1		T23	2		T27	1
valid_sources[0x5b]	1159	1			T4	1		T3	2		T7	3
valid_sources[0x5c]	963	1			T23	1		T26	2		T11	6
valid_sources[0x5d]	872	1			T65	1		T11	5		T95	2
valid_sources[0x5e]	1802	1			T14	13		T11	7		T84	1
valid_sources[0x5f]	1026	1			T8	24		T10	1		T11	2
valid_sources[0x60]	975	1			T26	2		T11	5		T51	3
valid_sources[0x61]	1049	1			T69	1		T11	11		T84	1
valid_sources[0x62]	1017	1			T11	6		T51	2		T75	45
valid_sources[0x63]	966	1			T11	6		T32	6		T30	3
valid_sources[0x64]	1028	1			T11	1		T51	1		T86	2
valid_sources[0x65]	924	1			T11	3		T86	1		T32	4
valid_sources[0x66]	866	1			T26	2		T10	1		T95	2
valid_sources[0x67]	1100	1			T74	13		T101	1		T11	3
valid_sources[0x68]	1024	1			T11	5		T51	2		T32	1
valid_sources[0x69]	1322	1			T12	4		T26	1		T65	2
valid_sources[0x6a]	982	1			T11	7		T32	3		T30	4
valid_sources[0x6b]	1039	1			T11	3		T59	1		T32	2
valid_sources[0x6c]	921	1			T23	1		T26	3		T24	3
valid_sources[0x6d]	857	1			T26	1		T11	1		T51	1
valid_sources[0x6e]	1469	1			T28	5		T11	2		T51	3
valid_sources[0x6f]	1104	1			T26	1		T9	1		T11	6
valid_sources[0x70]	995	1			T24	1		T11	6		T58	1
valid_sources[0x71]	1002	1			T23	1		T65	1		T11	1
valid_sources[0x72]	892	1			T65	3		T220	1		T11	7
valid_sources[0x73]	1040	1			T23	1		T65	1		T82	1
valid_sources[0x74]	1073	1			T11	1		T51	2		T84	1
valid_sources[0x75]	1739	1			T83	43		T11	6		T76	1
valid_sources[0x76]	1020	1			T26	2		T82	1		T11	4
valid_sources[0x77]	1175	1			T26	1		T82	1		T11	16
valid_sources[0x78]	789	1			T11	3		T51	1		T32	3
valid_sources[0x79]	823	1			T11	6		T84	3		T32	1
valid_sources[0x7a]	861	1			T11	5		T85	2		T32	2
valid_sources[0x7b]	1061	1			T11	9		T32	6		T30	1
valid_sources[0x7c]	876	1			T2	1		T26	2		T10	1
valid_sources[0x7d]	1722	1			T23	1		T82	1		T28	11
valid_sources[0x7e]	1141	1			T22	4		T26	1		T83	13
valid_sources[0x7f]	1034	1			T26	2		T11	3		T51	1
valid_sources[0x80]	996	1			T23	2		T82	1		T11	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

68023

1

T1

3

T2

3

T4

5

values[0x0]

all_enables

biggest_size

34177

1

T1

4

T2

4

T4

3

values[0x1]

all_enables

biggest_size

24171

1

T4

2

T13

2

T16

1