Module Definition
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Module : tlul_rsp_intg_gen
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_reg.u_rsp_intg_gen 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_rsp_intg_gen

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_data_intg.u_tlul_data_integ_enc 100.00 100.00
gen_rsp_intg.u_rsp_gen 100.00 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : tlul_rsp_intg_gen
Line No.TotalCoveredPercent
TOTAL44100.00
ALWAYS4733100.00
CONT_ASSIGN5311100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
47 1 1
48 1 1
49 1 1
53 1 1


Assert Coverage for Module : tlul_rsp_intg_gen
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataWidthCheck_A 802 802 0 0
PayLoadWidthCheck 802 802 0 0


DataWidthCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 802 802 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T16 1 1 0 0
T42 1 1 0 0
T47 1 1 0 0
T70 1 1 0 0
T71 1 1 0 0

PayLoadWidthCheck
NameAttemptsReal SuccessesFailuresIncomplete
Total 802 802 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T16 1 1 0 0
T42 1 1 0 0
T47 1 1 0 0
T70 1 1 0 0
T71 1 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%