Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : sysrst_ctrl_csr_assert_fpv
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.sysrst_ctrl_csr_assert 100.00 100.00


Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.02 100.00 96.08 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Since this is the module's only instance, the coverage report is the same as for the module.
Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 36 36 100.00 36 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 36 36 100.00 36 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
TlulOOBAddrErr_A 1278357336 11600 0 0
auto_block_debounce_ctl_rd_A 1278357336 1662 0 0
auto_block_out_ctl_rd_A 1278357336 2519 0 0
com_det_ctl_0_rd_A 1278357336 4442 0 0
com_det_ctl_1_rd_A 1278357336 4606 0 0
com_det_ctl_2_rd_A 1278357336 4301 0 0
com_det_ctl_3_rd_A 1278357336 4355 0 0
com_out_ctl_0_rd_A 1278357336 4984 0 0
com_out_ctl_1_rd_A 1278357336 5108 0 0
com_out_ctl_2_rd_A 1278357336 4963 0 0
com_out_ctl_3_rd_A 1278357336 4920 0 0
com_pre_det_ctl_0_rd_A 1278357336 1289 0 0
com_pre_det_ctl_1_rd_A 1278357336 1339 0 0
com_pre_det_ctl_2_rd_A 1278357336 1326 0 0
com_pre_det_ctl_3_rd_A 1278357336 1370 0 0
com_pre_sel_ctl_0_rd_A 1278357336 5520 0 0
com_pre_sel_ctl_1_rd_A 1278357336 5178 0 0
com_pre_sel_ctl_2_rd_A 1278357336 4955 0 0
com_pre_sel_ctl_3_rd_A 1278357336 5360 0 0
com_sel_ctl_0_rd_A 1278357336 5493 0 0
com_sel_ctl_1_rd_A 1278357336 5137 0 0
com_sel_ctl_2_rd_A 1278357336 5314 0 0
com_sel_ctl_3_rd_A 1278357336 5256 0 0
ec_rst_ctl_rd_A 1278357336 2349 0 0
intr_enable_rd_A 1278357336 1969 0 0
key_intr_ctl_rd_A 1278357336 4405 0 0
key_intr_debounce_ctl_rd_A 1278357336 1298 0 0
key_invert_ctl_rd_A 1278357336 4443 0 0
pin_allowed_ctl_rd_A 1278357336 5035 0 0
pin_out_ctl_rd_A 1278357336 3722 0 0
pin_out_value_rd_A 1278357336 3605 0 0
regwen_rd_A 1278357336 1682 0 0
ulp_ac_debounce_ctl_rd_A 1278357336 1368 0 0
ulp_ctl_rd_A 1278357336 1530 0 0
ulp_lid_debounce_ctl_rd_A 1278357336 1397 0 0
ulp_pwrb_debounce_ctl_rd_A 1278357336 1535 0 0


TlulOOBAddrErr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1278357336 11600 0 0
T3 227326 0 0 0
T6 228052 0 0 0
T8 243794 0 0 0
T9 242589 0 0 0
T17 159909 4 0 0
T18 57201 0 0 0
T26 246037 0 0 0
T64 192966 0 0 0
T65 171158 0 0 0
T74 250973 0 0 0
T103 0 17 0 0
T144 0 9 0 0
T205 0 2 0 0
T287 0 15 0 0
T289 0 13 0 0
T290 0 3 0 0
T291 0 10 0 0
T292 0 11 0 0
T293 0 10 0 0

auto_block_debounce_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1278357336 1662 0 0
T3 227326 0 0 0
T6 228052 0 0 0
T8 243794 0 0 0
T9 242589 0 0 0
T17 159909 36 0 0
T18 57201 0 0 0
T26 246037 0 0 0
T27 0 15 0 0
T28 0 12 0 0
T59 0 11 0 0
T63 0 9 0 0
T64 192966 0 0 0
T65 171158 0 0 0
T74 250973 0 0 0
T141 0 10 0 0
T242 0 27 0 0
T290 0 13 0 0
T294 0 1 0 0
T295 0 20 0 0

auto_block_out_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1278357336 2519 0 0
T3 227326 0 0 0
T6 228052 0 0 0
T8 243794 0 0 0
T9 242589 0 0 0
T17 159909 21 0 0
T18 57201 0 0 0
T26 246037 0 0 0
T27 0 17 0 0
T28 0 2 0 0
T59 0 9 0 0
T63 0 20 0 0
T64 192966 0 0 0
T65 171158 0 0 0
T74 250973 0 0 0
T141 0 4 0 0
T242 0 28 0 0
T290 0 9 0 0
T294 0 10 0 0
T295 0 15 0 0

com_det_ctl_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1278357336 4442 0 0
T3 227326 0 0 0
T6 228052 0 0 0
T8 243794 0 0 0
T9 242589 0 0 0
T17 159909 16 0 0
T18 57201 0 0 0
T26 246037 0 0 0
T39 0 23 0 0
T41 0 41 0 0
T44 0 76 0 0
T64 192966 0 0 0
T65 171158 0 0 0
T74 250973 0 0 0
T95 0 23 0 0
T104 0 65 0 0
T234 0 68 0 0
T242 0 42 0 0
T290 0 13 0 0
T295 0 19 0 0

com_det_ctl_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1278357336 4606 0 0
T3 227326 0 0 0
T6 228052 0 0 0
T8 243794 0 0 0
T9 242589 0 0 0
T17 159909 28 0 0
T18 57201 0 0 0
T26 246037 0 0 0
T39 0 38 0 0
T41 0 18 0 0
T44 0 84 0 0
T64 192966 0 0 0
T65 171158 0 0 0
T74 250973 0 0 0
T95 0 21 0 0
T104 0 84 0 0
T234 0 74 0 0
T242 0 48 0 0
T290 0 12 0 0
T295 0 23 0 0

com_det_ctl_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1278357336 4301 0 0
T3 227326 0 0 0
T6 228052 0 0 0
T8 243794 0 0 0
T9 242589 0 0 0
T17 159909 18 0 0
T18 57201 0 0 0
T26 246037 0 0 0
T39 0 52 0 0
T41 0 31 0 0
T44 0 95 0 0
T64 192966 0 0 0
T65 171158 0 0 0
T74 250973 0 0 0
T95 0 22 0 0
T104 0 70 0 0
T234 0 59 0 0
T242 0 42 0 0
T251 0 39 0 0
T295 0 9 0 0

com_det_ctl_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1278357336 4355 0 0
T3 227326 0 0 0
T6 228052 0 0 0
T8 243794 0 0 0
T9 242589 0 0 0
T17 159909 23 0 0
T18 57201 0 0 0
T26 246037 0 0 0
T39 0 48 0 0
T41 0 35 0 0
T44 0 75 0 0
T64 192966 0 0 0
T65 171158 0 0 0
T74 250973 0 0 0
T95 0 16 0 0
T104 0 57 0 0
T234 0 81 0 0
T242 0 29 0 0
T290 0 11 0 0
T295 0 17 0 0

com_out_ctl_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1278357336 4984 0 0
T3 227326 0 0 0
T6 228052 0 0 0
T8 243794 0 0 0
T9 242589 0 0 0
T17 159909 18 0 0
T18 57201 0 0 0
T26 246037 0 0 0
T39 0 41 0 0
T41 0 35 0 0
T44 0 64 0 0
T64 192966 0 0 0
T65 171158 0 0 0
T74 250973 0 0 0
T95 0 30 0 0
T104 0 92 0 0
T234 0 59 0 0
T242 0 42 0 0
T290 0 12 0 0
T295 0 15 0 0

com_out_ctl_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1278357336 5108 0 0
T3 227326 0 0 0
T6 228052 0 0 0
T8 243794 0 0 0
T9 242589 0 0 0
T17 159909 16 0 0
T18 57201 0 0 0
T26 246037 0 0 0
T39 0 26 0 0
T41 0 41 0 0
T44 0 72 0 0
T64 192966 0 0 0
T65 171158 0 0 0
T74 250973 0 0 0
T95 0 40 0 0
T104 0 62 0 0
T234 0 58 0 0
T242 0 43 0 0
T290 0 10 0 0
T295 0 16 0 0

com_out_ctl_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1278357336 4963 0 0
T3 227326 0 0 0
T6 228052 0 0 0
T8 243794 0 0 0
T9 242589 0 0 0
T17 159909 21 0 0
T18 57201 0 0 0
T26 246037 0 0 0
T39 0 32 0 0
T41 0 36 0 0
T44 0 72 0 0
T64 192966 0 0 0
T65 171158 0 0 0
T74 250973 0 0 0
T95 0 7 0 0
T104 0 65 0 0
T234 0 62 0 0
T242 0 42 0 0
T290 0 14 0 0
T295 0 21 0 0

com_out_ctl_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1278357336 4920 0 0
T3 227326 0 0 0
T6 228052 0 0 0
T8 243794 0 0 0
T9 242589 0 0 0
T17 159909 21 0 0
T18 57201 0 0 0
T26 246037 0 0 0
T39 0 27 0 0
T41 0 33 0 0
T44 0 92 0 0
T64 192966 0 0 0
T65 171158 0 0 0
T74 250973 0 0 0
T95 0 24 0 0
T104 0 56 0 0
T234 0 44 0 0
T242 0 41 0 0
T290 0 8 0 0
T295 0 26 0 0

com_pre_det_ctl_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1278357336 1289 0 0
T3 227326 0 0 0
T6 228052 0 0 0
T8 243794 0 0 0
T9 242589 0 0 0
T17 159909 19 0 0
T18 57201 0 0 0
T26 246037 0 0 0
T36 0 10 0 0
T37 0 163 0 0
T64 192966 0 0 0
T65 171158 0 0 0
T74 250973 0 0 0
T141 0 18 0 0
T242 0 41 0 0
T290 0 17 0 0
T295 0 18 0 0
T296 0 20 0 0
T297 0 16 0 0
T298 0 10 0 0

com_pre_det_ctl_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1278357336 1339 0 0
T3 227326 0 0 0
T6 228052 0 0 0
T8 243794 0 0 0
T9 242589 0 0 0
T17 159909 19 0 0
T18 57201 0 0 0
T26 246037 0 0 0
T36 0 11 0 0
T37 0 196 0 0
T64 192966 0 0 0
T65 171158 0 0 0
T74 250973 0 0 0
T141 0 21 0 0
T242 0 43 0 0
T290 0 1 0 0
T295 0 25 0 0
T296 0 14 0 0
T297 0 14 0 0
T298 0 10 0 0

com_pre_det_ctl_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1278357336 1326 0 0
T3 227326 0 0 0
T6 228052 0 0 0
T8 243794 0 0 0
T9 242589 0 0 0
T17 159909 16 0 0
T18 57201 0 0 0
T26 246037 0 0 0
T36 0 20 0 0
T37 0 109 0 0
T64 192966 0 0 0
T65 171158 0 0 0
T74 250973 0 0 0
T141 0 16 0 0
T242 0 61 0 0
T290 0 8 0 0
T295 0 9 0 0
T296 0 26 0 0
T297 0 17 0 0
T298 0 11 0 0

com_pre_det_ctl_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1278357336 1370 0 0
T3 227326 0 0 0
T6 228052 0 0 0
T8 243794 0 0 0
T9 242589 0 0 0
T17 159909 17 0 0
T18 57201 0 0 0
T26 246037 0 0 0
T36 0 10 0 0
T37 0 137 0 0
T64 192966 0 0 0
T65 171158 0 0 0
T74 250973 0 0 0
T141 0 12 0 0
T242 0 38 0 0
T290 0 16 0 0
T295 0 27 0 0
T296 0 20 0 0
T297 0 35 0 0
T298 0 3 0 0

com_pre_sel_ctl_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1278357336 5520 0 0
T3 227326 0 0 0
T6 228052 0 0 0
T8 243794 0 0 0
T9 242589 0 0 0
T17 159909 18 0 0
T18 57201 0 0 0
T26 246037 0 0 0
T39 0 58 0 0
T41 0 46 0 0
T44 0 53 0 0
T64 192966 0 0 0
T65 171158 0 0 0
T74 250973 0 0 0
T95 0 31 0 0
T104 0 84 0 0
T234 0 85 0 0
T242 0 43 0 0
T290 0 8 0 0
T295 0 23 0 0

com_pre_sel_ctl_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1278357336 5178 0 0
T3 227326 0 0 0
T6 228052 0 0 0
T8 243794 0 0 0
T9 242589 0 0 0
T17 159909 17 0 0
T18 57201 0 0 0
T26 246037 0 0 0
T39 0 35 0 0
T41 0 30 0 0
T44 0 60 0 0
T64 192966 0 0 0
T65 171158 0 0 0
T74 250973 0 0 0
T95 0 20 0 0
T104 0 73 0 0
T234 0 92 0 0
T242 0 41 0 0
T290 0 11 0 0
T295 0 11 0 0

com_pre_sel_ctl_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1278357336 4955 0 0
T3 227326 0 0 0
T6 228052 0 0 0
T8 243794 0 0 0
T9 242589 0 0 0
T17 159909 26 0 0
T18 57201 0 0 0
T26 246037 0 0 0
T39 0 45 0 0
T41 0 22 0 0
T44 0 69 0 0
T64 192966 0 0 0
T65 171158 0 0 0
T74 250973 0 0 0
T95 0 29 0 0
T104 0 61 0 0
T234 0 63 0 0
T242 0 42 0 0
T290 0 20 0 0
T295 0 14 0 0

com_pre_sel_ctl_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1278357336 5360 0 0
T3 227326 0 0 0
T6 228052 0 0 0
T8 243794 0 0 0
T9 242589 0 0 0
T17 159909 20 0 0
T18 57201 0 0 0
T26 246037 0 0 0
T39 0 52 0 0
T41 0 20 0 0
T44 0 49 0 0
T64 192966 0 0 0
T65 171158 0 0 0
T74 250973 0 0 0
T95 0 16 0 0
T104 0 74 0 0
T234 0 86 0 0
T242 0 41 0 0
T290 0 18 0 0
T295 0 17 0 0

com_sel_ctl_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1278357336 5493 0 0
T3 227326 0 0 0
T6 228052 0 0 0
T8 243794 0 0 0
T9 242589 0 0 0
T17 159909 19 0 0
T18 57201 0 0 0
T26 246037 0 0 0
T39 0 42 0 0
T41 0 29 0 0
T44 0 69 0 0
T64 192966 0 0 0
T65 171158 0 0 0
T74 250973 0 0 0
T95 0 12 0 0
T104 0 58 0 0
T234 0 99 0 0
T242 0 21 0 0
T290 0 12 0 0
T295 0 13 0 0

com_sel_ctl_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1278357336 5137 0 0
T3 227326 0 0 0
T6 228052 0 0 0
T8 243794 0 0 0
T9 242589 0 0 0
T17 159909 13 0 0
T18 57201 0 0 0
T26 246037 0 0 0
T39 0 47 0 0
T41 0 17 0 0
T44 0 84 0 0
T64 192966 0 0 0
T65 171158 0 0 0
T74 250973 0 0 0
T95 0 14 0 0
T104 0 83 0 0
T234 0 70 0 0
T242 0 43 0 0
T290 0 1 0 0
T295 0 22 0 0

com_sel_ctl_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1278357336 5314 0 0
T3 227326 0 0 0
T6 228052 0 0 0
T8 243794 0 0 0
T9 242589 0 0 0
T17 159909 20 0 0
T18 57201 0 0 0
T26 246037 0 0 0
T39 0 34 0 0
T41 0 57 0 0
T44 0 70 0 0
T64 192966 0 0 0
T65 171158 0 0 0
T74 250973 0 0 0
T95 0 20 0 0
T104 0 60 0 0
T234 0 67 0 0
T242 0 30 0 0
T290 0 21 0 0
T295 0 22 0 0

com_sel_ctl_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1278357336 5256 0 0
T3 227326 0 0 0
T6 228052 0 0 0
T8 243794 0 0 0
T9 242589 0 0 0
T17 159909 13 0 0
T18 57201 0 0 0
T26 246037 0 0 0
T39 0 25 0 0
T41 0 34 0 0
T44 0 77 0 0
T64 192966 0 0 0
T65 171158 0 0 0
T74 250973 0 0 0
T95 0 29 0 0
T104 0 77 0 0
T234 0 93 0 0
T242 0 39 0 0
T290 0 14 0 0
T295 0 31 0 0

ec_rst_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1278357336 2349 0 0
T3 227326 0 0 0
T6 228052 0 0 0
T8 243794 0 0 0
T9 242589 0 0 0
T17 159909 21 0 0
T18 57201 0 0 0
T26 246037 0 0 0
T39 0 18 0 0
T44 0 27 0 0
T55 0 4 0 0
T64 192966 0 0 0
T65 171158 0 0 0
T74 250973 0 0 0
T102 0 8 0 0
T188 0 7 0 0
T242 0 52 0 0
T290 0 5 0 0
T295 0 22 0 0
T299 0 5 0 0

intr_enable_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1278357336 1969 0 0
T3 227326 0 0 0
T6 228052 0 0 0
T8 243794 0 0 0
T9 242589 0 0 0
T17 159909 20 0 0
T18 57201 0 0 0
T26 246037 0 0 0
T64 192966 0 0 0
T65 171158 0 0 0
T74 250973 0 0 0
T116 0 10 0 0
T141 0 48 0 0
T242 0 60 0 0
T266 0 6 0 0
T290 0 9 0 0
T295 0 36 0 0
T296 0 17 0 0
T297 0 15 0 0
T300 0 9 0 0

key_intr_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1278357336 4405 0 0
T3 227326 0 0 0
T6 228052 0 0 0
T8 243794 0 0 0
T9 242589 0 0 0
T11 0 3 0 0
T17 159909 19 0 0
T18 57201 0 0 0
T26 246037 0 0 0
T55 0 71 0 0
T64 192966 0 0 0
T65 171158 0 0 0
T74 250973 0 0 0
T141 0 10 0 0
T160 0 4 0 0
T242 0 45 0 0
T290 0 10 0 0
T295 0 22 0 0
T296 0 14 0 0
T301 0 4 0 0

key_intr_debounce_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1278357336 1298 0 0
T3 227326 0 0 0
T6 228052 0 0 0
T8 243794 0 0 0
T9 242589 0 0 0
T17 159909 18 0 0
T18 57201 0 0 0
T26 246037 0 0 0
T36 0 20 0 0
T37 0 167 0 0
T64 192966 0 0 0
T65 171158 0 0 0
T74 250973 0 0 0
T141 0 18 0 0
T242 0 43 0 0
T290 0 24 0 0
T295 0 17 0 0
T296 0 6 0 0
T297 0 17 0 0
T298 0 6 0 0

key_invert_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1278357336 4443 0 0
T2 215378 0 0 0
T3 227326 0 0 0
T5 235905 33 0 0
T13 202586 0 0 0
T14 128132 0 0 0
T15 173596 0 0 0
T16 337249 0 0 0
T17 159909 25 0 0
T18 57201 43 0 0
T26 246037 0 0 0
T82 0 61 0 0
T84 0 91 0 0
T141 0 68 0 0
T197 0 41 0 0
T242 0 52 0 0
T290 0 11 0 0
T295 0 20 0 0

pin_allowed_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1278357336 5035 0 0
T3 227326 0 0 0
T6 228052 0 0 0
T8 243794 0 0 0
T9 242589 0 0 0
T17 159909 31 0 0
T18 57201 0 0 0
T26 246037 0 0 0
T59 0 65 0 0
T64 192966 0 0 0
T65 171158 0 0 0
T74 250973 0 0 0
T89 0 34 0 0
T112 0 85 0 0
T141 0 103 0 0
T171 0 79 0 0
T242 0 36 0 0
T290 0 16 0 0
T295 0 36 0 0
T302 0 73 0 0

pin_out_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1278357336 3722 0 0
T3 227326 0 0 0
T6 228052 0 0 0
T8 243794 0 0 0
T9 242589 0 0 0
T17 159909 45 0 0
T18 57201 0 0 0
T26 246037 0 0 0
T59 0 73 0 0
T64 192966 0 0 0
T65 171158 0 0 0
T74 250973 0 0 0
T89 0 48 0 0
T112 0 73 0 0
T141 0 96 0 0
T171 0 70 0 0
T242 0 48 0 0
T290 0 7 0 0
T295 0 12 0 0
T302 0 58 0 0

pin_out_value_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1278357336 3605 0 0
T3 227326 0 0 0
T6 228052 0 0 0
T8 243794 0 0 0
T9 242589 0 0 0
T17 159909 37 0 0
T18 57201 0 0 0
T26 246037 0 0 0
T59 0 87 0 0
T64 192966 0 0 0
T65 171158 0 0 0
T74 250973 0 0 0
T89 0 28 0 0
T112 0 54 0 0
T141 0 91 0 0
T171 0 86 0 0
T242 0 14 0 0
T290 0 9 0 0
T295 0 19 0 0
T302 0 55 0 0

regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1278357336 1682 0 0
T3 227326 0 0 0
T6 228052 0 0 0
T8 243794 0 0 0
T9 242589 0 0 0
T17 159909 20 0 0
T18 57201 0 0 0
T26 246037 0 0 0
T36 0 23 0 0
T37 0 201 0 0
T64 192966 0 0 0
T65 171158 0 0 0
T74 250973 0 0 0
T141 0 7 0 0
T242 0 31 0 0
T290 0 3 0 0
T295 0 11 0 0
T296 0 32 0 0
T297 0 17 0 0
T298 0 19 0 0

ulp_ac_debounce_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1278357336 1368 0 0
T3 227326 0 0 0
T6 228052 0 0 0
T8 243794 0 0 0
T9 242589 0 0 0
T17 159909 22 0 0
T18 57201 0 0 0
T26 246037 0 0 0
T64 192966 0 0 0
T65 171158 0 0 0
T73 0 1 0 0
T74 250973 0 0 0
T121 0 7 0 0
T141 0 13 0 0
T242 0 24 0 0
T290 0 13 0 0
T295 0 16 0 0
T303 0 6 0 0
T304 0 9 0 0
T305 0 5 0 0

ulp_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1278357336 1530 0 0
T3 227326 0 0 0
T6 228052 0 0 0
T8 243794 0 0 0
T9 242589 0 0 0
T17 159909 20 0 0
T18 57201 0 0 0
T26 246037 0 0 0
T64 192966 0 0 0
T65 171158 0 0 0
T73 0 6 0 0
T74 250973 0 0 0
T121 0 9 0 0
T141 0 13 0 0
T242 0 43 0 0
T290 0 10 0 0
T295 0 15 0 0
T303 0 9 0 0
T304 0 4 0 0
T305 0 7 0 0

ulp_lid_debounce_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1278357336 1397 0 0
T3 227326 0 0 0
T6 228052 0 0 0
T8 243794 0 0 0
T9 242589 0 0 0
T17 159909 26 0 0
T18 57201 0 0 0
T26 246037 0 0 0
T64 192966 0 0 0
T65 171158 0 0 0
T73 0 6 0 0
T74 250973 0 0 0
T121 0 5 0 0
T141 0 20 0 0
T242 0 29 0 0
T290 0 6 0 0
T295 0 34 0 0
T296 0 16 0 0
T304 0 6 0 0
T306 0 17 0 0

ulp_pwrb_debounce_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1278357336 1535 0 0
T3 227326 0 0 0
T6 228052 0 0 0
T8 243794 0 0 0
T9 242589 0 0 0
T17 159909 20 0 0
T18 57201 0 0 0
T26 246037 0 0 0
T64 192966 0 0 0
T65 171158 0 0 0
T73 0 4 0 0
T74 250973 0 0 0
T121 0 4 0 0
T141 0 19 0 0
T242 0 36 0 0
T290 0 10 0 0
T295 0 39 0 0
T303 0 1 0 0
T304 0 5 0 0
T305 0 9 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%