Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.34	100.00	96.72	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1273447815	9727	0	0
auto_block_debounce_ctl_rd_A	1273447815	1865	0	0
auto_block_out_ctl_rd_A	1273447815	2314	0	0
com_det_ctl_0_rd_A	1273447815	3836	0	0
com_det_ctl_1_rd_A	1273447815	4138	0	0
com_det_ctl_2_rd_A	1273447815	4131	0	0
com_det_ctl_3_rd_A	1273447815	4031	0	0
com_out_ctl_0_rd_A	1273447815	4304	0	0
com_out_ctl_1_rd_A	1273447815	4232	0	0
com_out_ctl_2_rd_A	1273447815	4165	0	0
com_out_ctl_3_rd_A	1273447815	4357	0	0
com_pre_det_ctl_0_rd_A	1273447815	1606	0	0
com_pre_det_ctl_1_rd_A	1273447815	1650	0	0
com_pre_det_ctl_2_rd_A	1273447815	1510	0	0
com_pre_det_ctl_3_rd_A	1273447815	1651	0	0
com_pre_sel_ctl_0_rd_A	1273447815	4395	0	0
com_pre_sel_ctl_1_rd_A	1273447815	4547	0	0
com_pre_sel_ctl_2_rd_A	1273447815	4384	0	0
com_pre_sel_ctl_3_rd_A	1273447815	4287	0	0
com_sel_ctl_0_rd_A	1273447815	4347	0	0
com_sel_ctl_1_rd_A	1273447815	4232	0	0
com_sel_ctl_2_rd_A	1273447815	4382	0	0
com_sel_ctl_3_rd_A	1273447815	4239	0	0
ec_rst_ctl_rd_A	1273447815	2581	0	0
intr_enable_rd_A	1273447815	2357	0	0
key_intr_ctl_rd_A	1273447815	2810	0	0
key_intr_debounce_ctl_rd_A	1273447815	1585	0	0
key_invert_ctl_rd_A	1273447815	4186	0	0
pin_allowed_ctl_rd_A	1273447815	4100	0	0
pin_out_ctl_rd_A	1273447815	3352	0	0
pin_out_value_rd_A	1273447815	3665	0	0
regwen_rd_A	1273447815	1814	0	0
ulp_ac_debounce_ctl_rd_A	1273447815	1601	0	0
ulp_ctl_rd_A	1273447815	1695	0	0
ulp_lid_debounce_ctl_rd_A	1273447815	1579	0	0
ulp_pwrb_debounce_ctl_rd_A	1273447815	1861	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1273447815	9727	0	0
T1	99621	2	0	0
T2	48994	0	0	0
T7	57869	718	0	0
T8	193164	0	0	0
T9	0	43	0	0
T10	0	11	0	0
T13	0	5	0	0
T41	46426	329	0	0
T45	52732	0	0	0
T46	185059	0	0	0
T47	51706	2	0	0
T48	199056	1	0	0
T49	50948	0	0	0
T308	0	773	0	0
T321	0	5	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1273447815	1865	0	0
T5	101532	11	0	0
T9	59258	0	0	0
T10	424070	106	0	0
T11	120915	0	0	0
T12	483489	33	0	0
T13	406943	0	0	0
T14	0	292	0	0
T27	323743	172	0	0
T28	58750	0	0	0
T39	0	9	0	0
T56	385624	0	0	0
T307	0	72	0	0
T308	209499	10	0	0
T310	0	5	0	0
T322	0	133	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1273447815	2314	0	0
T1	99621	0	0	0
T2	48994	0	0	0
T3	481344	0	0	0
T4	470845	0	0	0
T5	101532	13	0	0
T10	0	244	0	0
T12	0	7	0	0
T14	0	385	0	0
T26	15042	0	0	0
T27	0	241	0	0
T41	46426	0	0	0
T47	51706	9	0	0
T48	199056	0	0	0
T49	50948	0	0	0
T56	0	3	0	0
T307	0	102	0	0
T308	0	14	0	0
T310	0	17	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1273447815	3836	0	0
T1	99621	0	0	0
T2	48994	0	0	0
T3	481344	0	0	0
T4	470845	0	0	0
T5	101532	3	0	0
T10	0	101	0	0
T12	0	12	0	0
T14	0	290	0	0
T26	15042	0	0	0
T27	0	183	0	0
T41	46426	0	0	0
T47	51706	7	0	0
T48	199056	0	0	0
T49	50948	0	0	0
T56	0	6	0	0
T307	0	30	0	0
T308	0	14	0	0
T310	0	14	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1273447815	4138	0	0
T1	99621	0	0	0
T2	48994	0	0	0
T3	481344	0	0	0
T4	470845	0	0	0
T5	101532	8	0	0
T10	0	74	0	0
T12	0	13	0	0
T14	0	369	0	0
T26	15042	0	0	0
T27	0	207	0	0
T41	46426	0	0	0
T47	51706	6	0	0
T48	199056	0	0	0
T49	50948	0	0	0
T56	0	2	0	0
T307	0	41	0	0
T308	0	25	0	0
T310	0	18	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1273447815	4131	0	0
T5	101532	3	0	0
T9	59258	0	0	0
T10	424070	69	0	0
T11	120915	0	0	0
T12	483489	35	0	0
T13	406943	0	0	0
T14	0	361	0	0
T27	323743	220	0	0
T28	58750	0	0	0
T56	385624	1	0	0
T307	0	11	0	0
T308	209499	14	0	0
T310	0	12	0	0
T322	0	152	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1273447815	4031	0	0
T5	101532	7	0	0
T9	59258	0	0	0
T10	424070	47	0	0
T11	120915	0	0	0
T12	483489	37	0	0
T13	406943	0	0	0
T14	0	301	0	0
T27	323743	213	0	0
T28	58750	0	0	0
T56	385624	1	0	0
T307	0	23	0	0
T308	209499	5	0	0
T310	0	6	0	0
T322	0	149	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1273447815	4304	0	0
T5	101532	10	0	0
T9	59258	0	0	0
T10	424070	164	0	0
T11	120915	0	0	0
T12	483489	29	0	0
T13	406943	0	0	0
T14	0	315	0	0
T27	323743	214	0	0
T28	58750	0	0	0
T39	0	2	0	0
T56	385624	4	0	0
T307	0	91	0	0
T308	209499	13	0	0
T322	0	156	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1273447815	4232	0	0
T5	101532	8	0	0
T9	59258	0	0	0
T10	424070	212	0	0
T11	120915	0	0	0
T12	483489	18	0	0
T13	406943	0	0	0
T14	0	305	0	0
T27	323743	227	0	0
T28	58750	0	0	0
T39	0	5	0	0
T56	385624	4	0	0
T307	0	76	0	0
T308	209499	14	0	0
T310	0	7	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1273447815	4165	0	0
T5	101532	8	0	0
T9	59258	0	0	0
T10	424070	211	0	0
T11	120915	0	0	0
T12	483489	49	0	0
T13	406943	0	0	0
T14	0	296	0	0
T27	323743	203	0	0
T28	58750	0	0	0
T39	0	5	0	0
T56	385624	4	0	0
T307	0	112	0	0
T308	209499	7	0	0
T310	0	5	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1273447815	4357	0	0
T5	101532	3	0	0
T9	59258	0	0	0
T10	424070	201	0	0
T11	120915	0	0	0
T12	483489	29	0	0
T13	406943	0	0	0
T14	0	318	0	0
T27	323743	202	0	0
T28	58750	0	0	0
T39	0	13	0	0
T56	385624	1	0	0
T307	0	76	0	0
T308	209499	14	0	0
T310	0	9	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1273447815	1606	0	0
T1	99621	0	0	0
T2	48994	0	0	0
T3	481344	0	0	0
T4	470845	0	0	0
T5	101532	7	0	0
T10	0	86	0	0
T12	0	11	0	0
T14	0	293	0	0
T26	15042	0	0	0
T27	0	241	0	0
T41	46426	0	0	0
T47	51706	2	0	0
T48	199056	0	0	0
T49	50948	0	0	0
T56	0	1	0	0
T307	0	42	0	0
T308	0	22	0	0
T310	0	2	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1273447815	1650	0	0
T5	101532	7	0	0
T9	59258	0	0	0
T10	424070	96	0	0
T11	120915	0	0	0
T12	483489	14	0	0
T13	406943	0	0	0
T14	0	332	0	0
T27	323743	217	0	0
T28	58750	0	0	0
T39	0	1	0	0
T56	385624	5	0	0
T307	0	28	0	0
T308	209499	13	0	0
T310	0	8	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1273447815	1510	0	0
T10	424070	81	0	0
T11	120915	0	0	0
T12	483489	5	0	0
T13	406943	0	0	0
T14	78803	293	0	0
T15	50485	0	0	0
T27	323743	201	0	0
T28	58750	0	0	0
T38	228376	0	0	0
T39	0	3	0	0
T307	0	30	0	0
T310	0	9	0	0
T321	203821	0	0	0
T322	0	164	0	0
T323	0	4	0	0
T324	0	8	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1273447815	1651	0	0
T5	101532	6	0	0
T9	59258	0	0	0
T10	424070	58	0	0
T11	120915	0	0	0
T12	483489	31	0	0
T13	406943	0	0	0
T14	0	320	0	0
T27	323743	193	0	0
T28	58750	0	0	0
T56	385624	8	0	0
T307	0	19	0	0
T308	209499	23	0	0
T310	0	1	0	0
T322	0	173	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1273447815	4395	0	0
T1	99621	0	0	0
T2	48994	0	0	0
T3	481344	0	0	0
T4	470845	0	0	0
T5	101532	20	0	0
T10	0	195	0	0
T12	0	27	0	0
T14	0	293	0	0
T26	15042	0	0	0
T27	0	262	0	0
T41	46426	0	0	0
T47	51706	5	0	0
T48	199056	0	0	0
T49	50948	0	0	0
T56	0	8	0	0
T307	0	132	0	0
T308	0	12	0	0
T310	0	9	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1273447815	4547	0	0
T1	99621	0	0	0
T2	48994	0	0	0
T3	481344	0	0	0
T4	470845	0	0	0
T5	101532	41	0	0
T10	0	268	0	0
T12	0	12	0	0
T14	0	335	0	0
T26	15042	0	0	0
T27	0	151	0	0
T39	0	6	0	0
T41	46426	0	0	0
T47	51706	6	0	0
T48	199056	0	0	0
T49	50948	0	0	0
T56	0	1	0	0
T307	0	112	0	0
T310	0	10	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1273447815	4384	0	0
T1	99621	0	0	0
T2	48994	0	0	0
T3	481344	0	0	0
T4	470845	0	0	0
T5	101532	2	0	0
T10	0	311	0	0
T12	0	42	0	0
T14	0	326	0	0
T26	15042	0	0	0
T27	0	210	0	0
T41	46426	0	0	0
T47	51706	1	0	0
T48	199056	0	0	0
T49	50948	0	0	0
T56	0	1	0	0
T307	0	119	0	0
T310	0	4	0	0
T322	0	149	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1273447815	4287	0	0
T1	99621	0	0	0
T2	48994	0	0	0
T3	481344	0	0	0
T4	470845	0	0	0
T5	101532	7	0	0
T10	0	267	0	0
T12	0	13	0	0
T14	0	310	0	0
T26	15042	0	0	0
T27	0	246	0	0
T41	46426	0	0	0
T47	51706	10	0	0
T48	199056	0	0	0
T49	50948	0	0	0
T56	0	1	0	0
T307	0	95	0	0
T308	0	13	0	0
T310	0	5	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1273447815	4347	0	0
T5	101532	8	0	0
T9	59258	0	0	0
T10	424070	182	0	0
T11	120915	0	0	0
T12	483489	14	0	0
T13	406943	0	0	0
T14	0	303	0	0
T27	323743	210	0	0
T28	58750	0	0	0
T39	0	14	0	0
T56	385624	3	0	0
T307	0	165	0	0
T308	209499	10	0	0
T310	0	3	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1273447815	4232	0	0
T5	101532	15	0	0
T9	59258	0	0	0
T10	424070	217	0	0
T11	120915	0	0	0
T12	483489	0	0	0
T13	406943	0	0	0
T14	0	330	0	0
T27	323743	189	0	0
T28	58750	0	0	0
T39	0	13	0	0
T56	385624	6	0	0
T307	0	63	0	0
T308	209499	8	0	0
T310	0	4	0	0
T322	0	154	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1273447815	4382	0	0
T1	99621	0	0	0
T2	48994	0	0	0
T3	481344	0	0	0
T4	470845	0	0	0
T5	101532	24	0	0
T10	0	275	0	0
T12	0	22	0	0
T14	0	296	0	0
T26	15042	0	0	0
T27	0	227	0	0
T41	46426	0	0	0
T47	51706	7	0	0
T48	199056	0	0	0
T49	50948	0	0	0
T56	0	6	0	0
T307	0	78	0	0
T308	0	17	0	0
T310	0	27	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1273447815	4239	0	0
T5	101532	26	0	0
T9	59258	0	0	0
T10	424070	257	0	0
T11	120915	0	0	0
T12	483489	21	0	0
T13	406943	0	0	0
T14	0	296	0	0
T27	323743	195	0	0
T28	58750	0	0	0
T39	0	11	0	0
T56	385624	0	0	0
T307	0	96	0	0
T308	209499	14	0	0
T310	0	21	0	0
T322	0	171	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1273447815	2581	0	0
T1	99621	0	0	0
T2	48994	0	0	0
T3	481344	0	0	0
T4	470845	0	0	0
T5	101532	5	0	0
T10	0	79	0	0
T12	0	31	0	0
T14	0	293	0	0
T26	15042	0	0	0
T27	0	198	0	0
T39	0	8	0	0
T41	46426	0	0	0
T47	51706	2	0	0
T48	199056	0	0	0
T49	50948	0	0	0
T307	0	31	0	0
T308	0	6	0	0
T310	0	3	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1273447815	2357	0	0
T1	99621	0	0	0
T2	48994	0	0	0
T5	0	6	0	0
T6	58826	7	0	0
T7	57869	0	0	0
T8	193164	0	0	0
T10	0	94	0	0
T12	0	24	0	0
T14	0	312	0	0
T26	0	21	0	0
T27	0	247	0	0
T45	52732	0	0	0
T46	185059	0	0	0
T47	51706	0	0	0
T48	199056	0	0	0
T49	50948	0	0	0
T56	0	1	0	0
T307	0	46	0	0
T310	0	16	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1273447815	2810	0	0
T5	101532	62	0	0
T9	59258	0	0	0
T10	424070	688	0	0
T11	120915	0	0	0
T12	483489	19	0	0
T13	406943	0	0	0
T14	0	307	0	0
T27	323743	213	0	0
T28	58750	0	0	0
T56	385624	6	0	0
T307	0	220	0	0
T308	209499	4	0	0
T310	0	12	0	0
T322	0	148	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1273447815	1585	0	0
T1	99621	0	0	0
T2	48994	0	0	0
T3	481344	0	0	0
T4	470845	0	0	0
T5	101532	2	0	0
T10	0	98	0	0
T12	0	21	0	0
T14	0	291	0	0
T26	15042	0	0	0
T27	0	243	0	0
T41	46426	0	0	0
T47	51706	3	0	0
T48	199056	0	0	0
T49	50948	0	0	0
T56	0	5	0	0
T307	0	51	0	0
T308	0	6	0	0
T310	0	22	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1273447815	4186	0	0
T5	101532	27	0	0
T9	59258	0	0	0
T10	424070	510	0	0
T11	120915	0	0	0
T12	483489	29	0	0
T13	406943	0	0	0
T14	0	325	0	0
T27	323743	216	0	0
T28	58750	0	0	0
T39	0	23	0	0
T56	385624	9	0	0
T307	0	230	0	0
T308	209499	3	0	0
T310	0	26	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1273447815	4100	0	0
T5	101532	33	0	0
T9	59258	0	0	0
T10	424070	716	0	0
T11	120915	0	0	0
T12	483489	15	0	0
T13	406943	0	0	0
T14	0	344	0	0
T27	323743	235	0	0
T28	58750	0	0	0
T39	0	30	0	0
T56	385624	4	0	0
T307	0	327	0	0
T308	209499	4	0	0
T310	0	25	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1273447815	3352	0	0
T1	99621	0	0	0
T2	48994	0	0	0
T3	481344	0	0	0
T4	470845	0	0	0
T5	101532	46	0	0
T10	0	282	0	0
T12	0	7	0	0
T14	0	295	0	0
T26	15042	0	0	0
T27	0	213	0	0
T41	46426	0	0	0
T47	51706	1	0	0
T48	199056	0	0	0
T49	50948	0	0	0
T56	0	8	0	0
T307	0	160	0	0
T308	0	17	0	0
T310	0	11	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1273447815	3665	0	0
T1	99621	0	0	0
T2	48994	0	0	0
T3	481344	0	0	0
T4	470845	0	0	0
T5	101532	24	0	0
T10	0	389	0	0
T12	0	40	0	0
T14	0	329	0	0
T26	15042	0	0	0
T27	0	217	0	0
T41	46426	0	0	0
T47	51706	3	0	0
T48	199056	0	0	0
T49	50948	0	0	0
T56	0	3	0	0
T307	0	218	0	0
T308	0	1	0	0
T310	0	7	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1273447815	1814	0	0
T5	101532	14	0	0
T9	59258	0	0	0
T10	424070	94	0	0
T11	120915	0	0	0
T12	483489	16	0	0
T13	406943	0	0	0
T14	0	293	0	0
T27	323743	265	0	0
T28	58750	0	0	0
T56	385624	8	0	0
T307	0	23	0	0
T308	209499	12	0	0
T322	0	155	0	0
T325	0	7	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1273447815	1601	0	0
T5	101532	2	0	0
T9	59258	0	0	0
T10	424070	105	0	0
T11	120915	0	0	0
T12	483489	1	0	0
T13	406943	0	0	0
T14	0	291	0	0
T27	323743	236	0	0
T28	58750	0	0	0
T39	0	10	0	0
T56	385624	0	0	0
T307	0	22	0	0
T308	209499	5	0	0
T310	0	3	0	0
T322	0	178	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1273447815	1695	0	0
T10	424070	104	0	0
T11	120915	0	0	0
T12	483489	32	0	0
T13	406943	0	0	0
T14	78803	291	0	0
T15	50485	0	0	0
T27	323743	212	0	0
T28	58750	0	0	0
T38	228376	0	0	0
T56	385624	3	0	0
T307	0	26	0	0
T310	0	19	0	0
T322	0	159	0	0
T323	0	7	0	0
T325	0	8	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1273447815	1579	0	0
T1	99621	0	0	0
T2	48994	0	0	0
T3	481344	0	0	0
T4	470845	0	0	0
T5	101532	1	0	0
T10	0	79	0	0
T12	0	20	0	0
T14	0	299	0	0
T26	15042	0	0	0
T27	0	212	0	0
T41	46426	0	0	0
T47	51706	3	0	0
T48	199056	0	0	0
T49	50948	0	0	0
T56	0	5	0	0
T307	0	27	0	0
T308	0	6	0	0
T310	0	1	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1273447815	1861	0	0
T1	99621	0	0	0
T2	48994	0	0	0
T3	481344	0	0	0
T4	470845	0	0	0
T5	101532	7	0	0
T10	0	67	0	0
T12	0	36	0	0
T14	0	308	0	0
T26	15042	0	0	0
T27	0	208	0	0
T41	46426	0	0	0
T47	51706	7	0	0
T48	199056	0	0	0
T49	50948	0	0	0
T56	0	2	0	0
T307	0	33	0	0
T308	0	4	0	0
T310	0	16	0	0