Module Definition
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Module : sysrst_ctrl_csr_assert_fpv
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.sysrst_ctrl_csr_assert 100.00 100.00


Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.02 100.00 96.08 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Since this is the module's only instance, the coverage report is the same as for the module.
Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 36 36 100.00 36 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 36 36 100.00 36 100.00



Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
TlulOOBAddrErr_A 1332231489 11630 0 0
auto_block_debounce_ctl_rd_A 1332231489 1957 0 0
auto_block_out_ctl_rd_A 1332231489 2418 0 0
com_det_ctl_0_rd_A 1332231489 4024 0 0
com_det_ctl_1_rd_A 1332231489 4043 0 0
com_det_ctl_2_rd_A 1332231489 4137 0 0
com_det_ctl_3_rd_A 1332231489 4055 0 0
com_out_ctl_0_rd_A 1332231489 4391 0 0
com_out_ctl_1_rd_A 1332231489 4305 0 0
com_out_ctl_2_rd_A 1332231489 4492 0 0
com_out_ctl_3_rd_A 1332231489 4470 0 0
com_pre_det_ctl_0_rd_A 1332231489 1495 0 0
com_pre_det_ctl_1_rd_A 1332231489 1425 0 0
com_pre_det_ctl_2_rd_A 1332231489 1450 0 0
com_pre_det_ctl_3_rd_A 1332231489 1484 0 0
com_pre_sel_ctl_0_rd_A 1332231489 4659 0 0
com_pre_sel_ctl_1_rd_A 1332231489 4390 0 0
com_pre_sel_ctl_2_rd_A 1332231489 4521 0 0
com_pre_sel_ctl_3_rd_A 1332231489 4455 0 0
com_sel_ctl_0_rd_A 1332231489 4416 0 0
com_sel_ctl_1_rd_A 1332231489 4588 0 0
com_sel_ctl_2_rd_A 1332231489 4429 0 0
com_sel_ctl_3_rd_A 1332231489 4553 0 0
ec_rst_ctl_rd_A 1332231489 2538 0 0
intr_enable_rd_A 1332231489 2083 0 0
key_intr_ctl_rd_A 1332231489 3054 0 0
key_intr_debounce_ctl_rd_A 1332231489 1484 0 0
key_invert_ctl_rd_A 1332231489 4771 0 0
pin_allowed_ctl_rd_A 1332231489 6028 0 0
pin_out_ctl_rd_A 1332231489 4729 0 0
pin_out_value_rd_A 1332231489 4810 0 0
regwen_rd_A 1332231489 1468 0 0
ulp_ac_debounce_ctl_rd_A 1332231489 1679 0 0
ulp_ctl_rd_A 1332231489 1680 0 0
ulp_lid_debounce_ctl_rd_A 1332231489 1517 0 0
ulp_pwrb_debounce_ctl_rd_A 1332231489 1863 0 0


TlulOOBAddrErr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1332231489 11630 0 0
T30 213205 0 0 0
T32 251376 4 0 0
T39 112629 0 0 0
T53 147408 0 0 0
T54 0 8 0 0
T55 0 23 0 0
T72 655745 0 0 0
T100 0 5 0 0
T115 0 18 0 0
T129 0 10 0 0
T131 0 16 0 0
T159 60917 0 0 0
T160 62955 0 0 0
T161 160690 0 0 0
T167 51129 0 0 0
T178 0 4 0 0
T232 0 14 0 0
T248 100077 0 0 0
T357 0 16 0 0

auto_block_debounce_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1332231489 1957 0 0
T6 568425 0 0 0
T8 240611 0 0 0
T27 309902 10 0 0
T28 0 5 0 0
T29 52546 0 0 0
T54 0 6 0 0
T57 53142 0 0 0
T61 0 14 0 0
T65 251010 0 0 0
T66 48764 0 0 0
T67 53084 0 0 0
T68 393069 0 0 0
T69 21542 0 0 0
T156 0 17 0 0
T243 0 16 0 0
T253 0 7 0 0
T358 0 15 0 0
T359 0 13 0 0
T360 0 5 0 0

auto_block_out_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1332231489 2418 0 0
T6 568425 0 0 0
T8 240611 0 0 0
T27 309902 5 0 0
T29 52546 0 0 0
T54 0 9 0 0
T57 53142 0 0 0
T61 0 4 0 0
T65 251010 0 0 0
T66 48764 0 0 0
T67 53084 0 0 0
T68 393069 0 0 0
T69 21542 0 0 0
T156 0 9 0 0
T211 0 4 0 0
T232 0 63 0 0
T243 0 15 0 0
T358 0 10 0 0
T359 0 10 0 0
T360 0 8 0 0

com_det_ctl_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1332231489 4024 0 0
T11 750449 51 0 0
T41 0 44 0 0
T42 0 36 0 0
T51 103734 0 0 0
T54 0 11 0 0
T58 342709 0 0 0
T59 68785 0 0 0
T60 46454 0 0 0
T75 243533 0 0 0
T84 63404 0 0 0
T93 51059 0 0 0
T94 844352 0 0 0
T95 53819 0 0 0
T124 0 56 0 0
T193 0 18 0 0
T232 0 45 0 0
T361 0 53 0 0
T362 0 42 0 0
T363 0 71 0 0

com_det_ctl_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1332231489 4043 0 0
T11 750449 51 0 0
T41 0 42 0 0
T42 0 25 0 0
T51 103734 0 0 0
T54 0 9 0 0
T58 342709 0 0 0
T59 68785 0 0 0
T60 46454 0 0 0
T75 243533 0 0 0
T84 63404 0 0 0
T93 51059 0 0 0
T94 844352 0 0 0
T95 53819 0 0 0
T124 0 53 0 0
T193 0 24 0 0
T232 0 49 0 0
T361 0 57 0 0
T362 0 40 0 0
T363 0 73 0 0

com_det_ctl_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1332231489 4137 0 0
T11 750449 69 0 0
T41 0 54 0 0
T42 0 44 0 0
T51 103734 0 0 0
T54 0 16 0 0
T58 342709 0 0 0
T59 68785 0 0 0
T60 46454 0 0 0
T75 243533 0 0 0
T84 63404 0 0 0
T93 51059 0 0 0
T94 844352 0 0 0
T95 53819 0 0 0
T124 0 53 0 0
T193 0 8 0 0
T232 0 27 0 0
T361 0 71 0 0
T362 0 34 0 0
T363 0 82 0 0

com_det_ctl_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1332231489 4055 0 0
T11 750449 41 0 0
T41 0 30 0 0
T42 0 37 0 0
T51 103734 0 0 0
T58 342709 0 0 0
T59 68785 0 0 0
T60 46454 0 0 0
T75 243533 0 0 0
T84 63404 0 0 0
T93 51059 0 0 0
T94 844352 0 0 0
T95 53819 0 0 0
T124 0 49 0 0
T193 0 16 0 0
T199 0 81 0 0
T232 0 30 0 0
T361 0 75 0 0
T362 0 38 0 0
T363 0 53 0 0

com_out_ctl_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1332231489 4391 0 0
T11 750449 64 0 0
T41 0 59 0 0
T42 0 36 0 0
T51 103734 0 0 0
T54 0 16 0 0
T58 342709 0 0 0
T59 68785 0 0 0
T60 46454 0 0 0
T75 243533 0 0 0
T84 63404 0 0 0
T93 51059 0 0 0
T94 844352 0 0 0
T95 53819 0 0 0
T124 0 59 0 0
T193 0 23 0 0
T232 0 41 0 0
T361 0 69 0 0
T362 0 37 0 0
T363 0 61 0 0

com_out_ctl_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1332231489 4305 0 0
T11 750449 49 0 0
T41 0 33 0 0
T42 0 43 0 0
T51 103734 0 0 0
T54 0 8 0 0
T58 342709 0 0 0
T59 68785 0 0 0
T60 46454 0 0 0
T75 243533 0 0 0
T84 63404 0 0 0
T93 51059 0 0 0
T94 844352 0 0 0
T95 53819 0 0 0
T124 0 79 0 0
T193 0 17 0 0
T232 0 41 0 0
T361 0 83 0 0
T362 0 17 0 0
T363 0 70 0 0

com_out_ctl_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1332231489 4492 0 0
T11 750449 52 0 0
T41 0 43 0 0
T42 0 49 0 0
T51 103734 0 0 0
T54 0 17 0 0
T58 342709 0 0 0
T59 68785 0 0 0
T60 46454 0 0 0
T75 243533 0 0 0
T84 63404 0 0 0
T93 51059 0 0 0
T94 844352 0 0 0
T95 53819 0 0 0
T124 0 57 0 0
T193 0 30 0 0
T232 0 33 0 0
T361 0 81 0 0
T362 0 46 0 0
T363 0 86 0 0

com_out_ctl_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1332231489 4470 0 0
T11 750449 46 0 0
T41 0 43 0 0
T42 0 39 0 0
T51 103734 0 0 0
T54 0 10 0 0
T58 342709 0 0 0
T59 68785 0 0 0
T60 46454 0 0 0
T75 243533 0 0 0
T84 63404 0 0 0
T93 51059 0 0 0
T94 844352 0 0 0
T95 53819 0 0 0
T124 0 65 0 0
T193 0 11 0 0
T232 0 46 0 0
T361 0 59 0 0
T362 0 37 0 0
T363 0 65 0 0

com_pre_det_ctl_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1332231489 1495 0 0
T41 397556 0 0 0
T50 107026 0 0 0
T54 255599 2 0 0
T88 229364 0 0 0
T96 223132 0 0 0
T131 188523 0 0 0
T133 164224 0 0 0
T193 0 19 0 0
T204 0 6 0 0
T219 0 14 0 0
T226 222634 0 0 0
T227 248814 0 0 0
T228 188646 0 0 0
T232 0 33 0 0
T288 0 18 0 0
T364 0 21 0 0
T365 0 17 0 0
T366 0 8 0 0
T367 0 3 0 0

com_pre_det_ctl_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1332231489 1425 0 0
T41 397556 0 0 0
T50 107026 0 0 0
T54 255599 9 0 0
T88 229364 0 0 0
T96 223132 0 0 0
T131 188523 0 0 0
T133 164224 0 0 0
T193 0 13 0 0
T204 0 6 0 0
T206 0 7 0 0
T219 0 19 0 0
T226 222634 0 0 0
T227 248814 0 0 0
T228 188646 0 0 0
T232 0 29 0 0
T288 0 22 0 0
T364 0 15 0 0
T365 0 11 0 0
T366 0 13 0 0

com_pre_det_ctl_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1332231489 1450 0 0
T41 397556 0 0 0
T50 107026 0 0 0
T54 255599 8 0 0
T88 229364 0 0 0
T96 223132 0 0 0
T131 188523 0 0 0
T133 164224 0 0 0
T193 0 32 0 0
T204 0 12 0 0
T206 0 7 0 0
T219 0 21 0 0
T226 222634 0 0 0
T227 248814 0 0 0
T228 188646 0 0 0
T232 0 34 0 0
T288 0 7 0 0
T364 0 8 0 0
T365 0 24 0 0
T366 0 12 0 0

com_pre_det_ctl_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1332231489 1484 0 0
T41 397556 0 0 0
T50 107026 0 0 0
T54 255599 19 0 0
T88 229364 0 0 0
T96 223132 0 0 0
T131 188523 0 0 0
T133 164224 0 0 0
T193 0 8 0 0
T204 0 7 0 0
T206 0 7 0 0
T219 0 24 0 0
T226 222634 0 0 0
T227 248814 0 0 0
T228 188646 0 0 0
T232 0 25 0 0
T288 0 9 0 0
T364 0 20 0 0
T365 0 25 0 0
T366 0 11 0 0

com_pre_sel_ctl_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1332231489 4659 0 0
T11 750449 49 0 0
T41 0 42 0 0
T42 0 59 0 0
T51 103734 0 0 0
T54 0 16 0 0
T58 342709 0 0 0
T59 68785 0 0 0
T60 46454 0 0 0
T75 243533 0 0 0
T84 63404 0 0 0
T93 51059 0 0 0
T94 844352 0 0 0
T95 53819 0 0 0
T124 0 69 0 0
T193 0 16 0 0
T232 0 41 0 0
T361 0 63 0 0
T362 0 29 0 0
T363 0 81 0 0

com_pre_sel_ctl_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1332231489 4390 0 0
T11 750449 58 0 0
T41 0 59 0 0
T42 0 50 0 0
T51 103734 0 0 0
T54 0 6 0 0
T58 342709 0 0 0
T59 68785 0 0 0
T60 46454 0 0 0
T75 243533 0 0 0
T84 63404 0 0 0
T93 51059 0 0 0
T94 844352 0 0 0
T95 53819 0 0 0
T124 0 60 0 0
T193 0 8 0 0
T232 0 28 0 0
T361 0 60 0 0
T362 0 33 0 0
T363 0 86 0 0

com_pre_sel_ctl_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1332231489 4521 0 0
T11 750449 47 0 0
T41 0 30 0 0
T42 0 56 0 0
T51 103734 0 0 0
T54 0 12 0 0
T58 342709 0 0 0
T59 68785 0 0 0
T60 46454 0 0 0
T75 243533 0 0 0
T84 63404 0 0 0
T93 51059 0 0 0
T94 844352 0 0 0
T95 53819 0 0 0
T124 0 42 0 0
T193 0 9 0 0
T232 0 54 0 0
T361 0 74 0 0
T362 0 41 0 0
T363 0 91 0 0

com_pre_sel_ctl_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1332231489 4455 0 0
T11 750449 27 0 0
T41 0 50 0 0
T42 0 21 0 0
T51 103734 0 0 0
T54 0 17 0 0
T58 342709 0 0 0
T59 68785 0 0 0
T60 46454 0 0 0
T75 243533 0 0 0
T84 63404 0 0 0
T93 51059 0 0 0
T94 844352 0 0 0
T95 53819 0 0 0
T124 0 61 0 0
T193 0 5 0 0
T232 0 34 0 0
T361 0 66 0 0
T362 0 50 0 0
T363 0 44 0 0

com_sel_ctl_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1332231489 4416 0 0
T11 750449 33 0 0
T41 0 39 0 0
T42 0 39 0 0
T51 103734 0 0 0
T54 0 11 0 0
T58 342709 0 0 0
T59 68785 0 0 0
T60 46454 0 0 0
T75 243533 0 0 0
T84 63404 0 0 0
T93 51059 0 0 0
T94 844352 0 0 0
T95 53819 0 0 0
T124 0 56 0 0
T193 0 17 0 0
T232 0 43 0 0
T361 0 67 0 0
T362 0 28 0 0
T363 0 84 0 0

com_sel_ctl_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1332231489 4588 0 0
T11 750449 49 0 0
T41 0 45 0 0
T42 0 53 0 0
T51 103734 0 0 0
T54 0 18 0 0
T58 342709 0 0 0
T59 68785 0 0 0
T60 46454 0 0 0
T75 243533 0 0 0
T84 63404 0 0 0
T93 51059 0 0 0
T94 844352 0 0 0
T95 53819 0 0 0
T124 0 59 0 0
T193 0 33 0 0
T232 0 43 0 0
T361 0 81 0 0
T362 0 49 0 0
T363 0 84 0 0

com_sel_ctl_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1332231489 4429 0 0
T11 750449 64 0 0
T41 0 48 0 0
T42 0 39 0 0
T51 103734 0 0 0
T54 0 11 0 0
T58 342709 0 0 0
T59 68785 0 0 0
T60 46454 0 0 0
T75 243533 0 0 0
T84 63404 0 0 0
T93 51059 0 0 0
T94 844352 0 0 0
T95 53819 0 0 0
T124 0 65 0 0
T193 0 24 0 0
T232 0 40 0 0
T361 0 59 0 0
T362 0 34 0 0
T363 0 89 0 0

com_sel_ctl_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1332231489 4553 0 0
T11 750449 35 0 0
T41 0 45 0 0
T42 0 61 0 0
T51 103734 0 0 0
T54 0 11 0 0
T58 342709 0 0 0
T59 68785 0 0 0
T60 46454 0 0 0
T75 243533 0 0 0
T84 63404 0 0 0
T93 51059 0 0 0
T94 844352 0 0 0
T95 53819 0 0 0
T124 0 50 0 0
T193 0 9 0 0
T232 0 27 0 0
T361 0 88 0 0
T362 0 55 0 0
T363 0 75 0 0

ec_rst_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1332231489 2538 0 0
T3 215595 0 0 0
T7 60814 0 0 0
T11 0 53 0 0
T16 129820 1 0 0
T17 51227 0 0 0
T22 235908 0 0 0
T23 67247 0 0 0
T25 248822 0 0 0
T31 60611 0 0 0
T41 0 21 0 0
T42 0 15 0 0
T54 0 13 0 0
T74 104693 0 0 0
T81 101285 0 0 0
T124 0 34 0 0
T147 0 9 0 0
T151 0 4 0 0
T232 0 45 0 0
T368 0 4 0 0

intr_enable_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1332231489 2083 0 0
T10 129224 0 0 0
T11 750449 0 0 0
T28 665470 7 0 0
T51 103734 0 0 0
T54 0 17 0 0
T58 342709 0 0 0
T83 241118 0 0 0
T93 51059 0 0 0
T94 844352 0 0 0
T95 53819 0 0 0
T101 36845 0 0 0
T126 0 32 0 0
T193 0 20 0 0
T206 0 55 0 0
T219 0 40 0 0
T232 0 30 0 0
T360 0 27 0 0
T364 0 24 0 0
T369 0 14 0 0

key_intr_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1332231489 3054 0 0
T47 0 2 0 0
T49 0 2 0 0
T51 103734 4 0 0
T54 0 14 0 0
T58 342709 0 0 0
T59 68785 0 0 0
T60 46454 0 0 0
T75 243533 0 0 0
T84 63404 0 0 0
T93 51059 0 0 0
T94 844352 0 0 0
T95 53819 0 0 0
T117 0 11 0 0
T126 0 1 0 0
T132 233642 0 0 0
T193 0 18 0 0
T215 0 5 0 0
T232 0 54 0 0
T254 0 1 0 0

key_intr_debounce_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1332231489 1484 0 0
T41 397556 0 0 0
T50 107026 0 0 0
T54 255599 12 0 0
T88 229364 0 0 0
T96 223132 0 0 0
T131 188523 0 0 0
T133 164224 0 0 0
T193 0 22 0 0
T206 0 7 0 0
T219 0 8 0 0
T226 222634 0 0 0
T227 248814 0 0 0
T228 188646 0 0 0
T232 0 39 0 0
T288 0 3 0 0
T364 0 9 0 0
T365 0 24 0 0
T366 0 9 0 0
T367 0 16 0 0

key_invert_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1332231489 4771 0 0
T5 54551 0 0 0
T7 60814 0 0 0
T22 235908 92 0 0
T23 67247 0 0 0
T24 0 45 0 0
T25 248822 0 0 0
T26 250832 0 0 0
T27 309902 0 0 0
T31 60611 0 0 0
T54 0 89 0 0
T74 104693 0 0 0
T81 101285 0 0 0
T179 0 22 0 0
T232 0 115 0 0
T256 0 67 0 0
T310 0 35 0 0
T370 0 75 0 0
T371 0 79 0 0
T372 0 71 0 0

pin_allowed_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1332231489 6028 0 0
T51 103734 62 0 0
T54 0 208 0 0
T58 342709 0 0 0
T59 68785 0 0 0
T60 46454 0 0 0
T75 243533 0 0 0
T84 63404 82 0 0
T93 51059 0 0 0
T94 844352 0 0 0
T95 53819 0 0 0
T126 0 64 0 0
T132 233642 0 0 0
T159 0 39 0 0
T173 0 70 0 0
T307 0 52 0 0
T314 0 76 0 0
T317 0 62 0 0
T373 0 70 0 0

pin_out_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1332231489 4729 0 0
T51 103734 69 0 0
T54 0 209 0 0
T58 342709 0 0 0
T59 68785 0 0 0
T60 46454 0 0 0
T75 243533 0 0 0
T84 63404 60 0 0
T93 51059 0 0 0
T94 844352 0 0 0
T95 53819 0 0 0
T126 0 70 0 0
T132 233642 0 0 0
T159 0 57 0 0
T173 0 63 0 0
T307 0 52 0 0
T314 0 63 0 0
T317 0 68 0 0
T373 0 75 0 0

pin_out_value_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1332231489 4810 0 0
T51 103734 71 0 0
T54 0 216 0 0
T58 342709 0 0 0
T59 68785 0 0 0
T60 46454 0 0 0
T75 243533 0 0 0
T84 63404 73 0 0
T93 51059 0 0 0
T94 844352 0 0 0
T95 53819 0 0 0
T126 0 77 0 0
T132 233642 0 0 0
T159 0 15 0 0
T173 0 74 0 0
T307 0 74 0 0
T314 0 81 0 0
T317 0 58 0 0
T373 0 81 0 0

regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1332231489 1468 0 0
T41 397556 0 0 0
T50 107026 0 0 0
T54 255599 4 0 0
T88 229364 0 0 0
T96 223132 0 0 0
T131 188523 0 0 0
T133 164224 0 0 0
T193 0 14 0 0
T206 0 4 0 0
T219 0 17 0 0
T226 222634 0 0 0
T227 248814 0 0 0
T228 188646 0 0 0
T232 0 27 0 0
T288 0 22 0 0
T364 0 13 0 0
T365 0 23 0 0
T366 0 19 0 0
T367 0 8 0 0

ulp_ac_debounce_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1332231489 1679 0 0
T5 54551 5 0 0
T6 568425 0 0 0
T8 240611 0 0 0
T9 0 4 0 0
T26 250832 0 0 0
T27 309902 0 0 0
T29 52546 0 0 0
T54 0 18 0 0
T65 251010 0 0 0
T66 48764 0 0 0
T67 53084 0 0 0
T68 393069 0 0 0
T117 0 7 0 0
T165 0 12 0 0
T193 0 12 0 0
T232 0 38 0 0
T374 0 2 0 0
T375 0 5 0 0
T376 0 12 0 0

ulp_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1332231489 1680 0 0
T5 54551 2 0 0
T6 568425 0 0 0
T8 240611 0 0 0
T9 0 5 0 0
T26 250832 0 0 0
T27 309902 0 0 0
T29 52546 0 0 0
T54 0 14 0 0
T65 251010 0 0 0
T66 48764 0 0 0
T67 53084 0 0 0
T68 393069 0 0 0
T165 0 13 0 0
T193 0 20 0 0
T219 0 19 0 0
T232 0 31 0 0
T375 0 1 0 0
T376 0 9 0 0
T377 0 2 0 0

ulp_lid_debounce_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1332231489 1517 0 0
T5 54551 8 0 0
T6 568425 0 0 0
T8 240611 0 0 0
T9 0 3 0 0
T26 250832 0 0 0
T27 309902 0 0 0
T29 52546 0 0 0
T54 0 19 0 0
T65 251010 0 0 0
T66 48764 0 0 0
T67 53084 0 0 0
T68 393069 0 0 0
T117 0 1 0 0
T165 0 18 0 0
T193 0 17 0 0
T232 0 37 0 0
T375 0 3 0 0
T376 0 15 0 0
T377 0 4 0 0

ulp_pwrb_debounce_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1332231489 1863 0 0
T5 54551 1 0 0
T6 568425 0 0 0
T8 240611 0 0 0
T26 250832 0 0 0
T27 309902 0 0 0
T29 52546 0 0 0
T54 0 18 0 0
T65 251010 0 0 0
T66 48764 0 0 0
T67 53084 0 0 0
T68 393069 0 0 0
T117 0 1 0 0
T165 0 15 0 0
T193 0 12 0 0
T219 0 20 0 0
T232 0 53 0 0
T364 0 21 0 0
T376 0 4 0 0
T377 0 1 0 0