Module Definition
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Module : sysrst_ctrl_csr_assert_fpv
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.sysrst_ctrl_csr_assert 100.00 100.00



Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 28 28 100.00 28 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 28 28 100.00 28 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
TlulOOBAddrErr_A 269883870 10473 0 0
auto_block_debounce_ctl_rd_A 269883870 2453 0 0
auto_block_out_ctl_rd_A 269883870 3444 0 0
com_det_ctl_0_rd_A 269883870 2168 0 0
com_det_ctl_1_rd_A 269883870 2045 0 0
com_det_ctl_2_rd_A 269883870 2042 0 0
com_det_ctl_3_rd_A 269883870 2115 0 0
com_out_ctl_0_rd_A 269883870 2862 0 0
com_out_ctl_1_rd_A 269883870 2894 0 0
com_out_ctl_2_rd_A 269883870 2801 0 0
com_out_ctl_3_rd_A 269883870 2935 0 0
com_sel_ctl_0_rd_A 269883870 3031 0 0
com_sel_ctl_1_rd_A 269883870 3025 0 0
com_sel_ctl_2_rd_A 269883870 3089 0 0
com_sel_ctl_3_rd_A 269883870 3037 0 0
ec_rst_ctl_rd_A 269883870 2060 0 0
intr_enable_rd_A 269883870 3117 0 0
key_intr_ctl_rd_A 269883870 5248 0 0
key_intr_debounce_ctl_rd_A 269883870 2106 0 0
key_invert_ctl_rd_A 269883870 5554 0 0
pin_allowed_ctl_rd_A 269883870 6833 0 0
pin_out_ctl_rd_A 269883870 5807 0 0
pin_out_value_rd_A 269883870 5866 0 0
regwen_rd_A 269883870 2807 0 0
ulp_ac_debounce_ctl_rd_A 269883870 2170 0 0
ulp_ctl_rd_A 269883870 2217 0 0
ulp_lid_debounce_ctl_rd_A 269883870 2105 0 0
ulp_pwrb_debounce_ctl_rd_A 269883870 2178 0 0


TlulOOBAddrErr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 269883870 10473 0 0
T12 7026 420 0 0
T15 4776 2 0 0
T28 201954 17 0 0
T30 120725 12 0 0
T39 163633 10 0 0
T40 219738 18 0 0
T67 485885 24 0 0
T68 156485 20 0 0
T73 235642 28 0 0
T138 764791 7 0 0

auto_block_debounce_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 269883870 2453 0 0
T15 4776 6 0 0
T32 159807 13 0 0
T37 133554 6 0 0
T84 281477 3 0 0
T96 262620 72 0 0
T107 358945 16 0 0
T113 211085 17 0 0
T139 166926 14 0 0
T140 126517 8 0 0
T141 57607 16 0 0

auto_block_out_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 269883870 3444 0 0
T15 4776 7 0 0
T32 159807 7 0 0
T37 133554 12 0 0
T84 281477 13 0 0
T96 262620 43 0 0
T107 358945 9 0 0
T113 211085 5 0 0
T139 166926 6 0 0
T140 126517 7 0 0
T141 57607 3 0 0

com_det_ctl_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 269883870 2168 0 0
T4 318571 8 0 0
T15 4776 6 0 0
T36 163454 2 0 0
T82 53513 10 0 0
T84 281477 15 0 0
T96 262620 49 0 0
T113 211085 11 0 0
T116 154116 6 0 0
T131 668583 6 0 0
T142 111563 9 0 0

com_det_ctl_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 269883870 2045 0 0
T4 318571 2 0 0
T15 4776 5 0 0
T36 163454 9 0 0
T82 53513 8 0 0
T84 281477 20 0 0
T96 262620 42 0 0
T113 211085 11 0 0
T116 154116 12 0 0
T131 668583 7 0 0
T142 111563 8 0 0

com_det_ctl_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 269883870 2042 0 0
T4 318571 5 0 0
T15 4776 6 0 0
T36 163454 3 0 0
T82 53513 10 0 0
T84 281477 26 0 0
T96 262620 44 0 0
T113 211085 3 0 0
T116 154116 10 0 0
T131 668583 6 0 0
T142 111563 2 0 0

com_det_ctl_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 269883870 2115 0 0
T4 318571 9 0 0
T15 4776 1 0 0
T36 163454 1 0 0
T82 53513 7 0 0
T84 281477 19 0 0
T96 262620 35 0 0
T113 211085 6 0 0
T116 154116 7 0 0
T131 668583 3 0 0
T142 111563 7 0 0

com_out_ctl_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 269883870 2862 0 0
T4 318571 8 0 0
T15 4776 5 0 0
T36 163454 3 0 0
T82 53513 8 0 0
T84 281477 21 0 0
T96 262620 48 0 0
T113 211085 11 0 0
T116 154116 5 0 0
T131 668583 14 0 0
T142 111563 11 0 0

com_out_ctl_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 269883870 2894 0 0
T4 318571 7 0 0
T36 163454 7 0 0
T82 53513 7 0 0
T84 281477 15 0 0
T96 262620 53 0 0
T97 781953 3 0 0
T113 211085 9 0 0
T116 154116 5 0 0
T131 668583 6 0 0
T142 111563 4 0 0

com_out_ctl_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 269883870 2801 0 0
T4 318571 6 0 0
T15 4776 10 0 0
T36 163454 5 0 0
T82 53513 9 0 0
T84 281477 20 0 0
T96 262620 50 0 0
T113 211085 10 0 0
T116 154116 4 0 0
T131 668583 15 0 0
T142 111563 6 0 0

com_out_ctl_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 269883870 2935 0 0
T4 318571 2 0 0
T15 4776 3 0 0
T36 163454 4 0 0
T82 53513 15 0 0
T84 281477 11 0 0
T96 262620 39 0 0
T113 211085 4 0 0
T116 154116 6 0 0
T131 668583 4 0 0
T142 111563 7 0 0

com_sel_ctl_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 269883870 3031 0 0
T4 318571 6 0 0
T15 4776 4 0 0
T36 163454 4 0 0
T82 53513 7 0 0
T84 281477 23 0 0
T96 262620 29 0 0
T113 211085 14 0 0
T116 154116 9 0 0
T131 668583 4 0 0
T142 111563 12 0 0

com_sel_ctl_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 269883870 3025 0 0
T4 318571 8 0 0
T15 4776 8 0 0
T36 163454 15 0 0
T82 53513 11 0 0
T84 281477 9 0 0
T96 262620 38 0 0
T113 211085 14 0 0
T116 154116 13 0 0
T131 668583 7 0 0
T142 111563 2 0 0

com_sel_ctl_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 269883870 3089 0 0
T4 318571 11 0 0
T15 4776 5 0 0
T36 163454 3 0 0
T82 53513 12 0 0
T84 281477 19 0 0
T96 262620 47 0 0
T113 211085 4 0 0
T116 154116 10 0 0
T131 668583 2 0 0
T142 111563 11 0 0

com_sel_ctl_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 269883870 3037 0 0
T4 318571 18 0 0
T15 4776 8 0 0
T36 163454 18 0 0
T82 53513 8 0 0
T84 281477 23 0 0
T96 262620 52 0 0
T113 211085 10 0 0
T116 154116 1 0 0
T131 668583 4 0 0
T142 111563 5 0 0

ec_rst_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 269883870 2060 0 0
T15 4776 1 0 0
T84 281477 7 0 0
T96 262620 49 0 0
T113 211085 13 0 0
T143 312179 1 0 0
T144 216178 1 0 0
T145 196666 1 0 0
T146 146008 5 0 0
T147 247280 9 0 0
T148 446005 1 0 0

intr_enable_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 269883870 3117 0 0
T15 4776 1 0 0
T33 274849 7 0 0
T84 281477 34 0 0
T96 262620 41 0 0
T103 171782 28 0 0
T112 150736 13 0 0
T113 211085 46 0 0
T120 134743 57 0 0
T149 607812 11 0 0
T150 222178 15 0 0

key_intr_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 269883870 5248 0 0
T15 4776 6 0 0
T65 17311 7 0 0
T84 281477 4 0 0
T96 262620 25 0 0
T97 781953 10 0 0
T103 171782 4 0 0
T107 358945 5 0 0
T113 211085 9 0 0
T114 16562 9 0 0
T124 562649 9 0 0

key_intr_debounce_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 269883870 2106 0 0
T15 4776 9 0 0
T65 17311 6 0 0
T84 281477 6 0 0
T96 262620 27 0 0
T97 781953 7 0 0
T107 358945 6 0 0
T113 211085 15 0 0
T114 16562 2 0 0
T116 154116 3 0 0
T124 562649 1 0 0

key_invert_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 269883870 5554 0 0
T15 4776 9 0 0
T33 274849 64 0 0
T55 10414 69 0 0
T84 281477 68 0 0
T96 262620 91 0 0
T103 171782 57 0 0
T113 211085 71 0 0
T151 40809 66 0 0
T152 41273 51 0 0
T153 39896 53 0 0

pin_allowed_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 269883870 6833 0 0
T3 45683 63 0 0
T33 274849 56 0 0
T61 48017 49 0 0
T62 50548 59 0 0
T113 211085 7 0 0
T131 668583 89 0 0
T154 28727 87 0 0
T155 25631 66 0 0
T156 49583 84 0 0
T157 25737 67 0 0

pin_out_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 269883870 5807 0 0
T3 45683 55 0 0
T15 4776 9 0 0
T33 274849 62 0 0
T61 48017 57 0 0
T62 50548 100 0 0
T131 668583 70 0 0
T154 28727 73 0 0
T155 25631 39 0 0
T156 49583 82 0 0
T157 25737 88 0 0

pin_out_value_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 269883870 5866 0 0
T3 45683 73 0 0
T15 4776 10 0 0
T33 274849 51 0 0
T61 48017 70 0 0
T62 50548 78 0 0
T131 668583 65 0 0
T154 28727 82 0 0
T155 25631 74 0 0
T156 49583 73 0 0
T157 25737 87 0 0

regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 269883870 2807 0 0
T17 2587 5 0 0
T27 685686 16 0 0
T84 281477 12 0 0
T96 262620 49 0 0
T103 171782 1 0 0
T112 150736 9 0 0
T113 211085 8 0 0
T136 388286 79 0 0
T158 12609 17 0 0
T159 40187 263 0 0

ulp_ac_debounce_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 269883870 2170 0 0
T6 25841 7 0 0
T15 4776 5 0 0
T75 50916 18 0 0
T84 281477 28 0 0
T96 262620 28 0 0
T113 211085 16 0 0
T148 446005 13 0 0
T160 7052 3 0 0
T161 26443 2 0 0
T162 3748 1 0 0

ulp_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 269883870 2217 0 0
T6 25841 6 0 0
T15 4776 5 0 0
T75 50916 11 0 0
T84 281477 13 0 0
T96 262620 42 0 0
T113 211085 16 0 0
T148 446005 11 0 0
T161 26443 4 0 0
T163 3754 4 0 0
T164 53189 8 0 0

ulp_lid_debounce_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 269883870 2105 0 0
T6 25841 3 0 0
T15 4776 4 0 0
T75 50916 10 0 0
T84 281477 8 0 0
T96 262620 41 0 0
T103 171782 9 0 0
T113 211085 18 0 0
T148 446005 6 0 0
T161 26443 4 0 0
T162 3748 4 0 0

ulp_pwrb_debounce_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 269883870 2178 0 0
T6 25841 6 0 0
T15 4776 7 0 0
T75 50916 6 0 0
T84 281477 17 0 0
T96 262620 37 0 0
T103 171782 5 0 0
T113 211085 13 0 0
T148 446005 6 0 0
T160 7052 1 0 0
T162 3748 3 0 0

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