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Module Instance : tb.dut.u_reg.u_intr_state.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
50.00 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
50.00 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.24 85.71 100.00 100.00 u_intr_state


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_intr_enable.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_intr_enable


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_regwen.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_regwen


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_ec_rst_ctl.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_ec_rst_ctl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_ulp_ac_debounce_ctl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_ulp_lid_debounce_ctl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_ulp_pwrb_debounce_ctl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_ulp_ctl.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_ulp_ctl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_ulp_status.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_ulp_status


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_wkup_status.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_wkup_status


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_key_invert_ctl_key0_in.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_key_invert_ctl_key0_in


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_key_invert_ctl_key0_out.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_key_invert_ctl_key0_out


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_key_invert_ctl_key1_in.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_key_invert_ctl_key1_in


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_key_invert_ctl_key1_out.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_key_invert_ctl_key1_out


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_key_invert_ctl_key2_in.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_key_invert_ctl_key2_in


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_key_invert_ctl_key2_out.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_key_invert_ctl_key2_out


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_key_invert_ctl_pwrb_in.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_key_invert_ctl_pwrb_in


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_key_invert_ctl_pwrb_out.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_key_invert_ctl_pwrb_out


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_key_invert_ctl_ac_present.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_key_invert_ctl_ac_present


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_key_invert_ctl_bat_disable.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_key_invert_ctl_bat_disable


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_key_invert_ctl_lid_open.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_key_invert_ctl_lid_open


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_key_invert_ctl_z3_wakeup.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_key_invert_ctl_z3_wakeup


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_pin_allowed_ctl_bat_disable_0.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_pin_allowed_ctl_bat_disable_0


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_pin_allowed_ctl_ec_rst_l_0.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_pin_allowed_ctl_ec_rst_l_0


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_pin_allowed_ctl_pwrb_out_0.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_pin_allowed_ctl_pwrb_out_0


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_pin_allowed_ctl_key0_out_0.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_pin_allowed_ctl_key0_out_0


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Go back
Module Instances:
tb.dut.u_reg.u_intr_state.wr_en_data_arb
tb.dut.u_reg.u_intr_enable.wr_en_data_arb
tb.dut.u_reg.u_regwen.wr_en_data_arb
tb.dut.u_reg.u_ec_rst_ctl.wr_en_data_arb
tb.dut.u_reg.u_ulp_ac_debounce_ctl.wr_en_data_arb
tb.dut.u_reg.u_ulp_lid_debounce_ctl.wr_en_data_arb
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl.wr_en_data_arb
tb.dut.u_reg.u_ulp_ctl.wr_en_data_arb
tb.dut.u_reg.u_ulp_status.wr_en_data_arb
tb.dut.u_reg.u_wkup_status.wr_en_data_arb
tb.dut.u_reg.u_key_invert_ctl_key0_in.wr_en_data_arb
tb.dut.u_reg.u_key_invert_ctl_key0_out.wr_en_data_arb
tb.dut.u_reg.u_key_invert_ctl_key1_in.wr_en_data_arb
tb.dut.u_reg.u_key_invert_ctl_key1_out.wr_en_data_arb
tb.dut.u_reg.u_key_invert_ctl_key2_in.wr_en_data_arb
tb.dut.u_reg.u_key_invert_ctl_key2_out.wr_en_data_arb
tb.dut.u_reg.u_key_invert_ctl_pwrb_in.wr_en_data_arb
tb.dut.u_reg.u_key_invert_ctl_pwrb_out.wr_en_data_arb
tb.dut.u_reg.u_key_invert_ctl_ac_present.wr_en_data_arb
tb.dut.u_reg.u_key_invert_ctl_bat_disable.wr_en_data_arb
tb.dut.u_reg.u_key_invert_ctl_lid_open.wr_en_data_arb
tb.dut.u_reg.u_key_invert_ctl_z3_wakeup.wr_en_data_arb
tb.dut.u_reg.u_pin_allowed_ctl_bat_disable_0.wr_en_data_arb
tb.dut.u_reg.u_pin_allowed_ctl_ec_rst_l_0.wr_en_data_arb
tb.dut.u_reg.u_pin_allowed_ctl_pwrb_out_0.wr_en_data_arb
tb.dut.u_reg.u_pin_allowed_ctl_key0_out_0.wr_en_data_arb
Line Coverage for Instance : tb.dut.u_reg.u_intr_state.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL2150.00
CONT_ASSIGN43100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN5100
CONT_ASSIGN5200
CONT_ASSIGN5300


42                        end else if (SwAccess == SwAccessRO) begin : gen_ro
43         0/1     ==>      assign wr_en   = de;
44         1/1              assign wr_data = d;
           Tests:       T1 T4 T5 
45                          // Unused we, wd, q - Prevent lint errors.
46                          logic          unused_we;
47                          logic [DW-1:0] unused_wd;
48                          logic [DW-1:0] unused_q;
49                          //VCS coverage off
50                          // pragma coverage off
51         unreachable      assign unused_we = we;
52         unreachable      assign unused_wd = wd;
53         unreachable      assign unused_q  = q;
Line Coverage for Instance : tb.dut.u_reg.u_intr_enable.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900


32                        if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33         1/1              assign wr_en   = we | de;
           Tests:       T1 T4 T16 
34         1/1              assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
           Tests:       T1 T4 T5 
35                          // Unused q - Prevent lint errors.
36                          logic [DW-1:0] unused_q;
37                          //VCS coverage off
38                          // pragma coverage off
39         unreachable      assign unused_q = q;
Cond Coverage for Instance : tb.dut.u_reg.u_intr_enable.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T4,T5
01Unreachable
10CoveredT1,T4,T16 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT1,T4,T16 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT1,T4,T16
Branch Coverage for Instance : tb.dut.u_reg.u_intr_enable.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00 



34             assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
                                             -1-  
                                             ==>  
                                             ==>

Branches:
-1-StatusTests
1 Covered T1,T4,T16
0 Covered T1,T4,T5

Line Coverage for Instance : tb.dut.u_reg.u_regwen.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN13511100.00


112                       end else if (SwAccess == SwAccessW0C) begin : gen_w0c
113        1/1              assign wr_en   = we | de;
           Tests:       T33 T34 T35 
114                         if (Mubi) begin : gen_mubi
115                           if (DW == 4) begin : gen_mubi4
116                             assign wr_data = prim_mubi_pkg::mubi4_and_hi(prim_mubi_pkg::mubi4_t'(de ? d : q),
117                                                                          (we ? prim_mubi_pkg::mubi4_t'(wd) :
118                                                                                prim_mubi_pkg::MuBi4True));
119                           end else if (DW == 8) begin : gen_mubi8
120                             assign wr_data = prim_mubi_pkg::mubi8_and_hi(prim_mubi_pkg::mubi8_t'(de ? d : q),
121                                                                          (we ? prim_mubi_pkg::mubi8_t'(wd) :
122                                                                                prim_mubi_pkg::MuBi8True));
123                           end else if (DW == 12) begin : gen_mubi12
124                             assign wr_data = prim_mubi_pkg::mubi12_and_hi(prim_mubi_pkg::mubi12_t'(de ? d : q),
125                                                                           (we ? prim_mubi_pkg::mubi12_t'(wd) :
126                                                                                 prim_mubi_pkg::MuBi12True));
127                           end else if (DW == 16) begin : gen_mubi16
128                             assign wr_data = prim_mubi_pkg::mubi16_and_hi(prim_mubi_pkg::mubi16_t'(de ? d : q),
129                                                                           (we ? prim_mubi_pkg::mubi16_t'(wd) :
130                                                                                 prim_mubi_pkg::MuBi16True));
131                           end else begin : gen_invalid_mubi
132                             $error("%m: Invalid width for MuBi");
133                           end
134                         end else begin : gen_non_mubi
135        1/1                assign wr_data = (de ? d : q) & (we ? wd : '1);
           Tests:       T1 T4 T5 
Cond Coverage for Instance : tb.dut.u_reg.u_regwen.wr_en_data_arb
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       113
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T4,T5
01Unreachable
10CoveredT34,T35,T36 

 LINE       135
 EXPRESSION ((de ? d : q) & (we ? wd : '1))
             ------1-----   -------2------
-1--2-StatusTests
01CoveredT34,T37,T21
10CoveredT34,T37,T21
11CoveredT1,T4,T5 

 LINE       135
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT1,T4,T5
1Unreachable 

 LINE       135
 SUB-EXPRESSION (we ? wd : '1)
                 -1
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT34,T35,T36
Line Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900


32                        if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33         1/1              assign wr_en   = we | de;
           Tests:       T1 T2 T15 
34         1/1              assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
           Tests:       T1 T4 T5 
35                          // Unused q - Prevent lint errors.
36                          logic [DW-1:0] unused_q;
37                          //VCS coverage off
38                          // pragma coverage off
39         unreachable      assign unused_q = q;
Cond Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T4,T5
01Unreachable
10CoveredT1,T2,T15 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT1,T2,T15 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT1,T2,T15
Branch Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00 



34             assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
                                             -1-  
                                             ==>  
                                             ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T15
0 Covered T1,T4,T5

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900


32                        if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33         1/1              assign wr_en   = we | de;
           Tests:       T6 T12 T19 
34         1/1              assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
           Tests:       T1 T4 T5 
35                          // Unused q - Prevent lint errors.
36                          logic [DW-1:0] unused_q;
37                          //VCS coverage off
38                          // pragma coverage off
39         unreachable      assign unused_q = q;
Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T4,T5
01Unreachable
10CoveredT6,T12,T19 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT6,T12,T19 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT6,T12,T19
Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00 



34             assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
                                             -1-  
                                             ==>  
                                             ==>

Branches:
-1-StatusTests
1 Covered T6,T12,T19
0 Covered T1,T4,T5

Line Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900


32                        if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33         1/1              assign wr_en   = we | de;
           Tests:       T6 T12 T19 
34         1/1              assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
           Tests:       T1 T4 T5 
35                          // Unused q - Prevent lint errors.
36                          logic [DW-1:0] unused_q;
37                          //VCS coverage off
38                          // pragma coverage off
39         unreachable      assign unused_q = q;
Cond Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T4,T5
01Unreachable
10CoveredT6,T12,T19 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT6,T12,T19 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT6,T12,T19
Branch Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00 



34             assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
                                             -1-  
                                             ==>  
                                             ==>

Branches:
-1-StatusTests
1 Covered T6,T12,T19
0 Covered T1,T4,T5

Line Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900


32                        if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33         1/1              assign wr_en   = we | de;
           Tests:       T6 T12 T19 
34         1/1              assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
           Tests:       T1 T4 T5 
35                          // Unused q - Prevent lint errors.
36                          logic [DW-1:0] unused_q;
37                          //VCS coverage off
38                          // pragma coverage off
39         unreachable      assign unused_q = q;
Cond Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T4,T5
01Unreachable
10CoveredT6,T12,T19 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT6,T12,T19 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT6,T12,T19
Branch Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00 



34             assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
                                             -1-  
                                             ==>  
                                             ==>

Branches:
-1-StatusTests
1 Covered T6,T12,T19
0 Covered T1,T4,T5

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ctl.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900


32                        if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33         1/1              assign wr_en   = we | de;
           Tests:       T6 T12 T19 
34         1/1              assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
           Tests:       T1 T4 T5 
35                          // Unused q - Prevent lint errors.
36                          logic [DW-1:0] unused_q;
37                          //VCS coverage off
38                          // pragma coverage off
39         unreachable      assign unused_q = q;
Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ctl.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T4,T5
01Unreachable
10CoveredT6,T12,T19 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT6,T12,T19 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT6,T12,T19
Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ctl.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00 



34             assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
                                             -1-  
                                             ==>  
                                             ==>

Branches:
-1-StatusTests
1 Covered T6,T12,T19
0 Covered T1,T4,T5

Line Coverage for Instance : tb.dut.u_reg.u_ulp_status.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN11011100.00


87                          // If both try to set/clr at the same bit pos, SW wins.
88         1/1              assign wr_en   = we | de;
           Tests:       T1 T4 T5 
89                          if (Mubi) begin : gen_mubi
90                            if (DW == 4) begin : gen_mubi4
91                              assign wr_data = prim_mubi_pkg::mubi4_and_hi(prim_mubi_pkg::mubi4_t'(de ? d : q),
92                                                                           (we ? prim_mubi_pkg::mubi4_t'(~wd) :
93                                                                                 prim_mubi_pkg::MuBi4True));
94                            end else if (DW == 8) begin : gen_mubi8
95                              assign wr_data = prim_mubi_pkg::mubi8_and_hi(prim_mubi_pkg::mubi8_t'(de ? d : q),
96                                                                           (we ? prim_mubi_pkg::mubi8_t'(~wd) :
97                                                                                 prim_mubi_pkg::MuBi8True));
98                            end else if (DW == 12) begin : gen_mubi12
99                              assign wr_data = prim_mubi_pkg::mubi12_and_hi(prim_mubi_pkg::mubi12_t'(de ? d : q),
100                                                                           (we ? prim_mubi_pkg::mubi12_t'(~wd) :
101                                                                                 prim_mubi_pkg::MuBi12True));
102                           end else if (DW == 16) begin : gen_mubi16
103                             assign wr_data = prim_mubi_pkg::mubi16_and_hi(prim_mubi_pkg::mubi16_t'(de ? d : q),
104                                                                           (we ? prim_mubi_pkg::mubi16_t'(~wd) :
105                                                                                 prim_mubi_pkg::MuBi16True));
106                           end else begin : gen_invalid_mubi
107                             $error("%m: Invalid width for MuBi");
108                           end
109                         end else begin : gen_non_mubi
110        1/1                assign wr_data = (de ? d : q) & (we ? ~wd : '1);
           Tests:       T1 T4 T5 
Cond Coverage for Instance : tb.dut.u_reg.u_ulp_status.wr_en_data_arb
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       88
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T4,T5
01CoveredT6,T19,T38
10CoveredT6,T19,T38 

 LINE       110
 EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
             ------1-----   ---------2---------
-1--2-StatusTests
01CoveredT1,T4,T5
10CoveredT6,T19,T38
11CoveredT6,T19,T38 

 LINE       110
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT6,T19,T38 

 LINE       110
 SUB-EXPRESSION (we ? ((~wd)) : '1)
                 -1
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT6,T19,T38
Line Coverage for Instance : tb.dut.u_reg.u_wkup_status.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN11011100.00


87                          // If both try to set/clr at the same bit pos, SW wins.
88         1/1              assign wr_en   = we | de;
           Tests:       T1 T2 T3 
89                          if (Mubi) begin : gen_mubi
90                            if (DW == 4) begin : gen_mubi4
91                              assign wr_data = prim_mubi_pkg::mubi4_and_hi(prim_mubi_pkg::mubi4_t'(de ? d : q),
92                                                                           (we ? prim_mubi_pkg::mubi4_t'(~wd) :
93                                                                                 prim_mubi_pkg::MuBi4True));
94                            end else if (DW == 8) begin : gen_mubi8
95                              assign wr_data = prim_mubi_pkg::mubi8_and_hi(prim_mubi_pkg::mubi8_t'(de ? d : q),
96                                                                           (we ? prim_mubi_pkg::mubi8_t'(~wd) :
97                                                                                 prim_mubi_pkg::MuBi8True));
98                            end else if (DW == 12) begin : gen_mubi12
99                              assign wr_data = prim_mubi_pkg::mubi12_and_hi(prim_mubi_pkg::mubi12_t'(de ? d : q),
100                                                                           (we ? prim_mubi_pkg::mubi12_t'(~wd) :
101                                                                                 prim_mubi_pkg::MuBi12True));
102                           end else if (DW == 16) begin : gen_mubi16
103                             assign wr_data = prim_mubi_pkg::mubi16_and_hi(prim_mubi_pkg::mubi16_t'(de ? d : q),
104                                                                           (we ? prim_mubi_pkg::mubi16_t'(~wd) :
105                                                                                 prim_mubi_pkg::MuBi16True));
106                           end else begin : gen_invalid_mubi
107                             $error("%m: Invalid width for MuBi");
108                           end
109                         end else begin : gen_non_mubi
110        1/1                assign wr_data = (de ? d : q) & (we ? ~wd : '1);
           Tests:       T1 T4 T5 
Cond Coverage for Instance : tb.dut.u_reg.u_wkup_status.wr_en_data_arb
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       88
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T4,T5
01CoveredT1,T2,T3
10CoveredT6,T12,T20 

 LINE       110
 EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
             ------1-----   ---------2---------
-1--2-StatusTests
01CoveredT1,T4,T5
10CoveredT6,T20,T19
11CoveredT1,T2,T3 

 LINE       110
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT1,T2,T3 

 LINE       110
 SUB-EXPRESSION (we ? ((~wd)) : '1)
                 -1
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT6,T12,T20
Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_key0_in.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900


32                        if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33         1/1              assign wr_en   = we | de;
           Tests:       T5 T18 T25 
34         1/1              assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
           Tests:       T1 T4 T5 
35                          // Unused q - Prevent lint errors.
36                          logic [DW-1:0] unused_q;
37                          //VCS coverage off
38                          // pragma coverage off
39         unreachable      assign unused_q = q;
Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_key0_in.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T4,T5
01Unreachable
10CoveredT5,T18,T25 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT5,T18,T25 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT5,T18,T25
Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_key0_in.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00 



34             assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
                                             -1-  
                                             ==>  
                                             ==>

Branches:
-1-StatusTests
1 Covered T5,T18,T25
0 Covered T1,T4,T5

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_key0_out.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900


32                        if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33         1/1              assign wr_en   = we | de;
           Tests:       T5 T18 T25 
34         1/1              assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
           Tests:       T1 T4 T5 
35                          // Unused q - Prevent lint errors.
36                          logic [DW-1:0] unused_q;
37                          //VCS coverage off
38                          // pragma coverage off
39         unreachable      assign unused_q = q;
Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_key0_out.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T4,T5
01Unreachable
10CoveredT5,T18,T25 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT5,T18,T25 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT5,T18,T25
Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_key0_out.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00 



34             assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
                                             -1-  
                                             ==>  
                                             ==>

Branches:
-1-StatusTests
1 Covered T5,T18,T25
0 Covered T1,T4,T5

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_key1_in.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900


32                        if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33         1/1              assign wr_en   = we | de;
           Tests:       T5 T18 T25 
34         1/1              assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
           Tests:       T1 T4 T5 
35                          // Unused q - Prevent lint errors.
36                          logic [DW-1:0] unused_q;
37                          //VCS coverage off
38                          // pragma coverage off
39         unreachable      assign unused_q = q;
Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_key1_in.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T4,T5
01Unreachable
10CoveredT5,T18,T25 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT5,T18,T25 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT5,T18,T25
Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_key1_in.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00 



34             assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
                                             -1-  
                                             ==>  
                                             ==>

Branches:
-1-StatusTests
1 Covered T5,T18,T25
0 Covered T1,T4,T5

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_key1_out.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900


32                        if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33         1/1              assign wr_en   = we | de;
           Tests:       T5 T18 T25 
34         1/1              assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
           Tests:       T1 T4 T5 
35                          // Unused q - Prevent lint errors.
36                          logic [DW-1:0] unused_q;
37                          //VCS coverage off
38                          // pragma coverage off
39         unreachable      assign unused_q = q;
Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_key1_out.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T4,T5
01Unreachable
10CoveredT5,T18,T25 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT5,T18,T25 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT5,T18,T25
Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_key1_out.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00 



34             assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
                                             -1-  
                                             ==>  
                                             ==>

Branches:
-1-StatusTests
1 Covered T5,T18,T25
0 Covered T1,T4,T5

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_key2_in.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900


32                        if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33         1/1              assign wr_en   = we | de;
           Tests:       T5 T18 T25 
34         1/1              assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
           Tests:       T1 T4 T5 
35                          // Unused q - Prevent lint errors.
36                          logic [DW-1:0] unused_q;
37                          //VCS coverage off
38                          // pragma coverage off
39         unreachable      assign unused_q = q;
Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_key2_in.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T4,T5
01Unreachable
10CoveredT5,T18,T25 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT5,T18,T25 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT5,T18,T25
Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_key2_in.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00 



34             assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
                                             -1-  
                                             ==>  
                                             ==>

Branches:
-1-StatusTests
1 Covered T5,T18,T25
0 Covered T1,T4,T5

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_key2_out.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900


32                        if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33         1/1              assign wr_en   = we | de;
           Tests:       T5 T18 T25 
34         1/1              assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
           Tests:       T1 T4 T5 
35                          // Unused q - Prevent lint errors.
36                          logic [DW-1:0] unused_q;
37                          //VCS coverage off
38                          // pragma coverage off
39         unreachable      assign unused_q = q;
Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_key2_out.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T4,T5
01Unreachable
10CoveredT5,T18,T25 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT5,T18,T25 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT5,T18,T25
Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_key2_out.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00 



34             assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
                                             -1-  
                                             ==>  
                                             ==>

Branches:
-1-StatusTests
1 Covered T5,T18,T25
0 Covered T1,T4,T5

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_pwrb_in.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900


32                        if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33         1/1              assign wr_en   = we | de;
           Tests:       T5 T18 T25 
34         1/1              assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
           Tests:       T1 T4 T5 
35                          // Unused q - Prevent lint errors.
36                          logic [DW-1:0] unused_q;
37                          //VCS coverage off
38                          // pragma coverage off
39         unreachable      assign unused_q = q;
Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_pwrb_in.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T4,T5
01Unreachable
10CoveredT5,T18,T25 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT5,T18,T25 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT5,T18,T25
Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_pwrb_in.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00 



34             assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
                                             -1-  
                                             ==>  
                                             ==>

Branches:
-1-StatusTests
1 Covered T5,T18,T25
0 Covered T1,T4,T5

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_pwrb_out.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900


32                        if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33         1/1              assign wr_en   = we | de;
           Tests:       T5 T18 T25 
34         1/1              assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
           Tests:       T1 T4 T5 
35                          // Unused q - Prevent lint errors.
36                          logic [DW-1:0] unused_q;
37                          //VCS coverage off
38                          // pragma coverage off
39         unreachable      assign unused_q = q;
Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_pwrb_out.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T4,T5
01Unreachable
10CoveredT5,T18,T25 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT5,T18,T25 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT5,T18,T25
Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_pwrb_out.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00 



34             assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
                                             -1-  
                                             ==>  
                                             ==>

Branches:
-1-StatusTests
1 Covered T5,T18,T25
0 Covered T1,T4,T5

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_ac_present.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900


32                        if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33         1/1              assign wr_en   = we | de;
           Tests:       T5 T18 T25 
34         1/1              assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
           Tests:       T1 T4 T5 
35                          // Unused q - Prevent lint errors.
36                          logic [DW-1:0] unused_q;
37                          //VCS coverage off
38                          // pragma coverage off
39         unreachable      assign unused_q = q;
Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_ac_present.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T4,T5
01Unreachable
10CoveredT5,T18,T25 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT5,T18,T25 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT5,T18,T25
Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_ac_present.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00 



34             assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
                                             -1-  
                                             ==>  
                                             ==>

Branches:
-1-StatusTests
1 Covered T5,T18,T25
0 Covered T1,T4,T5

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_bat_disable.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900


32                        if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33         1/1              assign wr_en   = we | de;
           Tests:       T5 T18 T25 
34         1/1              assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
           Tests:       T1 T4 T5 
35                          // Unused q - Prevent lint errors.
36                          logic [DW-1:0] unused_q;
37                          //VCS coverage off
38                          // pragma coverage off
39         unreachable      assign unused_q = q;
Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_bat_disable.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T4,T5
01Unreachable
10CoveredT5,T18,T25 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT5,T18,T25 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT5,T18,T25
Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_bat_disable.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00 



34             assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
                                             -1-  
                                             ==>  
                                             ==>

Branches:
-1-StatusTests
1 Covered T5,T18,T25
0 Covered T1,T4,T5

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_lid_open.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900


32                        if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33         1/1              assign wr_en   = we | de;
           Tests:       T5 T18 T25 
34         1/1              assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
           Tests:       T1 T4 T5 
35                          // Unused q - Prevent lint errors.
36                          logic [DW-1:0] unused_q;
37                          //VCS coverage off
38                          // pragma coverage off
39         unreachable      assign unused_q = q;
Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_lid_open.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T4,T5
01Unreachable
10CoveredT5,T18,T25 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT5,T18,T25 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT5,T18,T25
Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_lid_open.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00 



34             assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
                                             -1-  
                                             ==>  
                                             ==>

Branches:
-1-StatusTests
1 Covered T5,T18,T25
0 Covered T1,T4,T5

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_z3_wakeup.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900


32                        if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33         1/1              assign wr_en   = we | de;
           Tests:       T5 T18 T25 
34         1/1              assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
           Tests:       T1 T4 T5 
35                          // Unused q - Prevent lint errors.
36                          logic [DW-1:0] unused_q;
37                          //VCS coverage off
38                          // pragma coverage off
39         unreachable      assign unused_q = q;
Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_z3_wakeup.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T4,T5
01Unreachable
10CoveredT5,T18,T25 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT5,T18,T25 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT5,T18,T25
Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_z3_wakeup.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00 



34             assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
                                             -1-  
                                             ==>  
                                             ==>

Branches:
-1-StatusTests
1 Covered T5,T18,T25
0 Covered T1,T4,T5

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_bat_disable_0.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900


32                        if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33         1/1              assign wr_en   = we | de;
           Tests:       T5 T14 T17 
34         1/1              assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
           Tests:       T1 T4 T5 
35                          // Unused q - Prevent lint errors.
36                          logic [DW-1:0] unused_q;
37                          //VCS coverage off
38                          // pragma coverage off
39         unreachable      assign unused_q = q;
Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_bat_disable_0.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T4,T5
01Unreachable
10CoveredT5,T14,T17 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT5,T14,T17 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT5,T14,T17
Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_bat_disable_0.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00 



34             assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
                                             -1-  
                                             ==>  
                                             ==>

Branches:
-1-StatusTests
1 Covered T5,T14,T17
0 Covered T1,T4,T5

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_ec_rst_l_0.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900


32                        if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33         1/1              assign wr_en   = we | de;
           Tests:       T5 T14 T17 
34         1/1              assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
           Tests:       T1 T4 T5 
35                          // Unused q - Prevent lint errors.
36                          logic [DW-1:0] unused_q;
37                          //VCS coverage off
38                          // pragma coverage off
39         unreachable      assign unused_q = q;
Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_ec_rst_l_0.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T4,T5
01Unreachable
10CoveredT5,T14,T17 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT5,T14,T17 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT5,T14,T17
Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_ec_rst_l_0.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00 



34             assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
                                             -1-  
                                             ==>  
                                             ==>

Branches:
-1-StatusTests
1 Covered T5,T14,T17
0 Covered T1,T4,T5

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_pwrb_out_0.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900


32                        if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33         1/1              assign wr_en   = we | de;
           Tests:       T5 T14 T17 
34         1/1              assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
           Tests:       T1 T4 T5 
35                          // Unused q - Prevent lint errors.
36                          logic [DW-1:0] unused_q;
37                          //VCS coverage off
38                          // pragma coverage off
39         unreachable      assign unused_q = q;
Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_pwrb_out_0.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T4,T5
01Unreachable
10CoveredT5,T14,T17 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT5,T14,T17 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT5,T14,T17
Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_pwrb_out_0.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00 



34             assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
                                             -1-  
                                             ==>  
                                             ==>

Branches:
-1-StatusTests
1 Covered T5,T14,T17
0 Covered T1,T4,T5

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_key0_out_0.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900


32                        if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33         1/1              assign wr_en   = we | de;
           Tests:       T5 T14 T17 
34         1/1              assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
           Tests:       T1 T4 T5 
35                          // Unused q - Prevent lint errors.
36                          logic [DW-1:0] unused_q;
37                          //VCS coverage off
38                          // pragma coverage off
39         unreachable      assign unused_q = q;
Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_key0_out_0.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T4,T5
01Unreachable
10CoveredT5,T14,T17 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT5,T14,T17 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT5,T14,T17
Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_key0_out_0.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00 



34             assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
                                             -1-  
                                             ==>  
                                             ==>

Branches:
-1-StatusTests
1 Covered T5,T14,T17
0 Covered T1,T4,T5

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%