Unified Coverage Report :: Module :: sysrst_ctrl_reg_top

Module : sysrst_ctrl_reg_top

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.62	100.00	94.48			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_reg_top.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg	98.62	100.00	94.46			100.00	100.00

---

Module Instance : tb.dut.u_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.62	100.00	94.46			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	99.42	96.19	100.00		98.84	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.34	100.00	96.72	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_alert_test	100.00	100.00
u_auto_block_debounce_ctl_auto_block_enable	100.00	100.00	100.00			100.00
u_auto_block_debounce_ctl_cdc	98.33	100.00	93.33			100.00	100.00
u_auto_block_debounce_ctl_debounce_timer	100.00	100.00	100.00			100.00
u_auto_block_out_ctl_cdc	99.17	100.00	96.67			100.00	100.00
u_auto_block_out_ctl_key0_out_sel	100.00	100.00	100.00			100.00
u_auto_block_out_ctl_key0_out_value	100.00	100.00	100.00			100.00
u_auto_block_out_ctl_key1_out_sel	100.00	100.00	100.00			100.00
u_auto_block_out_ctl_key1_out_value	100.00	100.00	100.00			100.00
u_auto_block_out_ctl_key2_out_sel	100.00	100.00	100.00			100.00
u_auto_block_out_ctl_key2_out_value	100.00	100.00	100.00			100.00
u_chk	100.00	100.00		100.00			100.00
u_com_det_ctl_0	100.00	100.00	100.00			100.00
u_com_det_ctl_0_cdc	99.17	100.00	96.67			100.00	100.00
u_com_det_ctl_1	100.00	100.00	100.00			100.00
u_com_det_ctl_1_cdc	99.17	100.00	96.67			100.00	100.00
u_com_det_ctl_2	100.00	100.00	100.00			100.00
u_com_det_ctl_2_cdc	99.17	100.00	96.67			100.00	100.00
u_com_det_ctl_3	100.00	100.00	100.00			100.00
u_com_det_ctl_3_cdc	99.17	100.00	96.67			100.00	100.00
u_com_out_ctl_0_bat_disable_0	100.00	100.00	100.00			100.00
u_com_out_ctl_0_cdc	99.17	100.00	96.67			100.00	100.00
u_com_out_ctl_0_ec_rst_0	100.00	100.00	100.00			100.00
u_com_out_ctl_0_interrupt_0	100.00	100.00	100.00			100.00
u_com_out_ctl_0_rst_req_0	100.00	100.00	100.00			100.00
u_com_out_ctl_1_bat_disable_1	100.00	100.00	100.00			100.00
u_com_out_ctl_1_cdc	99.17	100.00	96.67			100.00	100.00
u_com_out_ctl_1_ec_rst_1	100.00	100.00	100.00			100.00
u_com_out_ctl_1_interrupt_1	100.00	100.00	100.00			100.00
u_com_out_ctl_1_rst_req_1	100.00	100.00	100.00			100.00
u_com_out_ctl_2_bat_disable_2	100.00	100.00	100.00			100.00
u_com_out_ctl_2_cdc	99.17	100.00	96.67			100.00	100.00
u_com_out_ctl_2_ec_rst_2	100.00	100.00	100.00			100.00
u_com_out_ctl_2_interrupt_2	100.00	100.00	100.00			100.00
u_com_out_ctl_2_rst_req_2	100.00	100.00	100.00			100.00
u_com_out_ctl_3_bat_disable_3	100.00	100.00	100.00			100.00
u_com_out_ctl_3_cdc	99.17	100.00	96.67			100.00	100.00
u_com_out_ctl_3_ec_rst_3	100.00	100.00	100.00			100.00
u_com_out_ctl_3_interrupt_3	100.00	100.00	100.00			100.00
u_com_out_ctl_3_rst_req_3	100.00	100.00	100.00			100.00
u_com_pre_det_ctl_0	100.00	100.00	100.00			100.00
u_com_pre_det_ctl_0_cdc	99.17	100.00	96.67			100.00	100.00
u_com_pre_det_ctl_1	100.00	100.00	100.00			100.00
u_com_pre_det_ctl_1_cdc	99.17	100.00	96.67			100.00	100.00
u_com_pre_det_ctl_2	100.00	100.00	100.00			100.00
u_com_pre_det_ctl_2_cdc	99.17	100.00	96.67			100.00	100.00
u_com_pre_det_ctl_3	100.00	100.00	100.00			100.00
u_com_pre_det_ctl_3_cdc	99.17	100.00	96.67			100.00	100.00
u_com_pre_sel_ctl_0_ac_present_sel_0	100.00	100.00	100.00			100.00
u_com_pre_sel_ctl_0_cdc	99.17	100.00	96.67			100.00	100.00
u_com_pre_sel_ctl_0_key0_in_sel_0	100.00	100.00	100.00			100.00
u_com_pre_sel_ctl_0_key1_in_sel_0	100.00	100.00	100.00			100.00
u_com_pre_sel_ctl_0_key2_in_sel_0	100.00	100.00	100.00			100.00
u_com_pre_sel_ctl_0_pwrb_in_sel_0	100.00	100.00	100.00			100.00
u_com_pre_sel_ctl_1_ac_present_sel_1	100.00	100.00	100.00			100.00
u_com_pre_sel_ctl_1_cdc	99.17	100.00	96.67			100.00	100.00
u_com_pre_sel_ctl_1_key0_in_sel_1	100.00	100.00	100.00			100.00
u_com_pre_sel_ctl_1_key1_in_sel_1	100.00	100.00	100.00			100.00
u_com_pre_sel_ctl_1_key2_in_sel_1	100.00	100.00	100.00			100.00
u_com_pre_sel_ctl_1_pwrb_in_sel_1	100.00	100.00	100.00			100.00
u_com_pre_sel_ctl_2_ac_present_sel_2	100.00	100.00	100.00			100.00
u_com_pre_sel_ctl_2_cdc	99.17	100.00	96.67			100.00	100.00
u_com_pre_sel_ctl_2_key0_in_sel_2	100.00	100.00	100.00			100.00
u_com_pre_sel_ctl_2_key1_in_sel_2	100.00	100.00	100.00			100.00
u_com_pre_sel_ctl_2_key2_in_sel_2	100.00	100.00	100.00			100.00
u_com_pre_sel_ctl_2_pwrb_in_sel_2	100.00	100.00	100.00			100.00
u_com_pre_sel_ctl_3_ac_present_sel_3	100.00	100.00	100.00			100.00
u_com_pre_sel_ctl_3_cdc	99.17	100.00	96.67			100.00	100.00
u_com_pre_sel_ctl_3_key0_in_sel_3	100.00	100.00	100.00			100.00
u_com_pre_sel_ctl_3_key1_in_sel_3	100.00	100.00	100.00			100.00
u_com_pre_sel_ctl_3_key2_in_sel_3	100.00	100.00	100.00			100.00
u_com_pre_sel_ctl_3_pwrb_in_sel_3	100.00	100.00	100.00			100.00
u_com_sel_ctl_0_ac_present_sel_0	100.00	100.00	100.00			100.00
u_com_sel_ctl_0_cdc	99.17	100.00	96.67			100.00	100.00
u_com_sel_ctl_0_key0_in_sel_0	100.00	100.00	100.00			100.00
u_com_sel_ctl_0_key1_in_sel_0	100.00	100.00	100.00			100.00
u_com_sel_ctl_0_key2_in_sel_0	100.00	100.00	100.00			100.00
u_com_sel_ctl_0_pwrb_in_sel_0	100.00	100.00	100.00			100.00
u_com_sel_ctl_1_ac_present_sel_1	100.00	100.00	100.00			100.00
u_com_sel_ctl_1_cdc	99.17	100.00	96.67			100.00	100.00
u_com_sel_ctl_1_key0_in_sel_1	100.00	100.00	100.00			100.00
u_com_sel_ctl_1_key1_in_sel_1	100.00	100.00	100.00			100.00
u_com_sel_ctl_1_key2_in_sel_1	100.00	100.00	100.00			100.00
u_com_sel_ctl_1_pwrb_in_sel_1	100.00	100.00	100.00			100.00
u_com_sel_ctl_2_ac_present_sel_2	100.00	100.00	100.00			100.00
u_com_sel_ctl_2_cdc	99.17	100.00	96.67			100.00	100.00
u_com_sel_ctl_2_key0_in_sel_2	100.00	100.00	100.00			100.00
u_com_sel_ctl_2_key1_in_sel_2	100.00	100.00	100.00			100.00
u_com_sel_ctl_2_key2_in_sel_2	100.00	100.00	100.00			100.00
u_com_sel_ctl_2_pwrb_in_sel_2	100.00	100.00	100.00			100.00
u_com_sel_ctl_3_ac_present_sel_3	100.00	100.00	100.00			100.00
u_com_sel_ctl_3_cdc	99.17	100.00	96.67			100.00	100.00
u_com_sel_ctl_3_key0_in_sel_3	100.00	100.00	100.00			100.00
u_com_sel_ctl_3_key1_in_sel_3	100.00	100.00	100.00			100.00
u_com_sel_ctl_3_key2_in_sel_3	100.00	100.00	100.00			100.00
u_com_sel_ctl_3_pwrb_in_sel_3	100.00	100.00	100.00			100.00
u_combo_intr_status_cdc	96.06	100.00	85.92			98.31	100.00
u_combo_intr_status_combo0_h2l	100.00	100.00	100.00			100.00
u_combo_intr_status_combo1_h2l	100.00	100.00	100.00			100.00
u_combo_intr_status_combo2_h2l	100.00	100.00	100.00			100.00
u_combo_intr_status_combo3_h2l	100.00	100.00	100.00			100.00
u_ec_rst_ctl	100.00	100.00	100.00			100.00
u_ec_rst_ctl_cdc	98.33	100.00	93.33			100.00	100.00
u_intr_enable	100.00	100.00	100.00			100.00
u_intr_state	100.00	100.00	100.00			100.00
u_intr_test	100.00	100.00
u_key_intr_ctl_ac_present_h2l	100.00	100.00	100.00			100.00
u_key_intr_ctl_ac_present_l2h	100.00	100.00	100.00			100.00
u_key_intr_ctl_cdc	99.17	100.00	96.67			100.00	100.00
u_key_intr_ctl_ec_rst_l_h2l	100.00	100.00	100.00			100.00
u_key_intr_ctl_ec_rst_l_l2h	100.00	100.00	100.00			100.00
u_key_intr_ctl_flash_wp_l_h2l	100.00	100.00	100.00			100.00
u_key_intr_ctl_flash_wp_l_l2h	100.00	100.00	100.00			100.00
u_key_intr_ctl_key0_in_h2l	100.00	100.00	100.00			100.00
u_key_intr_ctl_key0_in_l2h	100.00	100.00	100.00			100.00
u_key_intr_ctl_key1_in_h2l	100.00	100.00	100.00			100.00
u_key_intr_ctl_key1_in_l2h	100.00	100.00	100.00			100.00
u_key_intr_ctl_key2_in_h2l	100.00	100.00	100.00			100.00
u_key_intr_ctl_key2_in_l2h	100.00	100.00	100.00			100.00
u_key_intr_ctl_pwrb_in_h2l	100.00	100.00	100.00			100.00
u_key_intr_ctl_pwrb_in_l2h	100.00	100.00	100.00			100.00
u_key_intr_debounce_ctl	100.00	100.00	100.00			100.00
u_key_intr_debounce_ctl_cdc	98.33	100.00	93.33			100.00	100.00
u_key_intr_status_ac_present_h2l	100.00	100.00	100.00			100.00
u_key_intr_status_ac_present_l2h	100.00	100.00	100.00			100.00
u_key_intr_status_cdc	96.06	100.00	85.92			98.31	100.00
u_key_intr_status_ec_rst_l_h2l	100.00	100.00	100.00			100.00
u_key_intr_status_ec_rst_l_l2h	100.00	100.00	100.00			100.00
u_key_intr_status_flash_wp_l_h2l	100.00	100.00	100.00			100.00
u_key_intr_status_flash_wp_l_l2h	100.00	100.00	100.00			100.00
u_key_intr_status_key0_in_h2l	100.00	100.00	100.00			100.00
u_key_intr_status_key0_in_l2h	100.00	100.00	100.00			100.00
u_key_intr_status_key1_in_h2l	100.00	100.00	100.00			100.00
u_key_intr_status_key1_in_l2h	100.00	100.00	100.00			100.00
u_key_intr_status_key2_in_h2l	100.00	100.00	100.00			100.00
u_key_intr_status_key2_in_l2h	100.00	100.00	100.00			100.00
u_key_intr_status_pwrb_h2l	100.00	100.00	100.00			100.00
u_key_intr_status_pwrb_l2h	100.00	100.00	100.00			100.00
u_key_invert_ctl_ac_present	100.00	100.00	100.00			100.00
u_key_invert_ctl_bat_disable	100.00	100.00	100.00			100.00
u_key_invert_ctl_cdc	99.17	100.00	96.67			100.00	100.00
u_key_invert_ctl_key0_in	100.00	100.00	100.00			100.00
u_key_invert_ctl_key0_out	100.00	100.00	100.00			100.00
u_key_invert_ctl_key1_in	100.00	100.00	100.00			100.00
u_key_invert_ctl_key1_out	100.00	100.00	100.00			100.00
u_key_invert_ctl_key2_in	100.00	100.00	100.00			100.00
u_key_invert_ctl_key2_out	100.00	100.00	100.00			100.00
u_key_invert_ctl_lid_open	100.00	100.00	100.00			100.00
u_key_invert_ctl_pwrb_in	100.00	100.00	100.00			100.00
u_key_invert_ctl_pwrb_out	100.00	100.00	100.00			100.00
u_key_invert_ctl_z3_wakeup	100.00	100.00	100.00			100.00
u_pin_allowed_ctl_bat_disable_0	100.00	100.00	100.00			100.00
u_pin_allowed_ctl_bat_disable_1	100.00	100.00	100.00			100.00
u_pin_allowed_ctl_cdc	99.17	100.00	96.67			100.00	100.00
u_pin_allowed_ctl_ec_rst_l_0	100.00	100.00	100.00			100.00
u_pin_allowed_ctl_ec_rst_l_1	100.00	100.00	100.00			100.00
u_pin_allowed_ctl_flash_wp_l_0	100.00	100.00	100.00			100.00
u_pin_allowed_ctl_flash_wp_l_1	100.00	100.00	100.00			100.00
u_pin_allowed_ctl_key0_out_0	100.00	100.00	100.00			100.00
u_pin_allowed_ctl_key0_out_1	100.00	100.00	100.00			100.00
u_pin_allowed_ctl_key1_out_0	100.00	100.00	100.00			100.00
u_pin_allowed_ctl_key1_out_1	100.00	100.00	100.00			100.00
u_pin_allowed_ctl_key2_out_0	100.00	100.00	100.00			100.00
u_pin_allowed_ctl_key2_out_1	100.00	100.00	100.00			100.00
u_pin_allowed_ctl_pwrb_out_0	100.00	100.00	100.00			100.00
u_pin_allowed_ctl_pwrb_out_1	100.00	100.00	100.00			100.00
u_pin_allowed_ctl_z3_wakeup_0	100.00	100.00	100.00			100.00
u_pin_allowed_ctl_z3_wakeup_1	100.00	100.00	100.00			100.00
u_pin_in_value_ac_present	63.33	80.00	50.00			60.00
u_pin_in_value_ec_rst_l	63.33	80.00	50.00			60.00
u_pin_in_value_flash_wp_l	63.33	80.00	50.00			60.00
u_pin_in_value_key0_in	63.33	80.00	50.00			60.00
u_pin_in_value_key1_in	63.33	80.00	50.00			60.00
u_pin_in_value_key2_in	63.33	80.00	50.00			60.00
u_pin_in_value_lid_open	63.33	80.00	50.00			60.00
u_pin_in_value_pwrb_in	63.33	80.00	50.00			60.00
u_pin_out_ctl_bat_disable	100.00	100.00	100.00			100.00
u_pin_out_ctl_cdc	99.17	100.00	96.67			100.00	100.00
u_pin_out_ctl_ec_rst_l	100.00	100.00	100.00			100.00
u_pin_out_ctl_flash_wp_l	100.00	100.00	100.00			100.00
u_pin_out_ctl_key0_out	100.00	100.00	100.00			100.00
u_pin_out_ctl_key1_out	100.00	100.00	100.00			100.00
u_pin_out_ctl_key2_out	100.00	100.00	100.00			100.00
u_pin_out_ctl_pwrb_out	100.00	100.00	100.00			100.00
u_pin_out_ctl_z3_wakeup	100.00	100.00	100.00			100.00
u_pin_out_value_bat_disable	100.00	100.00	100.00			100.00
u_pin_out_value_cdc	99.17	100.00	96.67			100.00	100.00
u_pin_out_value_ec_rst_l	100.00	100.00	100.00			100.00
u_pin_out_value_flash_wp_l	100.00	100.00	100.00			100.00
u_pin_out_value_key0_out	100.00	100.00	100.00			100.00
u_pin_out_value_key1_out	100.00	100.00	100.00			100.00
u_pin_out_value_key2_out	100.00	100.00	100.00			100.00
u_pin_out_value_pwrb_out	100.00	100.00	100.00			100.00
u_pin_out_value_z3_wakeup	100.00	100.00	100.00			100.00
u_prim_reg_we_check	100.00	100.00		100.00
u_reg_if	98.69	97.14	97.62			100.00	100.00
u_regwen	100.00	100.00	100.00			100.00
u_rsp_intg_gen	100.00	100.00					100.00
u_ulp_ac_debounce_ctl	100.00	100.00	100.00			100.00
u_ulp_ac_debounce_ctl_cdc	98.33	100.00	93.33			100.00	100.00
u_ulp_ctl	100.00	100.00	100.00			100.00
u_ulp_ctl_cdc	99.22	100.00	96.88			100.00	100.00
u_ulp_lid_debounce_ctl	100.00	100.00	100.00			100.00
u_ulp_lid_debounce_ctl_cdc	98.33	100.00	93.33			100.00	100.00
u_ulp_pwrb_debounce_ctl	100.00	100.00	100.00			100.00
u_ulp_pwrb_debounce_ctl_cdc	98.33	100.00	93.33			100.00	100.00
u_ulp_status	100.00	100.00	100.00			100.00
u_ulp_status_cdc	93.10	96.99	82.19			93.22	100.00
u_wkup_status	100.00	100.00	100.00			100.00
u_wkup_status_cdc	93.10	96.99	82.19			93.22	100.00

Line Coverage for Module : sysrst_ctrl_reg_top

	Line No.	Total	Covered	Percent
TOTAL		532	532	100.00
ALWAYS	73	4	4	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	272	2	2	100.00
CONT_ASSIGN	300	1	1	100.00
ALWAYS	311	2	2	100.00
CONT_ASSIGN	339	1	1	100.00
ALWAYS	350	2	2	100.00
CONT_ASSIGN	378	1	1	100.00
ALWAYS	389	2	2	100.00
CONT_ASSIGN	417	1	1	100.00
ALWAYS	427	2	2	100.00
CONT_ASSIGN	455	1	1	100.00
ALWAYS	468	4	4	100.00
CONT_ASSIGN	498	1	1	100.00
ALWAYS	511	4	4	100.00
CONT_ASSIGN	541	1	1	100.00
ALWAYS	563	13	13	100.00
CONT_ASSIGN	602	1	1	100.00
ALWAYS	628	17	17	100.00
CONT_ASSIGN	671	1	1	100.00
ALWAYS	688	9	9	100.00
CONT_ASSIGN	723	1	1	100.00
ALWAYS	740	9	9	100.00
CONT_ASSIGN	775	1	1	100.00
ALWAYS	799	15	15	100.00
CONT_ASSIGN	840	1	1	100.00
ALWAYS	851	2	2	100.00
CONT_ASSIGN	879	1	1	100.00
ALWAYS	891	3	3	100.00
CONT_ASSIGN	920	1	1	100.00
ALWAYS	936	7	7	100.00
CONT_ASSIGN	969	1	1	100.00
ALWAYS	984	6	6	100.00
CONT_ASSIGN	1016	1	1	100.00
ALWAYS	1031	6	6	100.00
CONT_ASSIGN	1063	1	1	100.00
ALWAYS	1078	6	6	100.00
CONT_ASSIGN	1110	1	1	100.00
ALWAYS	1125	6	6	100.00
CONT_ASSIGN	1157	1	1	100.00
ALWAYS	1168	2	2	100.00
CONT_ASSIGN	1196	1	1	100.00
ALWAYS	1207	2	2	100.00
CONT_ASSIGN	1235	1	1	100.00
ALWAYS	1246	2	2	100.00
CONT_ASSIGN	1274	1	1	100.00
ALWAYS	1285	2	2	100.00
CONT_ASSIGN	1313	1	1	100.00
ALWAYS	1328	6	6	100.00
CONT_ASSIGN	1360	1	1	100.00
ALWAYS	1375	6	6	100.00
CONT_ASSIGN	1407	1	1	100.00
ALWAYS	1422	6	6	100.00
CONT_ASSIGN	1454	1	1	100.00
ALWAYS	1469	6	6	100.00
CONT_ASSIGN	1501	1	1	100.00
ALWAYS	1512	2	2	100.00
CONT_ASSIGN	1540	1	1	100.00
ALWAYS	1551	2	2	100.00
CONT_ASSIGN	1579	1	1	100.00
ALWAYS	1590	2	2	100.00
CONT_ASSIGN	1618	1	1	100.00
ALWAYS	1629	2	2	100.00
CONT_ASSIGN	1657	1	1	100.00
ALWAYS	1671	5	5	100.00
CONT_ASSIGN	1702	1	1	100.00
ALWAYS	1716	5	5	100.00
CONT_ASSIGN	1747	1	1	100.00
ALWAYS	1761	5	5	100.00
CONT_ASSIGN	1792	1	1	100.00
ALWAYS	1806	5	5	100.00
CONT_ASSIGN	1837	1	1	100.00
ALWAYS	1856	10	10	100.00
CONT_ASSIGN	1892	1	1	100.00
ALWAYS	1931	30	30	100.00
CONT_ASSIGN	1987	1	1	100.00
CONT_ASSIGN	2048	1	1	100.00
CONT_ASSIGN	2062	1	1	100.00
CONT_ASSIGN	2068	1	1	100.00
CONT_ASSIGN	2082	1	1	100.00
CONT_ASSIGN	2115	1	1	100.00
CONT_ASSIGN	2145	1	1	100.00
CONT_ASSIGN	2176	1	1	100.00
CONT_ASSIGN	2207	1	1	100.00
CONT_ASSIGN	2264	1	1	100.00
CONT_ASSIGN	2293	1	1	100.00
CONT_ASSIGN	2323	1	1	100.00
CONT_ASSIGN	2640	1	1	100.00
CONT_ASSIGN	3691	1	1	100.00
CONT_ASSIGN	4060	1	1	100.00
CONT_ASSIGN	4091	1	1	100.00
CONT_ASSIGN	4149	1	1	100.00
CONT_ASSIGN	4312	1	1	100.00
CONT_ASSIGN	4448	1	1	100.00
CONT_ASSIGN	4584	1	1	100.00
CONT_ASSIGN	4720	1	1	100.00
CONT_ASSIGN	4856	1	1	100.00
CONT_ASSIGN	4887	1	1	100.00
CONT_ASSIGN	4918	1	1	100.00
CONT_ASSIGN	4949	1	1	100.00
CONT_ASSIGN	4980	1	1	100.00
CONT_ASSIGN	5116	1	1	100.00
CONT_ASSIGN	5252	1	1	100.00
CONT_ASSIGN	5388	1	1	100.00
CONT_ASSIGN	5524	1	1	100.00
CONT_ASSIGN	5555	1	1	100.00
CONT_ASSIGN	5586	1	1	100.00
CONT_ASSIGN	5617	1	1	100.00
CONT_ASSIGN	5648	1	1	100.00
CONT_ASSIGN	5758	1	1	100.00
CONT_ASSIGN	5868	1	1	100.00
CONT_ASSIGN	5978	1	1	100.00
CONT_ASSIGN	6086	1	1	100.00
CONT_ASSIGN	6194	1	1	100.00
ALWAYS	6563	44	44	100.00
CONT_ASSIGN	6609	1	1	100.00
ALWAYS	6613	1	1	100.00
CONT_ASSIGN	6660	1	1	100.00
CONT_ASSIGN	6662	1	1	100.00
CONT_ASSIGN	6663	1	1	100.00
CONT_ASSIGN	6665	1	1	100.00
CONT_ASSIGN	6666	1	1	100.00
CONT_ASSIGN	6668	1	1	100.00
CONT_ASSIGN	6669	1	1	100.00
CONT_ASSIGN	6671	1	1	100.00
CONT_ASSIGN	6672	1	1	100.00
CONT_ASSIGN	6674	1	1	100.00
CONT_ASSIGN	6675	1	1	100.00
CONT_ASSIGN	6677	1	1	100.00
CONT_ASSIGN	6679	1	1	100.00
CONT_ASSIGN	6681	1	1	100.00
CONT_ASSIGN	6683	1	1	100.00
CONT_ASSIGN	6685	1	1	100.00
CONT_ASSIGN	6687	1	1	100.00
CONT_ASSIGN	6689	1	1	100.00
CONT_ASSIGN	6702	1	1	100.00
CONT_ASSIGN	6719	1	1	100.00
CONT_ASSIGN	6728	1	1	100.00
CONT_ASSIGN	6737	1	1	100.00
CONT_ASSIGN	6752	1	1	100.00
CONT_ASSIGN	6754	1	1	100.00
CONT_ASSIGN	6757	1	1	100.00
CONT_ASSIGN	6764	1	1	100.00
CONT_ASSIGN	6770	1	1	100.00
CONT_ASSIGN	6776	1	1	100.00
CONT_ASSIGN	6782	1	1	100.00
CONT_ASSIGN	6788	1	1	100.00
CONT_ASSIGN	6790	1	1	100.00
CONT_ASSIGN	6792	1	1	100.00
CONT_ASSIGN	6794	1	1	100.00
CONT_ASSIGN	6796	1	1	100.00
CONT_ASSIGN	6802	1	1	100.00
CONT_ASSIGN	6808	1	1	100.00
CONT_ASSIGN	6814	1	1	100.00
CONT_ASSIGN	6820	1	1	100.00
CONT_ASSIGN	6822	1	1	100.00
CONT_ASSIGN	6824	1	1	100.00
CONT_ASSIGN	6826	1	1	100.00
CONT_ASSIGN	6828	1	1	100.00
CONT_ASSIGN	6833	1	1	100.00
CONT_ASSIGN	6838	1	1	100.00
CONT_ASSIGN	6843	1	1	100.00
CONT_ASSIGN	6848	1	1	100.00
CONT_ASSIGN	6853	1	1	100.00
ALWAYS	6871	44	44	100.00
ALWAYS	6919	52	52	100.00
CONT_ASSIGN	7075	1	1	100.00
ALWAYS	7077	39	39	100.00
CONT_ASSIGN	7203	1	1	100.00
CONT_ASSIGN	7204	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_reg_top.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_reg_top.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
82	1	1
94	1	1
95	1	1
123	1	1
124	1	1
272	1	1
273	1	1
300	1	1
311	1	1
312	1	1
339	1	1
350	1	1
351	1	1
378	1	1
389	1	1
390	1	1
417	1	1
427	1	1
428	1	1
455	1	1
468	1	1
469	1	1
470	1	1
471	1	1
498	1	1
511	1	1
512	1	1
513	1	1
514	1	1
541	1	1
563	1	1
564	1	1
565	1	1
566	1	1
567	1	1
568	1	1
569	1	1
570	1	1
571	1	1
572	1	1
573	1	1
574	1	1
575	1	1
602	1	1
628	1	1
629	1	1
630	1	1
631	1	1
632	1	1
633	1	1
634	1	1
635	1	1
636	1	1
637	1	1
638	1	1
639	1	1
640	1	1
641	1	1
642	1	1
643	1	1
644	1	1
671	1	1
688	1	1
689	1	1
690	1	1
691	1	1
692	1	1
693	1	1
694	1	1
695	1	1
696	1	1
723	1	1
740	1	1
741	1	1
742	1	1
743	1	1
744	1	1
745	1	1
746	1	1
747	1	1
748	1	1
775	1	1
799	1	1
800	1	1
801	1	1
802	1	1
803	1	1
804	1	1
805	1	1
806	1	1
807	1	1
808	1	1
809	1	1
810	1	1
811	1	1
812	1	1
813	1	1
840	1	1
851	1	1
852	1	1
879	1	1
891	1	1
892	1	1
893	1	1
920	1	1
936	1	1
937	1	1
938	1	1
939	1	1
940	1	1
941	1	1
942	1	1
969	1	1
984	1	1
985	1	1
986	1	1
987	1	1
988	1	1
989	1	1
1016	1	1
1031	1	1
1032	1	1
1033	1	1
1034	1	1
1035	1	1
1036	1	1
1063	1	1
1078	1	1
1079	1	1
1080	1	1
1081	1	1
1082	1	1
1083	1	1
1110	1	1
1125	1	1
1126	1	1
1127	1	1
1128	1	1
1129	1	1
1130	1	1
1157	1	1
1168	1	1
1169	1	1
1196	1	1
1207	1	1
1208	1	1
1235	1	1
1246	1	1
1247	1	1
1274	1	1
1285	1	1
1286	1	1
1313	1	1
1328	1	1
1329	1	1
1330	1	1
1331	1	1
1332	1	1
1333	1	1
1360	1	1
1375	1	1
1376	1	1
1377	1	1
1378	1	1
1379	1	1
1380	1	1
1407	1	1
1422	1	1
1423	1	1
1424	1	1
1425	1	1
1426	1	1
1427	1	1
1454	1	1
1469	1	1
1470	1	1
1471	1	1
1472	1	1
1473	1	1
1474	1	1
1501	1	1
1512	1	1
1513	1	1
1540	1	1
1551	1	1
1552	1	1
1579	1	1
1590	1	1
1591	1	1
1618	1	1
1629	1	1
1630	1	1
1657	1	1
1671	1	1
1672	1	1
1673	1	1
1674	1	1
1675	1	1
1702	1	1
1716	1	1
1717	1	1
1718	1	1
1719	1	1
1720	1	1
1747	1	1
1761	1	1
1762	1	1
1763	1	1
1764	1	1
1765	1	1
1792	1	1
1806	1	1
1807	1	1
1808	1	1
1809	1	1
1810	1	1
1837	1	1
1856	1	1
1857	1	1
1858	1	1
1859	1	1
1860	1	1
1861	1	1
1862	1	1
1863	1	1
1864	1	1
1865	1	1
1892	1	1
1931	1	1
1932	1	1
1933	1	1
1934	1	1
1935	1	1
1936	1	1
1937	1	1
1938	1	1
1939	1	1
1940	1	1
1941	1	1
1942	1	1
1943	1	1
1944	1	1
1945	1	1
1946	1	1
1947	1	1
1948	1	1
1949	1	1
1950	1	1
1951	1	1
1952	1	1
1953	1	1
1954	1	1
1955	1	1
1956	1	1
1957	1	1
1958	1	1
1959	1	1
1960	1	1
1987	1	1
2048	1	1
2062	1	1
2068	1	1
2082	1	1
2115	1	1
2145	1	1
2176	1	1
2207	1	1
2264	1	1
2293	1	1
2323	1	1
2640	1	1
3691	1	1
4060	1	1
4091	1	1
4149	1	1
4312	1	1
4448	1	1
4584	1	1
4720	1	1
4856	1	1
4887	1	1
4918	1	1
4949	1	1
4980	1	1
5116	1	1
5252	1	1
5388	1	1
5524	1	1
5555	1	1
5586	1	1
5617	1	1
5648	1	1
5758	1	1
5868	1	1
5978	1	1
6086	1	1
6194	1	1
6563	1	1
6564	1	1
6565	1	1
6566	1	1
6567	1	1
6568	1	1
6569	1	1
6570	1	1
6571	1	1
6572	1	1
6573	1	1
6574	1	1
6575	1	1
6576	1	1
6577	1	1
6578	1	1
6579	1	1
6580	1	1
6581	1	1
6582	1	1
6583	1	1
6584	1	1
6585	1	1
6586	1	1
6587	1	1
6588	1	1
6589	1	1
6590	1	1
6591	1	1
6592	1	1
6593	1	1
6594	1	1
6595	1	1
6596	1	1
6597	1	1
6598	1	1
6599	1	1
6600	1	1
6601	1	1
6602	1	1
6603	1	1
6604	1	1
6605	1	1
6606	1	1
6609	1	1
6613	1	1
6660	1	1
6662	1	1
6663	1	1
6665	1	1
6666	1	1
6668	1	1
6669	1	1
6671	1	1
6672	1	1
6674	1	1
6675	1	1
6677	1	1
6679	1	1
6681	1	1
6683	1	1
6685	1	1
6687	1	1
6689	1	1
6702	1	1
6719	1	1
6728	1	1
6737	1	1
6752	1	1
6754	1	1
6757	1	1
6764	1	1
6770	1	1
6776	1	1
6782	1	1
6788	1	1
6790	1	1
6792	1	1
6794	1	1
6796	1	1
6802	1	1
6808	1	1
6814	1	1
6820	1	1
6822	1	1
6824	1	1
6826	1	1
6828	1	1
6833	1	1
6838	1	1
6843	1	1
6848	1	1
6853	1	1
6871	1	1
6872	1	1
6873	1	1
6874	1	1
6875	1	1
6876	1	1
6877	1	1
6878	1	1
6879	1	1
6880	1	1
6881	1	1
6882	1	1
6883	1	1
6884	1	1
6885	1	1
6886	1	1
6887	1	1
6888	1	1
6889	1	1
6890	1	1
6891	1	1
6892	1	1
6893	1	1
6894	1	1
6895	1	1
6896	1	1
6897	1	1
6898	1	1
6899	1	1
6900	1	1
6901	1	1
6902	1	1
6903	1	1
6904	1	1
6905	1	1
6906	1	1
6907	1	1
6908	1	1
6909	1	1
6910	1	1
6911	1	1
6912	1	1
6913	1	1
6914	1	1
6919	1	1
6920	1	1
6922	1	1
6926	1	1
6930	1	1
6934	1	1
6938	1	1
6942	1	1
6945	1	1
6948	1	1
6951	1	1
6954	1	1
6957	1	1
6960	1	1
6963	1	1
6966	1	1
6969	1	1
6972	1	1
6975	1	1
6976	1	1
6977	1	1
6978	1	1
6979	1	1
6980	1	1
6981	1	1
6982	1	1
6986	1	1
6989	1	1
6992	1	1
6995	1	1
6998	1	1
7001	1	1
7004	1	1
7007	1	1
7010	1	1
7013	1	1
7016	1	1
7019	1	1
7022	1	1
7025	1	1
7028	1	1
7031	1	1
7034	1	1
7037	1	1
7040	1	1
7043	1	1
7046	1	1
7049	1	1
7052	1	1
7055	1	1
7058	1	1
7061	1	1
7075	1	1
7077	1	1
7078	1	1
7080	1	1
7083	1	1
7086	1	1
7089	1	1
7092	1	1
7095	1	1
7098	1	1
7101	1	1
7104	1	1
7107	1	1
7110	1	1
7113	1	1
7116	1	1
7119	1	1
7122	1	1
7125	1	1
7128	1	1
7131	1	1
7134	1	1
7137	1	1
7140	1	1
7143	1	1
7146	1	1
7149	1	1
7152	1	1
7155	1	1
7158	1	1
7161	1	1
7164	1	1
7167	1	1
7170	1	1
7173	1	1
7176	1	1
7179	1	1
7182	1	1
7185	1	1
7188	1	1
7203	1	1
7204	1	1

---

Cond Coverage for Module : sysrst_ctrl_reg_top

	Total	Covered	Percent
Conditions	543	513	94.48
Logical	543	513	94.48
Non-Logical	0	0
Event	0	0

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.

Line numbers	Percent
63-6677	92.52
6679-7075	100.00

---

Branch Coverage for Module : sysrst_ctrl_reg_top

	Line No.	Total	Covered	Percent
Branches		87	87	100.00
TERNARY	6609	2	2	100.00
IF	73	3	3	100.00
CASE	6920	44	44	100.00
CASE	7078	38	38	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_reg_top.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	6609	((reg_re || reg_we)) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	73	if ((!rst_ni))
-2-:	75	if ((intg_err || reg_we_err))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T6,T7,T8
0	1	Covered	T10,T13,T307
0	0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	6920	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[0]	Covered	T6,T7,T8
addr_hit[1]	Covered	T6,T7,T8
addr_hit[2]	Covered	T6,T7,T8
addr_hit[3]	Covered	T6,T7,T8
addr_hit[4]	Covered	T6,T7,T8
addr_hit[5]	Covered	T6,T7,T8
addr_hit[6]	Covered	T6,T7,T8
addr_hit[7]	Covered	T6,T7,T8
addr_hit[8]	Covered	T6,T7,T8
addr_hit[9]	Covered	T6,T7,T8
addr_hit[10]	Covered	T6,T7,T8
addr_hit[11]	Covered	T6,T7,T8
addr_hit[12]	Covered	T6,T7,T8
addr_hit[13]	Covered	T6,T7,T8
addr_hit[14]	Covered	T6,T7,T8
addr_hit[15]	Covered	T6,T7,T8
addr_hit[16]	Covered	T6,T7,T8
addr_hit[17]	Covered	T6,T7,T8
addr_hit[18]	Covered	T6,T7,T8
addr_hit[19]	Covered	T6,T7,T8
addr_hit[20]	Covered	T6,T7,T8
addr_hit[21]	Covered	T6,T7,T8
addr_hit[22]	Covered	T6,T7,T8
addr_hit[23]	Covered	T6,T7,T8
addr_hit[24]	Covered	T6,T7,T8
addr_hit[25]	Covered	T6,T7,T8
addr_hit[26]	Covered	T6,T7,T8
addr_hit[27]	Covered	T6,T7,T8
addr_hit[28]	Covered	T6,T7,T8
addr_hit[29]	Covered	T6,T7,T8
addr_hit[30]	Covered	T6,T7,T8
addr_hit[31]	Covered	T6,T7,T8
addr_hit[32]	Covered	T6,T7,T8
addr_hit[33]	Covered	T6,T7,T8
addr_hit[34]	Covered	T6,T7,T8
addr_hit[35]	Covered	T6,T7,T8
addr_hit[36]	Covered	T6,T7,T8
addr_hit[37]	Covered	T6,T7,T8
addr_hit[38]	Covered	T6,T7,T8
addr_hit[39]	Covered	T6,T7,T8
addr_hit[40]	Covered	T6,T7,T8
addr_hit[41]	Covered	T6,T7,T8
addr_hit[42]	Covered	T6,T7,T8
default	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	7078	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[5]	Covered	T6,T7,T8
addr_hit[6]	Covered	T6,T7,T8
addr_hit[7]	Covered	T6,T7,T8
addr_hit[8]	Covered	T6,T7,T8
addr_hit[9]	Covered	T6,T7,T8
addr_hit[10]	Covered	T6,T7,T8
addr_hit[11]	Covered	T6,T7,T8
addr_hit[12]	Covered	T6,T7,T8
addr_hit[13]	Covered	T6,T7,T8
addr_hit[14]	Covered	T6,T7,T8
addr_hit[15]	Covered	T6,T7,T8
addr_hit[17]	Covered	T6,T7,T8
addr_hit[18]	Covered	T6,T7,T8
addr_hit[19]	Covered	T6,T7,T8
addr_hit[20]	Covered	T6,T7,T8
addr_hit[21]	Covered	T6,T7,T8
addr_hit[22]	Covered	T6,T7,T8
addr_hit[23]	Covered	T6,T7,T8
addr_hit[24]	Covered	T6,T7,T8
addr_hit[25]	Covered	T6,T7,T8
addr_hit[26]	Covered	T6,T7,T8
addr_hit[27]	Covered	T6,T7,T8
addr_hit[28]	Covered	T6,T7,T8
addr_hit[29]	Covered	T6,T7,T8
addr_hit[30]	Covered	T6,T7,T8
addr_hit[31]	Covered	T6,T7,T8
addr_hit[32]	Covered	T6,T7,T8
addr_hit[33]	Covered	T6,T7,T8
addr_hit[34]	Covered	T6,T7,T8
addr_hit[35]	Covered	T6,T7,T8
addr_hit[36]	Covered	T6,T7,T8
addr_hit[37]	Covered	T6,T7,T8
addr_hit[38]	Covered	T6,T7,T8
addr_hit[39]	Covered	T6,T7,T8
addr_hit[40]	Covered	T6,T7,T8
addr_hit[41]	Covered	T6,T7,T8
addr_hit[42]	Covered	T6,T7,T8
default	Covered	T6,T7,T8

---

Assert Coverage for Module : sysrst_ctrl_reg_top

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
en2addrHit	1273447815	258791	0	0
reAfterRv	1273447815	258787	0	0
rePulse	1273447815	132571	0	0
wePulse	1273447815	126216	0	0

en2addrHit

Name	Attempts	Real Successes	Failures	Incomplete
Total	1273447815	258791	0	0
T1	99621	83	0	0
T2	48994	84	0	0
T6	58826	22	0	0
T7	57869	60	0	0
T8	193164	22	0	0
T45	52732	38	0	0
T46	185059	22	0	0
T47	51706	60	0	0
T48	199056	83	0	0
T49	50948	20	0	0

reAfterRv

Name	Attempts	Real Successes	Failures	Incomplete
Total	1273447815	258787	0	0
T1	99621	83	0	0
T2	48994	84	0	0
T6	58826	22	0	0
T7	57869	60	0	0
T8	193164	22	0	0
T45	52732	38	0	0
T46	185059	22	0	0
T47	51706	60	0	0
T48	199056	83	0	0
T49	50948	20	0	0

rePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	1273447815	132571	0	0
T1	99621	42	0	0
T2	48994	42	0	0
T6	58826	11	0	0
T7	57869	14	0	0
T8	193164	11	0	0
T45	52732	19	0	0
T46	185059	11	0	0
T47	51706	42	0	0
T48	199056	42	0	0
T49	50948	10	0	0

wePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	1273447815	126216	0	0
T1	99621	41	0	0
T2	48994	42	0	0
T6	58826	11	0	0
T7	57869	46	0	0
T8	193164	11	0	0
T45	52732	19	0	0
T46	185059	11	0	0
T47	51706	18	0	0
T48	199056	41	0	0
T49	50948	10	0	0

Line Coverage for Instance : tb.dut.u_reg

	Line No.	Total	Covered	Percent
TOTAL		532	532	100.00
ALWAYS	73	4	4	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	272	2	2	100.00
CONT_ASSIGN	300	1	1	100.00
ALWAYS	311	2	2	100.00
CONT_ASSIGN	339	1	1	100.00
ALWAYS	350	2	2	100.00
CONT_ASSIGN	378	1	1	100.00
ALWAYS	389	2	2	100.00
CONT_ASSIGN	417	1	1	100.00
ALWAYS	427	2	2	100.00
CONT_ASSIGN	455	1	1	100.00
ALWAYS	468	4	4	100.00
CONT_ASSIGN	498	1	1	100.00
ALWAYS	511	4	4	100.00
CONT_ASSIGN	541	1	1	100.00
ALWAYS	563	13	13	100.00
CONT_ASSIGN	602	1	1	100.00
ALWAYS	628	17	17	100.00
CONT_ASSIGN	671	1	1	100.00
ALWAYS	688	9	9	100.00
CONT_ASSIGN	723	1	1	100.00
ALWAYS	740	9	9	100.00
CONT_ASSIGN	775	1	1	100.00
ALWAYS	799	15	15	100.00
CONT_ASSIGN	840	1	1	100.00
ALWAYS	851	2	2	100.00
CONT_ASSIGN	879	1	1	100.00
ALWAYS	891	3	3	100.00
CONT_ASSIGN	920	1	1	100.00
ALWAYS	936	7	7	100.00
CONT_ASSIGN	969	1	1	100.00
ALWAYS	984	6	6	100.00
CONT_ASSIGN	1016	1	1	100.00
ALWAYS	1031	6	6	100.00
CONT_ASSIGN	1063	1	1	100.00
ALWAYS	1078	6	6	100.00
CONT_ASSIGN	1110	1	1	100.00
ALWAYS	1125	6	6	100.00
CONT_ASSIGN	1157	1	1	100.00
ALWAYS	1168	2	2	100.00
CONT_ASSIGN	1196	1	1	100.00
ALWAYS	1207	2	2	100.00
CONT_ASSIGN	1235	1	1	100.00
ALWAYS	1246	2	2	100.00
CONT_ASSIGN	1274	1	1	100.00
ALWAYS	1285	2	2	100.00
CONT_ASSIGN	1313	1	1	100.00
ALWAYS	1328	6	6	100.00
CONT_ASSIGN	1360	1	1	100.00
ALWAYS	1375	6	6	100.00
CONT_ASSIGN	1407	1	1	100.00
ALWAYS	1422	6	6	100.00
CONT_ASSIGN	1454	1	1	100.00
ALWAYS	1469	6	6	100.00
CONT_ASSIGN	1501	1	1	100.00
ALWAYS	1512	2	2	100.00
CONT_ASSIGN	1540	1	1	100.00
ALWAYS	1551	2	2	100.00
CONT_ASSIGN	1579	1	1	100.00
ALWAYS	1590	2	2	100.00
CONT_ASSIGN	1618	1	1	100.00
ALWAYS	1629	2	2	100.00
CONT_ASSIGN	1657	1	1	100.00
ALWAYS	1671	5	5	100.00
CONT_ASSIGN	1702	1	1	100.00
ALWAYS	1716	5	5	100.00
CONT_ASSIGN	1747	1	1	100.00
ALWAYS	1761	5	5	100.00
CONT_ASSIGN	1792	1	1	100.00
ALWAYS	1806	5	5	100.00
CONT_ASSIGN	1837	1	1	100.00
ALWAYS	1856	10	10	100.00
CONT_ASSIGN	1892	1	1	100.00
ALWAYS	1931	30	30	100.00
CONT_ASSIGN	1987	1	1	100.00
CONT_ASSIGN	2048	1	1	100.00
CONT_ASSIGN	2062	1	1	100.00
CONT_ASSIGN	2068	1	1	100.00
CONT_ASSIGN	2082	1	1	100.00
CONT_ASSIGN	2115	1	1	100.00
CONT_ASSIGN	2145	1	1	100.00
CONT_ASSIGN	2176	1	1	100.00
CONT_ASSIGN	2207	1	1	100.00
CONT_ASSIGN	2264	1	1	100.00
CONT_ASSIGN	2293	1	1	100.00
CONT_ASSIGN	2323	1	1	100.00
CONT_ASSIGN	2640	1	1	100.00
CONT_ASSIGN	3691	1	1	100.00
CONT_ASSIGN	4060	1	1	100.00
CONT_ASSIGN	4091	1	1	100.00
CONT_ASSIGN	4149	1	1	100.00
CONT_ASSIGN	4312	1	1	100.00
CONT_ASSIGN	4448	1	1	100.00
CONT_ASSIGN	4584	1	1	100.00
CONT_ASSIGN	4720	1	1	100.00
CONT_ASSIGN	4856	1	1	100.00
CONT_ASSIGN	4887	1	1	100.00
CONT_ASSIGN	4918	1	1	100.00
CONT_ASSIGN	4949	1	1	100.00
CONT_ASSIGN	4980	1	1	100.00
CONT_ASSIGN	5116	1	1	100.00
CONT_ASSIGN	5252	1	1	100.00
CONT_ASSIGN	5388	1	1	100.00
CONT_ASSIGN	5524	1	1	100.00
CONT_ASSIGN	5555	1	1	100.00
CONT_ASSIGN	5586	1	1	100.00
CONT_ASSIGN	5617	1	1	100.00
CONT_ASSIGN	5648	1	1	100.00
CONT_ASSIGN	5758	1	1	100.00
CONT_ASSIGN	5868	1	1	100.00
CONT_ASSIGN	5978	1	1	100.00
CONT_ASSIGN	6086	1	1	100.00
CONT_ASSIGN	6194	1	1	100.00
ALWAYS	6563	44	44	100.00
CONT_ASSIGN	6609	1	1	100.00
ALWAYS	6613	1	1	100.00
CONT_ASSIGN	6660	1	1	100.00
CONT_ASSIGN	6662	1	1	100.00
CONT_ASSIGN	6663	1	1	100.00
CONT_ASSIGN	6665	1	1	100.00
CONT_ASSIGN	6666	1	1	100.00
CONT_ASSIGN	6668	1	1	100.00
CONT_ASSIGN	6669	1	1	100.00
CONT_ASSIGN	6671	1	1	100.00
CONT_ASSIGN	6672	1	1	100.00
CONT_ASSIGN	6674	1	1	100.00
CONT_ASSIGN	6675	1	1	100.00
CONT_ASSIGN	6677	1	1	100.00
CONT_ASSIGN	6679	1	1	100.00
CONT_ASSIGN	6681	1	1	100.00
CONT_ASSIGN	6683	1	1	100.00
CONT_ASSIGN	6685	1	1	100.00
CONT_ASSIGN	6687	1	1	100.00
CONT_ASSIGN	6689	1	1	100.00
CONT_ASSIGN	6702	1	1	100.00
CONT_ASSIGN	6719	1	1	100.00
CONT_ASSIGN	6728	1	1	100.00
CONT_ASSIGN	6737	1	1	100.00
CONT_ASSIGN	6752	1	1	100.00
CONT_ASSIGN	6754	1	1	100.00
CONT_ASSIGN	6757	1	1	100.00
CONT_ASSIGN	6764	1	1	100.00
CONT_ASSIGN	6770	1	1	100.00
CONT_ASSIGN	6776	1	1	100.00
CONT_ASSIGN	6782	1	1	100.00
CONT_ASSIGN	6788	1	1	100.00
CONT_ASSIGN	6790	1	1	100.00
CONT_ASSIGN	6792	1	1	100.00
CONT_ASSIGN	6794	1	1	100.00
CONT_ASSIGN	6796	1	1	100.00
CONT_ASSIGN	6802	1	1	100.00
CONT_ASSIGN	6808	1	1	100.00
CONT_ASSIGN	6814	1	1	100.00
CONT_ASSIGN	6820	1	1	100.00
CONT_ASSIGN	6822	1	1	100.00
CONT_ASSIGN	6824	1	1	100.00
CONT_ASSIGN	6826	1	1	100.00
CONT_ASSIGN	6828	1	1	100.00
CONT_ASSIGN	6833	1	1	100.00
CONT_ASSIGN	6838	1	1	100.00
CONT_ASSIGN	6843	1	1	100.00
CONT_ASSIGN	6848	1	1	100.00
CONT_ASSIGN	6853	1	1	100.00
ALWAYS	6871	44	44	100.00
ALWAYS	6919	52	52	100.00
CONT_ASSIGN	7075	1	1	100.00
ALWAYS	7077	39	39	100.00
CONT_ASSIGN	7203	1	1	100.00
CONT_ASSIGN	7204	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_reg_top.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_reg_top.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
82	1	1
94	1	1
95	1	1
123	1	1
124	1	1
272	1	1
273	1	1
300	1	1
311	1	1
312	1	1
339	1	1
350	1	1
351	1	1
378	1	1
389	1	1
390	1	1
417	1	1
427	1	1
428	1	1
455	1	1
468	1	1
469	1	1
470	1	1
471	1	1
498	1	1
511	1	1
512	1	1
513	1	1
514	1	1
541	1	1
563	1	1
564	1	1
565	1	1
566	1	1
567	1	1
568	1	1
569	1	1
570	1	1
571	1	1
572	1	1
573	1	1
574	1	1
575	1	1
602	1	1
628	1	1
629	1	1
630	1	1
631	1	1
632	1	1
633	1	1
634	1	1
635	1	1
636	1	1
637	1	1
638	1	1
639	1	1
640	1	1
641	1	1
642	1	1
643	1	1
644	1	1
671	1	1
688	1	1
689	1	1
690	1	1
691	1	1
692	1	1
693	1	1
694	1	1
695	1	1
696	1	1
723	1	1
740	1	1
741	1	1
742	1	1
743	1	1
744	1	1
745	1	1
746	1	1
747	1	1
748	1	1
775	1	1
799	1	1
800	1	1
801	1	1
802	1	1
803	1	1
804	1	1
805	1	1
806	1	1
807	1	1
808	1	1
809	1	1
810	1	1
811	1	1
812	1	1
813	1	1
840	1	1
851	1	1
852	1	1
879	1	1
891	1	1
892	1	1
893	1	1
920	1	1
936	1	1
937	1	1
938	1	1
939	1	1
940	1	1
941	1	1
942	1	1
969	1	1
984	1	1
985	1	1
986	1	1
987	1	1
988	1	1
989	1	1
1016	1	1
1031	1	1
1032	1	1
1033	1	1
1034	1	1
1035	1	1
1036	1	1
1063	1	1
1078	1	1
1079	1	1
1080	1	1
1081	1	1
1082	1	1
1083	1	1
1110	1	1
1125	1	1
1126	1	1
1127	1	1
1128	1	1
1129	1	1
1130	1	1
1157	1	1
1168	1	1
1169	1	1
1196	1	1
1207	1	1
1208	1	1
1235	1	1
1246	1	1
1247	1	1
1274	1	1
1285	1	1
1286	1	1
1313	1	1
1328	1	1
1329	1	1
1330	1	1
1331	1	1
1332	1	1
1333	1	1
1360	1	1
1375	1	1
1376	1	1
1377	1	1
1378	1	1
1379	1	1
1380	1	1
1407	1	1
1422	1	1
1423	1	1
1424	1	1
1425	1	1
1426	1	1
1427	1	1
1454	1	1
1469	1	1
1470	1	1
1471	1	1
1472	1	1
1473	1	1
1474	1	1
1501	1	1
1512	1	1
1513	1	1
1540	1	1
1551	1	1
1552	1	1
1579	1	1
1590	1	1
1591	1	1
1618	1	1
1629	1	1
1630	1	1
1657	1	1
1671	1	1
1672	1	1
1673	1	1
1674	1	1
1675	1	1
1702	1	1
1716	1	1
1717	1	1
1718	1	1
1719	1	1
1720	1	1
1747	1	1
1761	1	1
1762	1	1
1763	1	1
1764	1	1
1765	1	1
1792	1	1
1806	1	1
1807	1	1
1808	1	1
1809	1	1
1810	1	1
1837	1	1
1856	1	1
1857	1	1
1858	1	1
1859	1	1
1860	1	1
1861	1	1
1862	1	1
1863	1	1
1864	1	1
1865	1	1
1892	1	1
1931	1	1
1932	1	1
1933	1	1
1934	1	1
1935	1	1
1936	1	1
1937	1	1
1938	1	1
1939	1	1
1940	1	1
1941	1	1
1942	1	1
1943	1	1
1944	1	1
1945	1	1
1946	1	1
1947	1	1
1948	1	1
1949	1	1
1950	1	1
1951	1	1
1952	1	1
1953	1	1
1954	1	1
1955	1	1
1956	1	1
1957	1	1
1958	1	1
1959	1	1
1960	1	1
1987	1	1
2048	1	1
2062	1	1
2068	1	1
2082	1	1
2115	1	1
2145	1	1
2176	1	1
2207	1	1
2264	1	1
2293	1	1
2323	1	1
2640	1	1
3691	1	1
4060	1	1
4091	1	1
4149	1	1
4312	1	1
4448	1	1
4584	1	1
4720	1	1
4856	1	1
4887	1	1
4918	1	1
4949	1	1
4980	1	1
5116	1	1
5252	1	1
5388	1	1
5524	1	1
5555	1	1
5586	1	1
5617	1	1
5648	1	1
5758	1	1
5868	1	1
5978	1	1
6086	1	1
6194	1	1
6563	1	1
6564	1	1
6565	1	1
6566	1	1
6567	1	1
6568	1	1
6569	1	1
6570	1	1
6571	1	1
6572	1	1
6573	1	1
6574	1	1
6575	1	1
6576	1	1
6577	1	1
6578	1	1
6579	1	1
6580	1	1
6581	1	1
6582	1	1
6583	1	1
6584	1	1
6585	1	1
6586	1	1
6587	1	1
6588	1	1
6589	1	1
6590	1	1
6591	1	1
6592	1	1
6593	1	1
6594	1	1
6595	1	1
6596	1	1
6597	1	1
6598	1	1
6599	1	1
6600	1	1
6601	1	1
6602	1	1
6603	1	1
6604	1	1
6605	1	1
6606	1	1
6609	1	1
6613	1	1
6660	1	1
6662	1	1
6663	1	1
6665	1	1
6666	1	1
6668	1	1
6669	1	1
6671	1	1
6672	1	1
6674	1	1
6675	1	1
6677	1	1
6679	1	1
6681	1	1
6683	1	1
6685	1	1
6687	1	1
6689	1	1
6702	1	1
6719	1	1
6728	1	1
6737	1	1
6752	1	1
6754	1	1
6757	1	1
6764	1	1
6770	1	1
6776	1	1
6782	1	1
6788	1	1
6790	1	1
6792	1	1
6794	1	1
6796	1	1
6802	1	1
6808	1	1
6814	1	1
6820	1	1
6822	1	1
6824	1	1
6826	1	1
6828	1	1
6833	1	1
6838	1	1
6843	1	1
6848	1	1
6853	1	1
6871	1	1
6872	1	1
6873	1	1
6874	1	1
6875	1	1
6876	1	1
6877	1	1
6878	1	1
6879	1	1
6880	1	1
6881	1	1
6882	1	1
6883	1	1
6884	1	1
6885	1	1
6886	1	1
6887	1	1
6888	1	1
6889	1	1
6890	1	1
6891	1	1
6892	1	1
6893	1	1
6894	1	1
6895	1	1
6896	1	1
6897	1	1
6898	1	1
6899	1	1
6900	1	1
6901	1	1
6902	1	1
6903	1	1
6904	1	1
6905	1	1
6906	1	1
6907	1	1
6908	1	1
6909	1	1
6910	1	1
6911	1	1
6912	1	1
6913	1	1
6914	1	1
6919	1	1
6920	1	1
6922	1	1
6926	1	1
6930	1	1
6934	1	1
6938	1	1
6942	1	1
6945	1	1
6948	1	1
6951	1	1
6954	1	1
6957	1	1
6960	1	1
6963	1	1
6966	1	1
6969	1	1
6972	1	1
6975	1	1
6976	1	1
6977	1	1
6978	1	1
6979	1	1
6980	1	1
6981	1	1
6982	1	1
6986	1	1
6989	1	1
6992	1	1
6995	1	1
6998	1	1
7001	1	1
7004	1	1
7007	1	1
7010	1	1
7013	1	1
7016	1	1
7019	1	1
7022	1	1
7025	1	1
7028	1	1
7031	1	1
7034	1	1
7037	1	1
7040	1	1
7043	1	1
7046	1	1
7049	1	1
7052	1	1
7055	1	1
7058	1	1
7061	1	1
7075	1	1
7077	1	1
7078	1	1
7080	1	1
7083	1	1
7086	1	1
7089	1	1
7092	1	1
7095	1	1
7098	1	1
7101	1	1
7104	1	1
7107	1	1
7110	1	1
7113	1	1
7116	1	1
7119	1	1
7122	1	1
7125	1	1
7128	1	1
7131	1	1
7134	1	1
7137	1	1
7140	1	1
7143	1	1
7146	1	1
7149	1	1
7152	1	1
7155	1	1
7158	1	1
7161	1	1
7164	1	1
7167	1	1
7170	1	1
7173	1	1
7176	1	1
7179	1	1
7182	1	1
7185	1	1
7188	1	1
7203	1	1
7204	1	1

---

Cond Coverage for Instance : tb.dut.u_reg

	Total	Covered	Percent
Conditions	542	512	94.46
Logical	542	512	94.46
Non-Logical	0	0
Event	0	0

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.

Line numbers	Percent
63-6677	92.50
6679-7075	100.00

---

Branch Coverage for Instance : tb.dut.u_reg

	Line No.	Total	Covered	Percent
Branches		87	87	100.00
TERNARY	6609	2	2	100.00
IF	73	3	3	100.00
CASE	6920	44	44	100.00
CASE	7078	38	38	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_reg_top.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	6609	((reg_re || reg_we)) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	73	if ((!rst_ni))
-2-:	75	if ((intg_err || reg_we_err))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T6,T7,T8
0	1	Covered	T10,T13,T307
0	0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	6920	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[0]	Covered	T6,T7,T8
addr_hit[1]	Covered	T6,T7,T8
addr_hit[2]	Covered	T6,T7,T8
addr_hit[3]	Covered	T6,T7,T8
addr_hit[4]	Covered	T6,T7,T8
addr_hit[5]	Covered	T6,T7,T8
addr_hit[6]	Covered	T6,T7,T8
addr_hit[7]	Covered	T6,T7,T8
addr_hit[8]	Covered	T6,T7,T8
addr_hit[9]	Covered	T6,T7,T8
addr_hit[10]	Covered	T6,T7,T8
addr_hit[11]	Covered	T6,T7,T8
addr_hit[12]	Covered	T6,T7,T8
addr_hit[13]	Covered	T6,T7,T8
addr_hit[14]	Covered	T6,T7,T8
addr_hit[15]	Covered	T6,T7,T8
addr_hit[16]	Covered	T6,T7,T8
addr_hit[17]	Covered	T6,T7,T8
addr_hit[18]	Covered	T6,T7,T8
addr_hit[19]	Covered	T6,T7,T8
addr_hit[20]	Covered	T6,T7,T8
addr_hit[21]	Covered	T6,T7,T8
addr_hit[22]	Covered	T6,T7,T8
addr_hit[23]	Covered	T6,T7,T8
addr_hit[24]	Covered	T6,T7,T8
addr_hit[25]	Covered	T6,T7,T8
addr_hit[26]	Covered	T6,T7,T8
addr_hit[27]	Covered	T6,T7,T8
addr_hit[28]	Covered	T6,T7,T8
addr_hit[29]	Covered	T6,T7,T8
addr_hit[30]	Covered	T6,T7,T8
addr_hit[31]	Covered	T6,T7,T8
addr_hit[32]	Covered	T6,T7,T8
addr_hit[33]	Covered	T6,T7,T8
addr_hit[34]	Covered	T6,T7,T8
addr_hit[35]	Covered	T6,T7,T8
addr_hit[36]	Covered	T6,T7,T8
addr_hit[37]	Covered	T6,T7,T8
addr_hit[38]	Covered	T6,T7,T8
addr_hit[39]	Covered	T6,T7,T8
addr_hit[40]	Covered	T6,T7,T8
addr_hit[41]	Covered	T6,T7,T8
addr_hit[42]	Covered	T6,T7,T8
default	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	7078	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[5]	Covered	T6,T7,T8
addr_hit[6]	Covered	T6,T7,T8
addr_hit[7]	Covered	T6,T7,T8
addr_hit[8]	Covered	T6,T7,T8
addr_hit[9]	Covered	T6,T7,T8
addr_hit[10]	Covered	T6,T7,T8
addr_hit[11]	Covered	T6,T7,T8
addr_hit[12]	Covered	T6,T7,T8
addr_hit[13]	Covered	T6,T7,T8
addr_hit[14]	Covered	T6,T7,T8
addr_hit[15]	Covered	T6,T7,T8
addr_hit[17]	Covered	T6,T7,T8
addr_hit[18]	Covered	T6,T7,T8
addr_hit[19]	Covered	T6,T7,T8
addr_hit[20]	Covered	T6,T7,T8
addr_hit[21]	Covered	T6,T7,T8
addr_hit[22]	Covered	T6,T7,T8
addr_hit[23]	Covered	T6,T7,T8
addr_hit[24]	Covered	T6,T7,T8
addr_hit[25]	Covered	T6,T7,T8
addr_hit[26]	Covered	T6,T7,T8
addr_hit[27]	Covered	T6,T7,T8
addr_hit[28]	Covered	T6,T7,T8
addr_hit[29]	Covered	T6,T7,T8
addr_hit[30]	Covered	T6,T7,T8
addr_hit[31]	Covered	T6,T7,T8
addr_hit[32]	Covered	T6,T7,T8
addr_hit[33]	Covered	T6,T7,T8
addr_hit[34]	Covered	T6,T7,T8
addr_hit[35]	Covered	T6,T7,T8
addr_hit[36]	Covered	T6,T7,T8
addr_hit[37]	Covered	T6,T7,T8
addr_hit[38]	Covered	T6,T7,T8
addr_hit[39]	Covered	T6,T7,T8
addr_hit[40]	Covered	T6,T7,T8
addr_hit[41]	Covered	T6,T7,T8
addr_hit[42]	Covered	T6,T7,T8
default	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
en2addrHit	1273447815	258791	0	0
reAfterRv	1273447815	258787	0	0
rePulse	1273447815	132571	0	0
wePulse	1273447815	126216	0	0

en2addrHit

Name	Attempts	Real Successes	Failures	Incomplete
Total	1273447815	258791	0	0
T1	99621	83	0	0
T2	48994	84	0	0
T6	58826	22	0	0
T7	57869	60	0	0
T8	193164	22	0	0
T45	52732	38	0	0
T46	185059	22	0	0
T47	51706	60	0	0
T48	199056	83	0	0
T49	50948	20	0	0

reAfterRv

Name	Attempts	Real Successes	Failures	Incomplete
Total	1273447815	258787	0	0
T1	99621	83	0	0
T2	48994	84	0	0
T6	58826	22	0	0
T7	57869	60	0	0
T8	193164	22	0	0
T45	52732	38	0	0
T46	185059	22	0	0
T47	51706	60	0	0
T48	199056	83	0	0
T49	50948	20	0	0

rePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	1273447815	132571	0	0
T1	99621	42	0	0
T2	48994	42	0	0
T6	58826	11	0	0
T7	57869	14	0	0
T8	193164	11	0	0
T45	52732	19	0	0
T46	185059	11	0	0
T47	51706	42	0	0
T48	199056	42	0	0
T49	50948	10	0	0

wePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	1273447815	126216	0	0
T1	99621	41	0	0
T2	48994	42	0	0
T6	58826	11	0	0
T7	57869	46	0	0
T8	193164	11	0	0
T45	52732	19	0	0
T46	185059	11	0	0
T47	51706	18	0	0
T48	199056	41	0	0
T49	50948	10	0	0