Module Definition
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Module : tlul_adapter_reg
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_reg_0.1/rtl/tlul_adapter_reg.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_reg.u_reg_if 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_reg_if

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.28 97.10 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_err 100.00 100.00 100.00 100.00 100.00
u_rsp_intg_gen 83.33 66.67 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : tlul_adapter_reg
Line No.TotalCoveredPercent
TOTAL3737100.00
CONT_ASSIGN7711100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8311100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN8611100.00
CONT_ASSIGN9111100.00
ALWAYS9566100.00
ALWAYS10188100.00
ALWAYS14166100.00
CONT_ASSIGN14911100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN20411100.00
CONT_ASSIGN20811100.00
CONT_ASSIGN21111100.00
ALWAYS21833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_reg_0.1/rtl/tlul_adapter_reg.sv' or '../src/lowrisc_tlul_adapter_reg_0.1/rtl/tlul_adapter_reg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
77 1 1
78 1 1
80 1 1
81 1 1
83 1 1
84 1 1
85 1 1
86 1 1
91 1 1
95 2 2
96 2 2
97 2 2
MISSING_ELSE
101 1 1
102 1 1
103 1 1
104 1 1
105 1 1
106 1 1
107 1 1
109 1 1
MISSING_ELSE
141 1 1
142 1 1
143 1 1
144 1 1
145 1 1
146 1 1
MISSING_ELSE
149 1 1
150 1 1
204 1 1
208 1 1
211 1 1
218 1 1
220 1 1
223 1 1


Cond Coverage for Module : tlul_adapter_reg
TotalCoveredPercent
Conditions1111100.00
Logical1111100.00
Non-Logical00
Event00

 LINE       109
 EXPRESSION (rd_req ? AccessAckData : AccessAck)
             ---1--
-1-StatusTests
0CoveredT14,T15,T16
1CoveredT14,T15,T16

 LINE       145
 EXPRESSION ((error_i || err_internal || wr_req) ? '1 : rdata_i)
             -----------------1-----------------
-1-StatusTests
0CoveredT14,T15,T16
1CoveredT14,T15,T16

 LINE       145
 SUB-EXPRESSION (error_i || err_internal || wr_req)
                 ---1---    ------2-----    ---3--
-1--2--3-StatusTests
000CoveredT14,T15,T16
001CoveredT14,T15,T16
010CoveredT18,T23,T141
100CoveredT16,T141,T142

 LINE       146
 EXPRESSION (error_i || err_internal)
             ---1---    ------2-----
-1--2-StatusTests
00CoveredT14,T15,T16
01CoveredT18,T23,T141
10CoveredT16,T23,T141

Branch Coverage for Module : tlul_adapter_reg
Line No.TotalCoveredPercent
Branches 14 14 100.00
IF 95 4 4 100.00
IF 101 4 4 100.00
IF 218 2 2 100.00
IF 141 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_reg_0.1/rtl/tlul_adapter_reg.sv' or '../src/lowrisc_tlul_adapter_reg_0.1/rtl/tlul_adapter_reg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 95 if ((!rst_ni)) -2-: 96 if (a_ack) -3-: 97 if (d_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T14,T15,T16
0 1 - Covered T14,T15,T16
0 0 1 Covered T14,T15,T16
0 0 0 Covered T14,T15,T16


LineNo. Expression -1-: 101 if ((!rst_ni)) -2-: 105 if (a_ack) -3-: 109 (rd_req) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T14,T15,T16
0 1 1 Covered T14,T15,T16
0 1 0 Covered T14,T15,T16
0 0 - Covered T14,T15,T16


LineNo. Expression -1-: 218 if (wr_req)

Branches:
-1-StatusTests
1 Covered T14,T15,T16
0 Covered T14,T15,T16


LineNo. Expression -1-: 141 if ((!rst_ni)) -2-: 144 if (a_ack) -3-: 145 (((error_i || err_internal) || wr_req)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T14,T15,T16
0 1 1 Covered T14,T15,T16
0 1 0 Covered T14,T15,T16
0 0 - Covered T14,T15,T16


Assert Coverage for Module : tlul_adapter_reg
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AllowedLatency_A 824 824 0 0
MatchedWidthAssert 824 824 0 0


AllowedLatency_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 824 824 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0
T22 1 1 0 0
T23 1 1 0 0

MatchedWidthAssert
NameAttemptsReal SuccessesFailuresIncomplete
Total 824 824 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0
T22 1 1 0 0
T23 1 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%