Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : sysrst_ctrl
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut 100.00 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.46 98.21 92.94 100.00 87.88 95.46 98.27


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
tb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_alert_tx[0].u_prim_alert_sender 100.00 100.00
sysrst_ctrl_csr_assert 100.00 100.00
tlul_assert_device 100.00 100.00 100.00 100.00
u_prim_flop_2sync_input 100.00 100.00 100.00
u_prim_intr_hw 100.00 100.00 100.00
u_prim_sync_reqack 100.00 100.00 100.00 100.00
u_reg 97.47 99.37 94.45 96.06 100.00
u_sysrst_ctrl_autoblock 96.64 96.15 90.91 100.00 96.15 100.00
u_sysrst_ctrl_combo 96.79 97.39 90.00 100.00 96.55 100.00
u_sysrst_ctrl_keyintr 87.68 91.59 81.50 82.14 89.64 93.55
u_sysrst_ctrl_pin 100.00 100.00 100.00 100.00
u_sysrst_ctrl_ulp 93.92 94.44 89.74 94.44 93.10 97.87


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : sysrst_ctrl
Line No.TotalCoveredPercent
TOTAL2525100.00
CONT_ASSIGN6711100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10711100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10911100.00
CONT_ASSIGN11011100.00
CONT_ASSIGN11111100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11411100.00
CONT_ASSIGN30211100.00
CONT_ASSIGN30311100.00
CONT_ASSIGN30411100.00
CONT_ASSIGN30511100.00
CONT_ASSIGN30611100.00
CONT_ASSIGN30711100.00
CONT_ASSIGN30911100.00
CONT_ASSIGN31011100.00
CONT_ASSIGN32811100.00
CONT_ASSIGN33111100.00
CONT_ASSIGN33311100.00
ALWAYS33755100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
67 1 1
106 1 1
107 1 1
108 1 1
109 1 1
110 1 1
111 1 1
113 1 1
114 1 1
302 1 1
303 1 1
304 1 1
305 1 1
306 1 1
307 1 1
309 1 1
310 1 1
328 1 1
331 1 1
333 1 1
337 1 1
338 1 1
340 1 1
341 1 1
343 1 1


Cond Coverage for Module : sysrst_ctrl
TotalCoveredPercent
Conditions77100.00
Logical77100.00
Non-Logical00
Event00

 LINE       328
 EXPRESSION (aon_ulp_wakeup_pulse_int || aon_sysrst_ctrl_combo_intr || aon_sysrst_ctrl_key_intr)
             ------------1-----------    -------------2------------    ------------3-----------
-1--2--3-StatusTests
000CoveredT8,T47,T42
001CoveredT4,T5,T13
010CoveredT13,T14,T15
100CoveredT2,T3,T6

 LINE       343
 EXPRESSION (aon_intr_req || aon_intr_event_pulse)
             ------1-----    ----------2---------
-1--2-StatusTests
00CoveredT8,T47,T42
01CoveredT2,T3,T4
10CoveredT2,T3,T4

Toggle Coverage for Module : sysrst_ctrl
TotalCoveredPercent
Totals 47 47 100.00
Total Bits 374 374 100.00
Total Bits 0->1 187 187 100.00
Total Bits 1->0 187 187 100.00

Ports 47 47 100.00
Port Bits 374 374 100.00
Port Bits 0->1 187 187 100.00
Port Bits 1->0 187 187 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T7,T8 Yes T1,T7,T8 INPUT
clk_aon_i Yes Yes T1,T7,T8 Yes T1,T7,T8 INPUT
rst_ni Yes Yes T17,T13,T20 Yes T1,T7,T8 INPUT
rst_aon_ni Yes Yes T17,T13,T20 Yes T1,T7,T8 INPUT
tl_i.d_ready Yes Yes T1,T7,T42 Yes T1,T7,T8 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T1,T7,T8 Yes T1,T7,T8 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T7,T8 Yes T1,T7,T8 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T7,T13,T25 Yes T7,T13,T25 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T1,T7,T8 Yes T1,T7,T8 INPUT
tl_i.a_mask[3:0] Yes Yes T7,T8,T42 Yes T7,T8,T42 INPUT
tl_i.a_address[31:0] Yes Yes T7,T42,T2 Yes T7,T42,T2 INPUT
tl_i.a_source[7:0] Yes Yes T1,T7,T8 Yes T1,T7,T8 INPUT
tl_i.a_size[1:0] Yes Yes T7,T8,T47 Yes T7,T8,T47 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T1,T7,T8 Yes T1,T7,T8 INPUT
tl_i.a_valid Yes Yes T1,T7,T8 Yes T1,T7,T8 INPUT
tl_o.a_ready Yes Yes T1,T7,T8 Yes T1,T7,T8 OUTPUT
tl_o.d_error Yes Yes T7,T13,T25 Yes T7,T13,T25 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T1,T8,T42 Yes T1,T8,T42 OUTPUT
tl_o.d_user.rsp_intg[5:0] Yes Yes *T1,T7,*T8 Yes T1,T7,T8 OUTPUT
tl_o.d_user.rsp_intg[6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_data[31:0] Yes Yes T1,T7,T8 Yes T1,T7,T8 OUTPUT
tl_o.d_sink Unreachable Unreachable Unreachable OUTPUT
tl_o.d_source[7:0] Yes Yes T1,T7,T8 Yes T1,T7,T8 OUTPUT
tl_o.d_size[1:0] Yes Yes T7,T8,T47 Yes T7,T8,T47 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T1,*T7,*T8 Yes T1,T7,T8 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T1,T7,T8 Yes T1,T7,T8 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T7,T8 Yes T1,T7,T8 INPUT
alert_rx_i[0].ack_p Yes Yes T1,T130,T131 Yes T1,T130,T131 INPUT
alert_rx_i[0].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[0].ping_p Unreachable Unreachable Unreachable INPUT
alert_tx_o[0].alert_n Yes Yes T1,T7,T8 Yes T1,T7,T8 OUTPUT
alert_tx_o[0].alert_p Yes Yes T1,T130,T131 Yes T1,T130,T131 OUTPUT
wkup_req_o Yes Yes T2,T3,T6 Yes T2,T3,T4 OUTPUT
aon_sysrst_ctrl_rst_req_o Yes Yes T13,T20,T14 Yes T13,T20,T14 OUTPUT
intr_sysrst_ctrl_o Yes Yes T2,T3,T13 Yes T2,T3,T13 OUTPUT
cio_ac_present_i Yes Yes T47,T42,T2 Yes T47,T42,T2 INPUT
cio_ec_rst_l_i Yes Yes T47,T42,T70 Yes T47,T42,T70 INPUT
cio_key0_in_i Yes Yes T47,T42,T70 Yes T47,T42,T70 INPUT
cio_key1_in_i Yes Yes T47,T42,T70 Yes T47,T42,T70 INPUT
cio_key2_in_i Yes Yes T47,T42,T70 Yes T47,T42,T70 INPUT
cio_pwrb_in_i Yes Yes T8,T47,T42 Yes T8,T47,T42 INPUT
cio_lid_open_i Yes Yes T47,T42,T2 Yes T47,T42,T2 INPUT
cio_flash_wp_l_i Yes Yes T47,T42,T70 Yes T47,T42,T70 INPUT
cio_bat_disable_o Yes Yes T1,T47,T42 Yes T1,T47,T42 OUTPUT
cio_flash_wp_l_o Yes Yes T47,T48,T13 Yes T47,T48,T13 OUTPUT
cio_ec_rst_l_o Yes Yes T48,T13,T32 Yes T17,T48,T13 OUTPUT
cio_key0_out_o Yes Yes T1,T47,T42 Yes T1,T47,T42 OUTPUT
cio_key1_out_o Yes Yes T1,T47,T42 Yes T1,T47,T42 OUTPUT
cio_key2_out_o Yes Yes T1,T8,T47 Yes T1,T8,T47 OUTPUT
cio_pwrb_out_o Yes Yes T1,T8,T47 Yes T1,T8,T47 OUTPUT
cio_z3_wakeup_o Yes Yes T1,T47,T42 Yes T1,T47,T42 OUTPUT
cio_bat_disable_en_o Unreachable Unreachable Unreachable OUTPUT
cio_flash_wp_l_en_o Unreachable Unreachable Unreachable OUTPUT
cio_ec_rst_l_en_o Unreachable Unreachable Unreachable OUTPUT
cio_key0_out_en_o Unreachable Unreachable Unreachable OUTPUT
cio_key1_out_en_o Unreachable Unreachable Unreachable OUTPUT
cio_key2_out_en_o Unreachable Unreachable Unreachable OUTPUT
cio_pwrb_out_en_o Unreachable Unreachable Unreachable OUTPUT
cio_z3_wakeup_en_o Unreachable Unreachable Unreachable OUTPUT

*Tests covering at least one bit in the range

Branch Coverage for Module : sysrst_ctrl
Line No.TotalCoveredPercent
Branches 3 3 100.00
IF 337 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 337 if ((~rst_aon_ni)) -2-: 340 if (aon_intr_ack)

Branches:
-1--2-StatusTests
1 - Covered T8,T47,T42
0 1 Covered T2,T3,T4
0 0 Covered T8,T47,T42


Assert Coverage for Module : sysrst_ctrl
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 23 23 100.00 23 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 23 23 100.00 23 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AlertKnown_A 351519555 351104424 0 0
BatOEnIsOne_A 351519555 351104424 0 0
BatOKnown_A 351519555 351104424 0 0
ECRSTOEnIsOne_A 351519555 351104424 0 0
ECRSTOKnown_A 351519555 351104424 0 0
FlashWpOEnIsOne_A 351519555 351104424 0 0
FlashWpOKnown_A 351519555 351104424 0 0
FpvSecCmRegWeOnehotCheck_A 351519555 80 0 0
IntrSysRstCtrlOKnown_A 351519555 351104424 0 0
Key0OEnIsOne_A 351519555 351104424 0 0
Key0OKnown_A 351519555 351104424 0 0
Key1OEnIsOne_A 351519555 351104424 0 0
Key1OKnown_A 351519555 351104424 0 0
Key2OEnIsOne_A 351519555 351104424 0 0
Key2OKnown_A 351519555 351104424 0 0
OTRstOKnown_A 351519555 351104424 0 0
OTWkOKnown_A 351519555 351104424 0 0
PwrbOEnIsOne_A 351519555 351104424 0 0
PwrbOKnown_A 351519555 351104424 0 0
TlOAReadyKnown_A 351519555 351104424 0 0
TlODValidKnown_A 351519555 351104424 0 0
Z3WakeupOEnIsOne_A 351519555 351104424 0 0
Z3WwakupOKnown_A 351519555 351104424 0 0


AlertKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 351519555 351104424 0 0
T2 13584 13519 0 0
T3 25288 25235 0 0
T8 69961 69898 0 0
T16 30613 30555 0 0
T17 665683 665363 0 0
T34 3393 3323 0 0
T42 11059 11004 0 0
T47 59246 59175 0 0
T70 11477 11388 0 0
T71 5900 5813 0 0

BatOEnIsOne_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 351519555 351104424 0 0
T2 13584 13519 0 0
T3 25288 25235 0 0
T8 69961 69898 0 0
T16 30613 30555 0 0
T17 665683 665363 0 0
T34 3393 3323 0 0
T42 11059 11004 0 0
T47 59246 59175 0 0
T70 11477 11388 0 0
T71 5900 5813 0 0

BatOKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 351519555 351104424 0 0
T2 13584 13519 0 0
T3 25288 25235 0 0
T8 69961 69898 0 0
T16 30613 30555 0 0
T17 665683 665363 0 0
T34 3393 3323 0 0
T42 11059 11004 0 0
T47 59246 59175 0 0
T70 11477 11388 0 0
T71 5900 5813 0 0

ECRSTOEnIsOne_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 351519555 351104424 0 0
T2 13584 13519 0 0
T3 25288 25235 0 0
T8 69961 69898 0 0
T16 30613 30555 0 0
T17 665683 665363 0 0
T34 3393 3323 0 0
T42 11059 11004 0 0
T47 59246 59175 0 0
T70 11477 11388 0 0
T71 5900 5813 0 0

ECRSTOKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 351519555 351104424 0 0
T2 13584 13519 0 0
T3 25288 25235 0 0
T8 69961 69898 0 0
T16 30613 30555 0 0
T17 665683 665363 0 0
T34 3393 3323 0 0
T42 11059 11004 0 0
T47 59246 59175 0 0
T70 11477 11388 0 0
T71 5900 5813 0 0

FlashWpOEnIsOne_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 351519555 351104424 0 0
T2 13584 13519 0 0
T3 25288 25235 0 0
T8 69961 69898 0 0
T16 30613 30555 0 0
T17 665683 665363 0 0
T34 3393 3323 0 0
T42 11059 11004 0 0
T47 59246 59175 0 0
T70 11477 11388 0 0
T71 5900 5813 0 0

FlashWpOKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 351519555 351104424 0 0
T2 13584 13519 0 0
T3 25288 25235 0 0
T8 69961 69898 0 0
T16 30613 30555 0 0
T17 665683 665363 0 0
T34 3393 3323 0 0
T42 11059 11004 0 0
T47 59246 59175 0 0
T70 11477 11388 0 0
T71 5900 5813 0 0

FpvSecCmRegWeOnehotCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 351519555 80 0 0
T130 192733 20 0 0
T131 400674 20 0 0
T132 103934 20 0 0
T133 174272 10 0 0
T134 198324 10 0 0

IntrSysRstCtrlOKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 351519555 351104424 0 0
T2 13584 13519 0 0
T3 25288 25235 0 0
T8 69961 69898 0 0
T16 30613 30555 0 0
T17 665683 665363 0 0
T34 3393 3323 0 0
T42 11059 11004 0 0
T47 59246 59175 0 0
T70 11477 11388 0 0
T71 5900 5813 0 0

Key0OEnIsOne_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 351519555 351104424 0 0
T2 13584 13519 0 0
T3 25288 25235 0 0
T8 69961 69898 0 0
T16 30613 30555 0 0
T17 665683 665363 0 0
T34 3393 3323 0 0
T42 11059 11004 0 0
T47 59246 59175 0 0
T70 11477 11388 0 0
T71 5900 5813 0 0

Key0OKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 351519555 351104424 0 0
T2 13584 13519 0 0
T3 25288 25235 0 0
T8 69961 69898 0 0
T16 30613 30555 0 0
T17 665683 665363 0 0
T34 3393 3323 0 0
T42 11059 11004 0 0
T47 59246 59175 0 0
T70 11477 11388 0 0
T71 5900 5813 0 0

Key1OEnIsOne_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 351519555 351104424 0 0
T2 13584 13519 0 0
T3 25288 25235 0 0
T8 69961 69898 0 0
T16 30613 30555 0 0
T17 665683 665363 0 0
T34 3393 3323 0 0
T42 11059 11004 0 0
T47 59246 59175 0 0
T70 11477 11388 0 0
T71 5900 5813 0 0

Key1OKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 351519555 351104424 0 0
T2 13584 13519 0 0
T3 25288 25235 0 0
T8 69961 69898 0 0
T16 30613 30555 0 0
T17 665683 665363 0 0
T34 3393 3323 0 0
T42 11059 11004 0 0
T47 59246 59175 0 0
T70 11477 11388 0 0
T71 5900 5813 0 0

Key2OEnIsOne_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 351519555 351104424 0 0
T2 13584 13519 0 0
T3 25288 25235 0 0
T8 69961 69898 0 0
T16 30613 30555 0 0
T17 665683 665363 0 0
T34 3393 3323 0 0
T42 11059 11004 0 0
T47 59246 59175 0 0
T70 11477 11388 0 0
T71 5900 5813 0 0

Key2OKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 351519555 351104424 0 0
T2 13584 13519 0 0
T3 25288 25235 0 0
T8 69961 69898 0 0
T16 30613 30555 0 0
T17 665683 665363 0 0
T34 3393 3323 0 0
T42 11059 11004 0 0
T47 59246 59175 0 0
T70 11477 11388 0 0
T71 5900 5813 0 0

OTRstOKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 351519555 351104424 0 0
T2 13584 13519 0 0
T3 25288 25235 0 0
T8 69961 69898 0 0
T16 30613 30555 0 0
T17 665683 665363 0 0
T34 3393 3323 0 0
T42 11059 11004 0 0
T47 59246 59175 0 0
T70 11477 11388 0 0
T71 5900 5813 0 0

OTWkOKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 351519555 351104424 0 0
T2 13584 13519 0 0
T3 25288 25235 0 0
T8 69961 69898 0 0
T16 30613 30555 0 0
T17 665683 665363 0 0
T34 3393 3323 0 0
T42 11059 11004 0 0
T47 59246 59175 0 0
T70 11477 11388 0 0
T71 5900 5813 0 0

PwrbOEnIsOne_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 351519555 351104424 0 0
T2 13584 13519 0 0
T3 25288 25235 0 0
T8 69961 69898 0 0
T16 30613 30555 0 0
T17 665683 665363 0 0
T34 3393 3323 0 0
T42 11059 11004 0 0
T47 59246 59175 0 0
T70 11477 11388 0 0
T71 5900 5813 0 0

PwrbOKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 351519555 351104424 0 0
T2 13584 13519 0 0
T3 25288 25235 0 0
T8 69961 69898 0 0
T16 30613 30555 0 0
T17 665683 665363 0 0
T34 3393 3323 0 0
T42 11059 11004 0 0
T47 59246 59175 0 0
T70 11477 11388 0 0
T71 5900 5813 0 0

TlOAReadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 351519555 351104424 0 0
T2 13584 13519 0 0
T3 25288 25235 0 0
T8 69961 69898 0 0
T16 30613 30555 0 0
T17 665683 665363 0 0
T34 3393 3323 0 0
T42 11059 11004 0 0
T47 59246 59175 0 0
T70 11477 11388 0 0
T71 5900 5813 0 0

TlODValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 351519555 351104424 0 0
T2 13584 13519 0 0
T3 25288 25235 0 0
T8 69961 69898 0 0
T16 30613 30555 0 0
T17 665683 665363 0 0
T34 3393 3323 0 0
T42 11059 11004 0 0
T47 59246 59175 0 0
T70 11477 11388 0 0
T71 5900 5813 0 0

Z3WakeupOEnIsOne_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 351519555 351104424 0 0
T2 13584 13519 0 0
T3 25288 25235 0 0
T8 69961 69898 0 0
T16 30613 30555 0 0
T17 665683 665363 0 0
T34 3393 3323 0 0
T42 11059 11004 0 0
T47 59246 59175 0 0
T70 11477 11388 0 0
T71 5900 5813 0 0

Z3WwakupOKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 351519555 351104424 0 0
T2 13584 13519 0 0
T3 25288 25235 0 0
T8 69961 69898 0 0
T16 30613 30555 0 0
T17 665683 665363 0 0
T34 3393 3323 0 0
T42 11059 11004 0 0
T47 59246 59175 0 0
T70 11477 11388 0 0
T71 5900 5813 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%